CN108231538A - 薄膜沉积方法 - Google Patents

薄膜沉积方法 Download PDF

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CN108231538A
CN108231538A CN201711293365.8A CN201711293365A CN108231538A CN 108231538 A CN108231538 A CN 108231538A CN 201711293365 A CN201711293365 A CN 201711293365A CN 108231538 A CN108231538 A CN 108231538A
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deposition
gas
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赵炳哲
李相镇
李仁焕
陈光善
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YUANYI IPS CORP
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Abstract

本发明一实施例的薄膜沉积方法包括:提供形成图案的基板的步骤;表面处理步骤,利用沉积抑制气体形成沉积抑制层,所述沉积抑制气体用于抑制在所述图案上端的薄膜沉积;薄膜沉积步骤,利用工艺气体在包括所述表面处理的所述图案上沉积所述薄膜;其中,所述沉积抑制气体为包括氟的气体。

Description

薄膜沉积方法
技术领域
本发明涉及半导体装置制造方法,更详细地说涉及薄膜沉积方法。
背景技术
半导体装置可指在晶片形成的多个电子元件的组合品。
半导体装置制造工艺中,薄膜沉积是指在晶片上物理性形成导电性、绝缘性、半导体物质等的工艺。
用于沉积薄膜的代表性方法可有ALD(Atomic Layer Deposition,原子层沉积)方法和CVD(Chemical Vapor Deposition,化学气相沉积)方法。
CVD方法是通过反应两种气体来沉积薄膜的方式,可细分为LPCVD(Low PressureCVD,低压化学气相沉积)、PECVD(Plasma Enhanced CVD,等离子体增强化学气相沉积)等。ALD方法是一层一层沉积原子的工艺,可利用于要求细分化工艺的地方。
另一方面,前体(Precursor)是指在金属结合配体的物质,随着半导体工艺的细分化,正在活跃的使用利用前体的薄膜沉积方式。
但是,目前的实情是半导体装置的设计规则正在持续减少,同时正在持续要求能够满足在这一条件下要求的膜特性的薄膜沉积方法。
发明内容
本发明一实施例的薄膜沉积方法包括:提供形成图案的基板的步骤;表面处理步骤,利用沉积抑制气体形成沉积抑制层,所述沉积抑制气体用于抑制在所述图案上端的薄膜沉积;薄膜沉积步骤,在所述表面处理的所述图案上利用工艺气体沉积所述薄膜;其中所述沉积抑制气体为包含氟的气体。
附图说明
图1是用于说明一实施例的薄膜沉积方法的流程图。
图2a至2e是用于说明一实施例的薄膜沉积方法的剖面图。
图3是用于说明一实施例的薄膜沉积方法的流程图。
图4a至图4b是用于说明一实施例的薄膜沉积方法的剖面图。
图5是用于说明根据沉积抑制气体的分布以及位置而体现出薄膜沉积速度的差异的图面。
具体实施方式
以下,参照附图详细说明本发明的实施例。
图1是用于说明一实施例的薄膜沉积方法的流程图;图2a至2e是用于说明一实施例的薄膜沉积方法的剖面图。
首先,如图2a,可向基板沉积腔室内提供形成下部结构103的基板101。
在一实施例中,下部结构103可以是具有通孔、沟槽、接触孔等纵横比(Aspectratio)的图案,在这一情况下,在下部结构103可包括孔105。
为了只在基板101的目标部分沉积薄膜,可供应沉积抑制气体(S101)。在供应沉积抑制气体之后可实施吹扫。
在一实施例中,若待沉积的薄膜为包含硅(Si)的金属有机(Metal Organic;MO)化合物,则沉积抑制气体可以是包含氟的前体。
对于包含氟前体,与氟一同可选自在包含氧(O)、碳(C)、氢(H)、氮(N)中的至少一个的物质中。在一实施例中,包含氟的前体可选自包含NF3、F2、CF4、CHF的群组中,但不限于此。
如图2b所示,沉积抑制层107是不使目标薄膜沉积而选定的区域(沉积避免区域),例如,可附着在下部结构103的上端。为此,可控制向腔室内供应的沉积抑制气体的流量、供应时间、供应压力等。
通过供应沉积抑制气体,基板101的表面变成包含氟(F)疏水性,进而可降低沉积前体(例如,硅前体)附着于基板101表面的概率。
在沉积避免区域形成沉积抑制层107的表面处理过程之后,可在未形成沉积抑制层107的区域(沉积区域)形成薄膜。例如,能够以ALD方法沉积薄膜。
更详细地说,对腔室供应沉积前体,(即,第一工艺气体(源气体)),使该沉积前体吸附于沉积区域表面后可进行吹扫。
若目标薄膜为包含硅的金属有机化合物,则沉积前体可以是金属有机(MO)前体。
之后,将第二工艺气体(反应气体)供应于腔室内,与已吸附的第一工艺气体反应之后进行吹扫(S105),可在未形成沉积抑制层107的区域(沉积区域)(例如,孔105内部)沉积薄膜109(参照图2c)。
在一实施例中,作为第一工艺气体的源气体选自包含硅的群组中。同时,作为第二工艺气体的反应气体可选自O2等离子、H20、H2O2、O3中,或者可选自NH3、N2中。
通过供应源气体(S103)以及供应反应气体(S105)沉积目标薄膜的过程可以是反复指定次数(m次)的循环沉积过程,直至薄膜的厚度达到已设定的目标厚度为止(S107)。
据此,如图2d所示,可在沉积区域形成具有目标厚度的薄膜109。在一实施例中,薄膜109可形成能够填埋于孔105内部的厚度。
然后,清除在沉积避免区域上形成的沉积抑制层107(S109),进而可制造如图2e的半导体装置。
在一实施例中,可通过还原剂或者等离子处理清除沉积抑制层107。还原剂可以是包含羟基(-OH)的还原剂,但是不限于此。等离子处理可利用氩(Ar)来执行,但不限于此。
通过本发明的技术,在填埋具有纵横比的下部结构图案的孔内时,在图案上端提前形成沉积抑制层,之后可利用源气体(沉积前体)与反应气体填埋孔内部。根据选择性地只填埋孔内部,可形成不引起缝隙和空隙的优质薄膜。
图3是用于说明一实施例的薄膜沉积方法的流程图;图4a至图4b是用于说明一实施例的薄膜沉积方法的剖面图。
首先,可提供形成下部结构103的基板101,其中所述下部结构103包括具有纵横比的图案。
对于所述基板,通过步骤S201~S209的过程,可只在基板101的目标部分沉积第一薄膜109A(参照图2e)
对于步骤S201~S209的过程,与图1示出的步骤S101~S109实际上相同,因此省略详细说明。
在孔内形成第一薄膜109A并且清除沉积抑制层107,之后对腔室内重新供应并吸附源气体(第一工艺气体)作为沉积前体之后进行吹扫(S211)。接着,向腔室内供应反应气体(第二工艺气体)与第一工艺气体反应之后可进行吹扫(S213)。
据此,如图4a所示,在形成下部结构103以及第一薄膜109A的整体结构上部可沉积第二薄膜111。
通过供应源气体(S211)以及供应反应气体(S213)沉积目标薄膜的过程可以是反复指定次数(n次)的循环沉积过程直至薄膜厚度达到已设定的目标厚度为止(S215)。
据此,如图4b所示,在整体结构上部可形成具有目标厚度的第二薄膜111。在一实施例中,第二薄膜111可由与第一薄膜109A相同的物质或者不同的物质构成。
在本实施例中,对于形成具有纵横比的下部结构图案的基板,用第一薄膜填埋下部结构图案内的孔,之后在已填埋孔的下部结构上可形成指定厚度的第二薄膜。
在形成第二薄膜之前,可处于孔内部被第一薄膜完全填埋的状态,因此能够提高半导体装置的成品率和可靠性。
图5是用于说明根据沉积抑制气体的分布以及位置而体现出薄膜沉积速度的差异的图面。
参照图5,可以知道根据对图案201表面的沉积抑制气体203分布以及位置,薄膜205(例如,氧化硅膜)的沉积速度有所不同。
即,如图5(a)所示,可控制沉积抑制气体203的供应量,使图案201的上端供应量多于内部。可调节沉积抑制气体203供应时间或者供应量等,以使对图案201不同地分布沉积抑制气体203。
在这一情况下,如图5(b)所示,从沉积抑制气体203分布相对少的图案201的内侧开始沉积薄膜205。如图5(c)所示,随着沉积工艺持续进行图案201内部被薄膜205填充。
然后,若减少沉积抑制气体203的量或者清除附着于图案201表面的沉积抑制气体203之后继续进行沉积工艺,则薄膜205的生长速度提高的同时可在图案201上端沉积目标厚度的薄膜205。
据此,可形成没有缝隙(seam)或者空隙(void)的薄膜。
图5(e)是随着时间的推移的薄膜205沉积速度。如图5(b),可以知道在几乎未附着沉积抑制气体203附着的图案201内侧底部沉积薄膜205的速度(A)、在附着预定量的沉积抑制气体203的图案201内侧上侧沉积薄膜205的速度(B)、在附着大量沉积抑制气体203的图案201上部表面沉积薄膜205的速度(C)相互不同,并且可以了解到薄膜的沉积速度与沉积抑制气体203的附着量成反比。
在一实施例中,无需通过沉积抑制气体203的清除沉积抑制层203的过程,也能够反复执行供应沉积制气体、吹扫、供应第一工艺气体的、吹扫、供应第二工艺气体、吹扫的过程的沉积。

Claims (13)

1.一种薄膜沉积方法,其特征在于,包括:
提供形成图案的基板的步骤;
表面处理步骤,利用包含氟的沉积抑制气体形成沉积抑制层,所述沉积抑制层用于抑制在所述图案上端的薄膜沉积;以及
薄膜沉积步骤,利用工艺气体在包括所述表面处理后的所述图案的所述基板上沉积所述薄膜。
2.根据权利要求1所述的薄膜沉积方法,其特征在于,
所述图案形成具有纵横比的形状,并且包括通孔、沟槽、接触孔。
3.根据权利要求1所述的薄膜沉积方法,其特征在于,
所述薄膜沉积步骤包括:
吸附步骤,对所述表面处理后的所述图案上提供所述第一供应气体,并吸附所述第一工艺气体;
第一吹扫步骤,吹扫所述第一工艺气体;
反应步骤,对所述图案上提供第二工艺气体以与所述第一工艺气体反应;以及
第二吹扫步骤,吹扫所述第二工艺气体。
4.根据权利要求3所述的薄膜沉积方法,其特征在于,
所述第一工艺气体选自包含硅的金属有机化合物中。
5.根据权利要求3所述的薄膜沉积方法,其特征在于,
所述第二工艺气体选自O2等离子、H20、H2O2、O3中。
6.根据权利要求3所述的薄膜沉积方法,其特征在于,
所述第二工艺气体选自NH3,N2中。
7.根据权利要求1所述的薄膜沉积方法,其特征在于,
所述沉积抑制气体包含所述氟,并且选自还包含氧、碳、氢、氮中的至少一个的物质中。
8.根据权利要求1所述的薄膜沉积方法,其特征在于,
所述沉积抑制气体选自包含NF3,F2,CF4,CHF的群组中。
9.根据权利要求1所述的薄膜沉积方法,其特征在于,
所述表面处理步骤执行一次,所述薄膜沉积步骤为多次沉积第一薄膜的循环沉积步骤;
所述表面处理步骤以及所述循环沉积步骤执行多次。
10.根据权利要求1所述的薄膜沉积方法,其特征在于,还包括:
还原步骤,在所述循环沉积步骤之后清除所述沉积抑制层;以及
第二循环沉积步骤,在清除所述沉积抑制层的整体结构上部多次沉积第二薄膜;
所述表面处理步骤执行一次,所述薄膜沉积步骤为多次沉积第一薄膜的第一循环沉积步骤。
11.根据权利要求10所述的薄膜沉积方法,其特征在于,
所述还原步骤利用包含羟基的还原剂执行,所述羟基为-OH。
12.根据权利要求10所述的薄膜沉积方法,其特征在于,
所述还原步骤包括利用氩的等离子处理步骤。
13.根据权利要求10所述的薄膜沉积方法,其特征在于,
所述第二薄膜由与所述第一薄膜相同的物质或者不同的物质构成。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10781519B2 (en) * 2018-06-18 2020-09-22 Tokyo Electron Limited Method and apparatus for processing substrate
KR20210117344A (ko) * 2019-02-14 2021-09-28 램 리써치 코포레이션 희생 마스크 (sacrificial mask) 를 사용하는 선택적인 에칭
JP6953480B2 (ja) * 2019-07-31 2021-10-27 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置、およびプログラム
JP7118099B2 (ja) * 2020-01-15 2022-08-15 株式会社Kokusai Electric 半導体装置の製造方法、基板処理装置およびプログラム
JP7305700B2 (ja) * 2021-04-19 2023-07-10 株式会社Kokusai Electric 基板処理方法、半導体装置の製造方法、基板処理装置、およびプログラム
JP2023118554A (ja) * 2022-02-15 2023-08-25 東京エレクトロン株式会社 シリコン窒化膜の形成方法及び成膜装置
JP2024042235A (ja) * 2022-09-15 2024-03-28 株式会社Kokusai Electric 基板処理方法、半導体装置の製造方法、基板処理装置、およびプログラム
JP2024047283A (ja) * 2022-09-26 2024-04-05 株式会社Kokusai Electric 基板処理方法、半導体装置の製造方法、プログラム、および基板処理装置
WO2024069683A1 (ja) * 2022-09-26 2024-04-04 株式会社Kokusai Electric 基板処理方法、半導体装置の製造方法、基板処理装置およびプログラム

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19638171C1 (de) * 1996-08-26 1997-09-04 Fraunhofer Ges Forschung In-situ-Plasmavorbehandlung zur TEOS-Siliziumoxid-Abscheidung
US6342421B1 (en) * 1994-09-13 2002-01-29 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US7211525B1 (en) * 2005-03-16 2007-05-01 Novellus Systems, Inc. Hydrogen treatment enhanced gap fill
CN101868762A (zh) * 2007-11-20 2010-10-20 伊斯曼柯达公司 含硅氧烷的可光图案化沉积抑制剂
KR20110052475A (ko) * 2009-11-12 2011-05-18 주식회사 아토 갭필 방법
US20120276721A1 (en) * 2011-04-28 2012-11-01 Samsung Electronics Co., Ltd. Method of forming an oxide layer and method of manufacturing semiconductor device including the oxide layer
CN104928654A (zh) * 2014-02-26 2015-09-23 朗姆研究公司 用于无缝特征填充的抑制剂等离子体介导的原子层沉积
WO2016147941A1 (ja) * 2015-03-13 2016-09-22 株式会社村田製作所 原子層堆積阻害材料

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000044876A (ko) * 1998-12-30 2000-07-15 김영환 반도체 소자의 금속배선 형성 방법
KR100585011B1 (ko) * 2000-06-30 2006-05-29 주식회사 하이닉스반도체 반도체 소자의 게이트전극 형성 방법
US9378971B1 (en) * 2014-12-04 2016-06-28 Lam Research Corporation Technique to deposit sidewall passivation for high aspect ratio cylinder etch
JP6545094B2 (ja) * 2015-12-17 2019-07-17 東京エレクトロン株式会社 成膜方法及び成膜装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6342421B1 (en) * 1994-09-13 2002-01-29 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
DE19638171C1 (de) * 1996-08-26 1997-09-04 Fraunhofer Ges Forschung In-situ-Plasmavorbehandlung zur TEOS-Siliziumoxid-Abscheidung
US7211525B1 (en) * 2005-03-16 2007-05-01 Novellus Systems, Inc. Hydrogen treatment enhanced gap fill
CN101868762A (zh) * 2007-11-20 2010-10-20 伊斯曼柯达公司 含硅氧烷的可光图案化沉积抑制剂
KR20110052475A (ko) * 2009-11-12 2011-05-18 주식회사 아토 갭필 방법
US20120276721A1 (en) * 2011-04-28 2012-11-01 Samsung Electronics Co., Ltd. Method of forming an oxide layer and method of manufacturing semiconductor device including the oxide layer
CN104928654A (zh) * 2014-02-26 2015-09-23 朗姆研究公司 用于无缝特征填充的抑制剂等离子体介导的原子层沉积
WO2016147941A1 (ja) * 2015-03-13 2016-09-22 株式会社村田製作所 原子層堆積阻害材料

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