CN108122988A - 折叠通道沟槽mosfet - Google Patents

折叠通道沟槽mosfet Download PDF

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CN108122988A
CN108122988A CN201711217259.1A CN201711217259A CN108122988A CN 108122988 A CN108122988 A CN 108122988A CN 201711217259 A CN201711217259 A CN 201711217259A CN 108122988 A CN108122988 A CN 108122988A
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conduction type
concavo
epitaxial layer
convex portion
lightly doped
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CN108122988B (zh
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雷燮光
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NATIONS SEMICONDUCTOR (CAYMAN) Ltd
Alpha and Omega Semiconductor Cayman Ltd
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Abstract

一种沟槽MOSFET器件包括本体区和源极区，凹凸部分沿MOSFET器件的通道宽度方向，使得本体区和源极区的深度变化沿通道宽度方向。凹凸部分增大了MOSFET的通道宽度。

Description

折叠通道沟槽MOSFET
技术领域
本发明主要涉及集成电路，更确切地说是关于具有场效应晶体管（FET）的集成电路器件。
背景技术
场效应晶体管（FET）是半导体晶体管器件，其中电绝缘栅极所加电压控制了源极和漏极之间的电流流动。FET的一个示例是金属氧化物半导体FET（MOSFET），其中通过氧化绝缘物，使栅极电极与半导体本体区绝缘。当栅极加载电压时，所产生的电场穿通氧化物，在半导体-绝缘物交界处形成一个“反转层”或“通道”。反转层提供可以穿过电流的通道。改变栅极电压调制该层的导电性，从而控制漏极和源极之间的电流。MOSFET可以具有不同的结构。在一个示例中，MOSFET可以具有一种平面结构，其中栅极、源极和漏极在器件上方，电流在平行于表面的通路中流动。在另一个示例中，MOSFET可以具有一种垂直结构，其中用掺杂多晶硅填充的沟槽，从源极延伸到漏极，侧壁和地板都内衬一层热生长的二氧化硅。这样的沟槽MOSFET晶体管允许不收缩的电流流动，从而提供较小的比导通电阻。
FET适合多种功率开关应用。在一种电池保护电路模块（PCM）中使用的特殊结构中，两个FET背对背配置，它们的漏极在浮动结构中连接在一起。图1A表示这种结构的示意图。图1B表示这种器件100连接电池保护电路模块PCM 102、电池104以及负载或充电器106。在本例中FET 120和130充放电的栅极分别由控制器集成电路（IC）110独立驱动。这种结构允许在两个方向上控制电流：充电到电池和电池到负载。在正常的充电和放电操作中，MOSFET 120和130都接通（即导电）。在电池104发生过充电或充电过电流情况时，控制器IC110断开充电FET 120，并接通放电FET 130。在过放电或过电流情况下，控制器IC 110接通充电FET 120，并断开放电FET 130。
正是在这一背景下，提出了本发明的各种实施例。
发明内容
本发明提供一种折叠通道沟槽MOSFET，获得低通道电阻，减小源极-源极电阻。
为实现上述目的，本发明提供一种沟槽MOSFET器件，其特点是，其包含：
一个第一导电类型的轻掺杂外延层，在第一导电类型的重掺杂半导体衬底上；
一个用导电材料填充的栅极沟槽，在轻掺杂外延层中延伸；
一个与第一导电类型相反的第二导电类型的本体区，在一部分轻掺杂外延层中，其中本体区具有第一个凹凸部分，沿通道宽度方向；以及
一个第一导电类型的源极区，在本体区顶部，其中源极区具有第二个凹凸部分，在第一个凹凸部分上方沿通道宽度方向，其中MOSFET器件的通道宽度随着引入第一和第二个凹凸部分而增大。
上述第一导电类型为N型，第二导电类型为P型。
上述轻掺杂外延层、本体区和源极区的深度沿通道宽度变化。
上述轻掺杂外延层具有第三个凹凸部分，沿MOSFET器件的通道宽度方向。
上述第三个凹凸部分的深度延伸到半导体衬底中，比轻掺杂外延层的其他部分更深的地方。
上述第一个凹凸部分的深度延伸到轻掺杂外延层中，比本体区的其他部分更深的地方。
上述第二个凹凸部分的深度延伸到本体区中，比源极区的其他部分更深的地方。
上述第一个和第二个凹凸部分的锥形边缘，其角度约在25度和90度之间。
一种用于制备沟槽MOSFET器件的方法，其特点是，其包含：
在第一导电类型的重掺杂半导体衬底上，制备一个第一导电类型的轻掺杂外延层；
在轻掺杂外延层中制备一个栅极电极；
在轻掺杂外延层的一部分中，制备与第一导电类型相反的第二导电类型的本体区，其中本体区的第一个凹凸部分沿通道宽度方向；并且
在本体区顶部中，制备第一导电类型的源极区，其中源极区具有第二个凹凸部分，沿第一个凹凸部分上方的通道宽度方向。
上述第一导电类型为N型，第二导电类型为P型。
上述轻掺杂外延层具有第三个凹凸部分，沿MOSFET器件的通道宽度方向。
其中在第一导电类型的重掺杂半导体衬底上，制备一个第一导电类型的轻掺杂外延层，包含：
在半导体衬底上，制备一个第一外延层；
利用第一掩膜，制备一个掩埋层，其中第一掩膜限定第三个凹凸部分；并且
在掩埋层上，制备一个第二外延层。
其中在轻掺杂外延层中，制备一个栅极电极，包括：
利用第二掩膜，在轻掺杂外延层中，制备一个栅极沟槽，其中第二掩膜限定栅极沟槽；
用绝缘材料内衬栅极沟槽的内表面；并且
用导电材料通过回刻填充栅极沟槽。
其中在一部分轻掺杂外延层中，制备与第一导电类型相反的第二导电类型的本体区，包括：
在轻掺杂外延层上方，制备一层第一绝缘材料；
在这层第一绝缘材料上方，制备一层第二绝缘材料，其中这层第一绝缘材料可以抵抗刻蚀第二绝缘材料层的扩散工艺；
在轻掺杂外延层上，制备第三掩膜，其中第三掩膜具有一个开口，以限定第一个凹凸部分；并且
在轻掺杂外延层中，注入第二导电类型的掺杂物，以形成本体区，其中第二导电类型的掺杂物注入到开口下方轻掺杂外延层内较深的地方，以形成第一个凹凸部分。
上述第一绝缘材料为氮化物。
上述第二绝缘材料为氧化物。
其中这层第一绝缘材料的厚度约为200Å至500Å。
其中这层第二绝缘材料的厚度约为500Å至1000Å。
其中第一个凹凸部分的角度遵循开口的斜度。
其中在本体区顶部中，制备第一导电类型的源极区，包括：
利用第三掩膜，制备本体区，其中第三掩膜具有一个开口，以限定第一个凹凸部分；并且
在本体区中，注入第一导电类型的掺杂物，以形成源极区，其中第一导电类型的掺杂物注入到开口下方本体区中较深的地方，以形成第二个凹凸部分。
上述方法还包含：
利用一个接触沟槽掩膜，制备一个接触沟槽；
用第一导电材料，内衬接触沟槽的内表面；
用第二导电材料填充接触沟槽，其中第二导电材料不同于第一导电材料；并且
回刻第二导电材料。
本发明折叠通道沟槽MOSFET与现有技术相比，其优点在于，本发明通过折叠沟槽MOSFET的通道区，来获得低通道电阻，减小源极-源极电阻。
附图说明
阅读以下详细说明并参照以下附图之后，本发明的其他特征和优势将显而易见：
图1A表示一种具有两个背对背MOSFET的传统开关电路的示意图；
图1B表示一种传统的电池保护电路模块（PCM）的示意图；
图2A表示在并排结构中具有两个背对背MOSFET的传统的开关器件的平面示意图；
图2B表示沿图2A的A-A’线，图2A所示传统的开关电路的剖面示意图；
图3表示传统的平面MOSFET器件的示意图；
图4表示传统的FinFET器件的示意图；
图5表示折叠通道平面MOSFET器件的示意图；
图6表示传统的沟槽MOSFET器件的示意图；
图7表示依据本发明的各个方面，沟槽MOSFET器件的示意图；
图8AA’-29AA’表示在图7所示的A-A’剖面中制备沟槽MOSFET工艺的剖面图；
图8BB’-29BB’表示在图7所示的B-B’剖面中制备沟槽MOSFET工艺的剖面图。
具体实施方式
以下结合附图，进一步说明本发明的具体实施例。
引言
图2A表示具有两个完全绝缘的垂直MOSFET 220和230的器件200的传统布局，两个MOSFET 220和230都具有各自的端接和通道终点。MOSFET 1和MOSFET 2之间要求有大量的死空间，以提供各自的端接区和通道终点。
图2A所示器件的剖面图表示在图2B中。每个垂直MOSFET 220/230都包括多个有源器件晶胞，形成在较重掺杂的衬底244上生长的轻掺杂外延层246中。在本例中，重掺杂（例如N+）衬底244作为漏极，两个MOSFET 220和230的漏极通过形成在衬底244背面的背部金属242电连接在一起。有源器件形成在较轻掺杂的外延漂流层246中，外延漂流层246具有相同的导电类型（例如N-型），生长在衬底244的正面。本体区250的导电类型与衬底244和外延区246相反（例如P-型），形成在一部分外延层246中。沟槽252形成在外延层246中，然后内衬绝缘物254（例如氧化物）。电绝缘栅极电极256，例如由多晶体硅（多晶硅）制成，置于沟槽252中。与衬底244导电类型相同的重掺杂（例如N+）源极区260形成在沟槽252附近。通过源极金属层265和垂直源极接头267，形成到源极区的外部电接头。利用与栅极电极类似的绝缘电极，制备通道终点280、282，栅极电极通过外延区中的源极型导电区，短接至外延漂流区。端接还包括由本体型导电区形成的保护环284、286。
该器件的一个关键特征在于，两个MOSFET 220和230接通下的源极至源极电阻。必须使该电阻尽可能地小。总的源极-源极电阻Rss由下式给出：
其中Rch为当栅极接通时，通过源极260和本体区250的导电通道的电阻，Rdrift是外延层246的电阻，Rbackmetal是背部金属242的电阻以及Rsubstrate是衬底244的电阻。由于通道电阻（Rch）为总的源极-源极电阻Rss的最大组成部分之一，因此必须使导电通道电阻（Rch）尽可能地小。
图3表示一种传统的平面MOSFET中，其通道长度（L）和通道宽度（W）的示意图。半导体器件领域中技术人员众所周知，通道电阻（Rch）与通道长度（L）成正比，与通道宽度（W）成反比。对于指定的晶片尺寸来说，通道电阻（Rch）也与通道密度成反比。为了减小通道电阻（Rch），传统的方法是减小MOSFET的晶胞尺寸，从而增大通道密度。然而，由于制造水平，使得一个晶胞中的可选件和一个邻近晶胞中的另一个可选件之间的距离存在一个极限。
FINFET
鳍式场效晶体管（“FinFET”）是一种建立在绝缘体上硅衬底的非平面晶体管。Hisamoto等人在《用于深亚第十微米时代的折叠通道MOSFET》1032 IEDM（1998）中，介绍了一种FinFET结构，其中包括一个垂直的超薄硅鱼鳍，两个自对准到源极和漏极的栅极，一个升高的源极和漏极，以降低寄生电阻，以及一个准平面结构。图4表示一种改良型FinFET晶体管400的透视图。晶体管400由硅本体402制成，硅本体402包括一个漏极区404、一个源极区406和一个鳍形通道区408，连接在漏极区404和源极区406之间。漏极404、源极406和鳍-通道区408被电介质层412覆盖。栅极结构410穿过鳍形通道408并缠绕在它上面，使得栅极结构与通道408的三个边交接。FinFET 400的结构提供优于通道传导的改良电控制，有助于降低漏电流水平，克服其他的短通道效应。另外，要注意的是，FinFET的通道通过在通道408上方缠绕栅极，其宽度大约为通道区鳍高度的两倍。此后，人们提出了多种方法，通过折叠如图5所示的器件500等器件，增大平面MOSFET的通道宽度。
折叠通道沟槽MOSFET，以减小Rss
依据本发明的各个方面，要阐明折叠通道MOSFET的优势，必须理解传统的沟槽MOSFET。图6表示一部分传统的沟槽MOSFET器件600。沟槽MOSFET 600包括一个栅极电极602、一个本体区604以及一个在衬底上方的源极区606（图中没有表示出）。要注意的是，虽然图6仅表示出了一个栅极电极602，但是在源极区606a边缘的附近，可能存在另一个栅极电极。沟槽MOSFET 600的通道长度（L）为源极区606的底部和本体区604的底部（即衬底顶部）之间，通道宽度（W）为如图所示剖面的第三维度。为了通过减小沟槽MOSFET 600的通道电阻（Rch）来改善总的源极-源极电阻Rss，必须减小其通道长度（L）或增大其通道宽度（W）。
本发明的各个方面通过“折叠”沟槽MOSFET的通道区，来获得低通道电阻。图7表示依据本发明的各个方面，沟槽MOSFET器件700的示意图。要注意的是，虽然图7仅表示出了一部分有源器件晶胞，但是器件700可以具有多个有源器件晶胞。沟槽MOSFET器件700包括一个第一导电类型的轻掺杂外延层720（例如N-），形成在相同导电类型（例如N+）的重掺杂半导体衬底710上方。与衬底710和外延层720（例如P型）相反，具有第二导电类型的本体区730，形成在一部分轻掺杂外延层720中。用电绝缘栅极电极742（例如多晶硅）填充的栅极沟槽740，在轻掺杂外延层720中延伸。与衬底（例如N+）导电类型相同的重掺杂源极区750，形成在本体区730内的沟槽附近。
如图7所示，外延层720具有一个凹凸部分725（或凹陷部分），沿器件700的通道宽度方向，使得外延层720的深度变化在外延层720和衬底710之间的交界面处沿通道宽度方向。另外，本体区730具有一个凹凸部分735，沿凹凸部分725上方的通道宽度方向，使得本体区730的深度变化在本体区730和外延层720之间的交界面处沿通道宽度方向。源极区750具有一个凹凸部分755，沿凹凸部分725和735上方的通道宽度方向，使得源极区750的深度变化在源极区750和本体区730之间的交界面处沿通道宽度方向。如图所示，凹凸部分725、735和755都具有一个凹陷的底面和锥形边缘。引入凹凸部分725、735和755之后，器件700的通道就“折叠”起来了，如图7所示，从而减小了通道宽度，降低了通道电阻。在一个示例中，当凹凸部分725、735和755的锥形边缘角度790约为45度时，通道电阻可以降低16.3%。要注意的是，角度790越尖，通道电阻（Rch）的减小越显著。作为示例，但不作为局限，凹凸部分725、735和755的锥形边缘的角度约在25度和90度之间。
图8AA’-29AA’和图8BB’-29BB’表示图7所示的A-A’和B-B’剖面中，沟槽MOSFET的制备工艺。在图8AA’和8BB’中，该工艺使用第一导电类型的半导体衬底810作为初始材料。在一些示例中，衬底810可以是重掺杂的N型（N+）硅晶圆。然后，在N+衬底810上沉积一个薄的外延层（EPI）812。在一些示例中，EPI 812为硅的轻掺杂N-型层。在图9AA’和9BB’中，在EPI层812上使用一个掩埋层掩膜819，然后注入轻掺杂的N型杂质（N+），形成掩埋层814。如图9AA’所示，一部分EPI 812被掩埋层掩膜819覆盖，以限定凹凸部分的位置。在图10AA’和10BB中，例如通过退火，驱动杂质。要注意的是，如图10AA’所示，在退火工艺除去掩埋层掩膜819之后，被掩埋层掩膜819覆盖的那部分EPI 812留下，裸露出来。在下一步中，与衬底810具有相同导电类型的厚EPI层820，制备在衬底810上方，如图11AA’和11BB’上方。在一些实施例中，厚EPI层820为轻掺杂N型层。在一些配置中，厚EPI层820的厚度约为1μm至3μm之间。如图11AA’所示，在上述步骤中掩埋层注入物的掩埋，导致之前被掩埋层掩膜819覆盖的那部分EPI层820更厚且更深，之前未被掩埋层掩膜819覆盖的那部分区域更薄且更浅。EPI层820的较厚且较深区形成第一个凹凸部分。
在图12AA’和12BB’中，绝缘层822制备在EPI层820上方。在一些实施例中，绝缘层822为氧化层。在绝缘层822上方使用光致抗蚀剂（图中没有表示出），并形成图案，以限定栅极沟槽。带图案的光致抗蚀剂包括在栅极沟槽位置处的开口。如图13AA’和13BB’所示，通过刻蚀工艺，刻蚀掉通过光致抗蚀剂中的开口暴露于刻蚀剂的那部分绝缘层822。除去光致抗蚀剂之后，剩余的那部分绝缘层822用作掩膜，向下刻蚀下方的EPI层820的相应部分，形成栅极沟槽840，如图14AA’和14BB’所示。然后，除去剩余的那部分绝缘层822。
然后，可以生长并除去一个牺牲氧化层（图中没有表示出）以改善硅表面。然后在EPI层820上方，沿栅极沟槽840的内表面，形成一个绝缘层（例如栅极氧化物）824，如图15AA’和15BB’所示。在图16AA’和16BB’中，导电材料842沉积在栅极氧化层824上方。在一些实施例中，导电材料可以是原位掺杂或未掺杂的多晶硅。然后，回刻导电材料842，形成栅极电极842a，如图17AA’和17BB’所示。在图18AA’和18BB’中，进行退火工艺。如图18BB’所示，通过在退火配方中加入一些氧气，可以在栅极电极842a上方形成一个氧化物842a的薄层。
在图19AA’和19BB’中，在栅极氧化层824上方，沉积一个第一绝缘材料826的薄层。在一些实施例中，第一绝缘材料826的薄层厚度范围在200 Å至500 Å之间。在图20AA’和20BB’中，一层第二绝缘材料828沉积在第一绝缘材料826的薄层上方。在一些实施例中，第二绝缘材料828的层厚约为500 Å至1000 Å。薄层826和层828是两种不同的绝缘材料，每种材料都可以抵抗刻蚀另一种材料的刻蚀工艺。也就是说，第一绝缘材料826的薄层可以抵抗刻蚀第二绝缘材料828层的刻蚀工艺，反之亦然。 ，第一绝缘材料826的薄层可以形成一个刻蚀终点，用于后续在第二绝缘材料828层上的刻蚀。在一些实施例中，薄层826为氮化层，第二绝缘材料828层为氧化层。处理绝缘材料828，使得开口的边缘在刻蚀后为斜坡或锥形。例如，表面可以掺杂或注入，以增大刻蚀深度，改善跟切，用于湿刻蚀。如果使用等离子刻蚀的话，可以在刻蚀过程中加入氧气，以腐蚀光致抗蚀剂，形成倾斜的边缘。因此，可以定制所需角度的开口斜度。
然后，进行本体注入和本体扩散。在图21AA’和21BB’中，使用本体掩膜829用于本体注入。要注意的是，本体掩膜829具有一个开口，表示在A-A’平面中，而不是在B-B’平面中。如图22AA’-22BB’所示，掺杂物通过氧化层828和薄氮化层826注入到EPI层820中。掺杂离子的导电类型与衬底810的掺杂相反。在一些实施例中，对于N通道器件来说，掺杂离子可以是硼离子。在一些实施例中，对于P-通道器件来说，可以使用磷或砷离子。由于掩膜开口下方的氧化层828和钝化层826并不厚，因此，掺杂物可以注入到开口下方EPI层820中较深的地方，形成第二个凹凸部分。凹凸部分的角度遵循氧化物开口的斜度。如图23AA’和23BB’所示，用热激活掺杂原子，并驱动掺杂物扩散，形成本体区830。
制备本体区830之后，进行源极注入和源极扩散。首先，如图24AA’和24BB’所示，通过相同的开口，进行源极注入。掺杂离子的导电类型与衬底810的掺杂相同。在一些实施例中，对于N-通道器件来说，可以注入砷离子。对于P-通道器件来说，还可选择注入硼离子。由于，掩膜开口下方的氧化层828和氮化层826并不厚，因此，掺杂物可以注入到开口下方本体区830中较深的地方，形成第三个凹凸部分。在图25AA’和25BB’中，利用标准的扩散工艺，在本体区830中形成源极区850。然后，如图26AA’和26BB’所示，依据标准工艺，除去氧化层828和氮化层826。
如图27AA’-27BB’所示，在栅极氧化层824上方，沉积一个电介质层860，例如氧化物。在一些实施例中，电介质层860可以通过低温氧化物随后一层含有硼酸的硅玻璃（BPSG）构成。
在电介质层860上，使用接触光致抗蚀剂869，其图案是在接触沟槽的位置处有一个开口。在图28AA’-28BB’中，通过刻蚀工艺，除去电介质层860未被覆盖的部分，并在本体区830中形成接触沟槽870。在图29AA’-29BB’中，首先用势垒金属872内衬接触沟槽870的内表面。在一些实施例中，势垒金属872可以是钛（Ti）和氮化钛（TiN）。在接触沟槽870中，可以全面沉积钨（W）等导电材料，然后向上回刻到电介质层860的表面，形成导电插头874。最终，如图29AA’-29BB’所示，在上面沉积一个金属层880。在一些实施例中，金属层880可以是铝（Al）或铝铜（AlCu）。
尽管本发明关于某些较佳的版本已经做了详细的叙述，但是仍可能存在其他版本。因此，本发明的范围不应由上述说明决定，与之相反，本发明的范围应参照所附的权利要求书及其全部等效内容。任何可选件（无论首选与否），都可与其他任何可选件（无论首选与否）组合。在以下权利要求中，除非特别声明，否则不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。除非用“意思是”明确指出限定功能，否则所附的权利要求书并不应认为是意义和功能的局限。权利要求书中没有进行特定功能的精确指明“意义是”的任何项目，都不应理解为美国§ 112, ¶ 6中35所述的“意义”或“步骤”。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (21)

1.一种沟槽MOSFET器件，其特征在于，其包含：
一个第一导电类型的轻掺杂外延层，在第一导电类型的重掺杂半导体衬底上；
一个用导电材料填充的栅极沟槽，在轻掺杂外延层中延伸；
一个与第一导电类型相反的第二导电类型的本体区，在一部分轻掺杂外延层中，其中本体区具有第一个凹凸部分，沿通道宽度方向；以及
一个第一导电类型的源极区，在本体区顶部，其中源极区具有第二个凹凸部分，在第一个凹凸部分上方沿通道宽度方向，其中MOSFET器件的通道宽度随着引入第一和第二个凹凸部分而增大。
2.如权利要求1所述的器件，其特征在于，所述第一导电类型为N型，第二导电类型为P型。
3.如权利要求1所述的器件，其特征在于，所述轻掺杂外延层、本体区和源极区的深度沿通道宽度变化。
4.如权利要求1所述的器件，其特征在于，所述轻掺杂外延层具有第三个凹凸部分，沿MOSFET器件的通道宽度方向。
5.如权利要求4所述的器件，其特征在于，所述第三个凹凸部分的深度延伸到半导体衬底中，比轻掺杂外延层的其他部分更深的地方。
6.如权利要求1所述的器件，其特征在于，所述第一个凹凸部分的深度延伸到轻掺杂外延层中，比本体区的其他部分更深的地方。
7.如权利要求1所述的器件，其特征在于，所述第二个凹凸部分的深度延伸到本体区中，比源极区的其他部分更深的地方。
8.如权利要求1所述的器件，其特征在于，所述第一个和第二个凹凸部分的锥形边缘，其角度约在25度和90度之间。
9.一种用于制备沟槽MOSFET器件的方法，其特征在于，其包含：
在第一导电类型的重掺杂半导体衬底上，制备一个第一导电类型的轻掺杂外延层；
在轻掺杂外延层中制备一个栅极电极；
在轻掺杂外延层的一部分中，制备与第一导电类型相反的第二导电类型的本体区，其中本体区的第一个凹凸部分沿通道宽度方向；并且
在本体区顶部中，制备第一导电类型的源极区，其中源极区具有第二个凹凸部分，沿第一个凹凸部分上方的通道宽度方向。
10.如权利要求9所述的方法，其特征在于，所述第一导电类型为N型，第二导电类型为P型。
11.如权利要求9所述的方法，其特征在于，所述轻掺杂外延层具有第三个凹凸部分，沿MOSFET器件的通道宽度方向。
12.如权利要求9所述的方法，其特征在于，其中在第一导电类型的重掺杂半导体衬底上，制备一个第一导电类型的轻掺杂外延层，包含：
在半导体衬底上，制备一个第一外延层；
利用第一掩膜，制备一个掩埋层，其中第一掩膜限定第三个凹凸部分；并且
在掩埋层上，制备一个第二外延层。
13.如权利要求9所述的方法，其特征在于，其中在轻掺杂外延层中，制备一个栅极电极，包括：
利用第二掩膜，在轻掺杂外延层中，制备一个栅极沟槽，其中第二掩膜限定栅极沟槽；
用绝缘材料内衬栅极沟槽的内表面；并且
用导电材料通过回刻填充栅极沟槽。
14.如权利要求9所述的方法，其特征在于，其中在一部分轻掺杂外延层中，制备与第一导电类型相反的第二导电类型的本体区，包括：
在轻掺杂外延层上方，制备一层第一绝缘材料；
在这层第一绝缘材料上方，制备一层第二绝缘材料，其中这层第一绝缘材料可以抵抗刻蚀第二绝缘材料层的扩散工艺；
在轻掺杂外延层上，制备第三掩膜，其中第三掩膜具有一个开口，以限定第一个凹凸部分；并且
在轻掺杂外延层中，注入第二导电类型的掺杂物，以形成本体区，其中第二导电类型的掺杂物注入到开口下方轻掺杂外延层内较深的地方，以形成第一个凹凸部分。
15.如权利要求14所述的方法，其特征在于，所述第一绝缘材料为氮化物。
16.如权利要求14所述的方法，其特征在于，所述第二绝缘材料为氧化物。
17.如权利要求14所述的方法，其特征在于，其中这层第一绝缘材料的厚度约为200Å至500Å。
18.如权利要求14所述的方法，其特征在于，其中这层第二绝缘材料的厚度约为500Å至1000Å。
19.如权利要求14所述的方法，其特征在于，其中第一个凹凸部分的角度遵循开口的斜度。
20.如权利要求9所述的方法，其特征在于，其中在本体区顶部中，制备第一导电类型的源极区，包括：
利用第三掩膜，制备本体区，其中第三掩膜具有一个开口，以限定第一个凹凸部分；并且
在本体区中，注入第一导电类型的掺杂物，以形成源极区，其中第一导电类型的掺杂物注入到开口下方本体区中较深的地方，以形成第二个凹凸部分。
21.如权利要求9所述的方法，其特征在于，还包含：
利用一个接触沟槽掩膜，制备一个接触沟槽；
用第一导电材料，内衬接触沟槽的内表面；
用第二导电材料填充接触沟槽，其中第二导电材料不同于第一导电材料；并且
回刻第二导电材料。
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