CN108022909B - 在电子芯片与载体衬底之间形成电连接的方法和电子器件 - Google Patents

在电子芯片与载体衬底之间形成电连接的方法和电子器件 Download PDF

Info

Publication number
CN108022909B
CN108022909B CN201710374080.0A CN201710374080A CN108022909B CN 108022909 B CN108022909 B CN 108022909B CN 201710374080 A CN201710374080 A CN 201710374080A CN 108022909 B CN108022909 B CN 108022909B
Authority
CN
China
Prior art keywords
electrical connection
carrier substrate
electronic chip
dielectric layer
connection pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710374080.0A
Other languages
English (en)
Other versions
CN108022909A (zh
Inventor
D·奥彻雷
A·哈吉
F·奎尔恰
J·洛佩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grenoble 2 SAS
Original Assignee
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Grenoble 2 SAS filed Critical STMicroelectronics Grenoble 2 SAS
Publication of CN108022909A publication Critical patent/CN108022909A/zh
Application granted granted Critical
Publication of CN108022909B publication Critical patent/CN108022909B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the wire connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/858—Bonding techniques
    • H01L2224/85801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本公开涉及在电子芯片与载体衬底之间形成电连接的方法和电子器件。电连接线连接电子芯片的电连接焊盘与载体衬底的电连接焊盘，该电子芯片安装至该载体衬底。介电层围绕键合接线并且至少覆盖该电子芯片和该载体衬底的一部分。液体导电材料沉积在该介电层上并且然后硬化以形成围绕在该键合接线处的该介电层的局部导电屏蔽。

Description

在电子芯片与载体衬底之间形成电连接的方法和电子器件
优先权要求
本申请要求于2016年11月3日提交的第1660622号法国专利申请的优先权权益，该申请的公开内容通过引用以其全文结合在此。
技术领域
实施例涉及电子器件领域并且更具体地涉及包括安装在载体衬底上的电子芯片以及将芯片连接至载体衬底的电连接线的那些电子器件，该载体衬底包括电连接网络或引线框。
背景技术
在电连接线尤其是以高频率传送信号的情况下，这些信号可以通过围绕电磁场而被衰减或被破坏和/或发射可能破坏周围环境的电磁场。
目前，为了应对这种问题，提出了向电子器件添加潜在地连接至地的金属屏蔽板。尽管如此，定位这类金属屏蔽板并将其电连接至地，加上制造包封块或将包封盖放置就位造成了问题并且成本很高。此外，由于所获得的屏蔽是非特定的并且位于距电连接线一定距离，因此，所获得的电磁保护水平仍然是不够的。
发明内容
根据一个实施例，提出了一种用于在电子芯片与载体衬底之间形成电连接的方法，此芯片安装在该载体衬底上。
该方法包括以下步骤：将至少一条电连接线置于该芯片的暴露的电连接焊盘与该载体衬底的暴露的电连接焊盘之间并且在该线的两端与这些焊盘之间形成电结；制造介电层，该介电层由在该电子芯片的以及该载体衬底的区域的顶部上的介电材料制成，包括该电连接线、这些电结和这些焊盘，使得此介电层形成局部介电涂层，该局部介电涂层至少部分地围绕该电连接线并且至少部分地覆盖这些电结和这些焊盘；以及制造局部导电屏蔽，该局部导电屏蔽由导电材料制成、至少部分地覆盖该局部介电涂层。
可以通过分配确定量的液体状态下的该介电材料以及使此介电材料硬化来获得包括该局部介电涂层的该介电层。
可以借助于溅射来分配该介电材料。
可以通过分配确定量的液体状态下的导电材料以及使此导电材料硬化来获得该局部导电屏蔽。
可以借助于包括分注注射器的控制工具来分配该导电材料。
可以制造该局部介电涂层以完全围绕该电连接线并完全覆盖这些焊盘和这些结，并且可以制造该局部导电屏蔽以完全覆盖该局部介电涂层。
该方法可以附加地包括以下步骤：在该电子芯片的以及该载体衬底的附加电连接焊盘之上的该介电层中制造开口；将附加电连接线置于这些附加焊盘之间并且在该附加线的两端与这些附加焊盘之间形成电结；以及制造该局部导电屏蔽使得此局部导电屏蔽与该附加电连接线和/或与这些附加焊盘中的至少一个附加焊盘相接触。
还提出了一种电子器件，该电子器件包括：载体衬底；电子芯片，该电子芯片安装在该载体衬底上；至少一条电连接线，该至少一条电连接线连接该载体衬底的电连接焊盘和该电子芯片的电连接焊盘；介电层，该介电层由在该电子芯片的以及该载体衬底的区域的顶部上的介电材料制成，包括该电连接线、这些结和这些焊盘，使得此介电材料形成局部介电涂层，该局部介电涂层至少部分地围绕该电连接线并且至少部分地覆盖这些结和这些焊盘；以及局部导电屏蔽，该局部导电屏蔽由导电材料制成、至少部分地覆盖该局部介电涂层。
该局部介电涂层可以完全围绕该电连接线并且完全覆盖这些焊盘和这些结，并且该局部导电屏蔽可以完全覆盖该局部介电涂层。
该器件可以包括至少一条附加电连接线，该至少一条附加电连接线连接该载体衬底的电连接焊盘和该电子芯片的电连接焊盘，该局部导电屏蔽与该附加电连接线和/或与这些电连接焊盘中的至少一个电连接焊盘相接触。
附图说明
现在将以附图所展示的非限制性示例的方式描述电子器件和制造模式，在附图中：
图1表示制造过程中的电子器件在一个制造步骤中的横截面视图；
图2表示图1的电子器件的俯视图；
图3表示制造过程中的电子器件在随后的制造步骤中的横截面视图；
图4表示图3的电子器件的俯视图；
图5表示制造过程中的电子器件在随后的制造步骤中的俯视图；
图6表示制造过程中的电子器件在随后的制造步骤中的横截面视图，示出了所获得的电子器件；以及
图7表示图6的电子器件的俯视图。
具体实施方式
如在图1和图2中所展示的，电子器件1包括载体衬底2以及包括有集成电路的电子芯片3，该电子芯片的背面4借助于粘合层(未示出)固定至载体衬底2的正面5。
载体衬底2由介电材料制成并且包括用于连接至一个或多个金属层的集成电连接网络6，该集成电连接网络包括正面5的正面暴露的电连接焊盘7和8，这些正面暴露的电连接焊盘横向地位于与电子芯片3的侧面9相距一定距离处并且彼此靠近。
电子芯片3包括与其背面4相反的此电子芯片3的正面12的正面暴露的电连接焊盘10和11，这些正面暴露的电连接焊盘位于与电子芯片3的侧面9相距一定距离处，离载体衬底2的正面焊盘7和8不远。
现在将描述出于在载体衬底2的以及电子芯片3的焊盘7与10之间以及可选地在焊盘8与11之间分别形成电连接的目的的步骤。
在图1和图2所展示的步骤中，电连接线(也称为键合接线)213被放置就位在暴露的电连接焊盘7与10之间，并且电结214和215借助于焊接分别形成在电连接线213的两端与焊盘7和10之间。
可以使用专门的接线键合机来实施将电连接线213放置就位的这个操作。
在图3和图4所展示的随后的步骤中，将确定量的粘合液体介电材料分配在载体衬底2和电子芯片3的正面5和12的以及电连接线213的区域的顶部上，使得此介电材料至少部分地覆盖面5和12、焊盘7、8、10和12以及结214和215并且完全围绕电连接线213。
在硬化之后，此介电材料在载体衬底2的以及电子芯片3的正面5和12的顶部上形成介电层217a并且形成局部介电涂层217b，该局部介电涂层覆盖焊盘7、8、10和12以及结214和215并且围绕电连接线213，介电层217a和局部介电涂层217b互相延伸。
此操作可以例如使用专门的工具来实施，该专门的工具包括能够递送液体导电材料的至少一滴对应校准的液体导电材料的控制分注注射器218，此液体导电材料具体地借助于润湿效应或者毛细效应流动。作为变体，此操作可以通过将整个电子器件1浸入到介电材料浴中来实施。可以借助于溅射来替代性地分配介电材料。
接下来，液体介电材料凭借其在室温下固有的硬化品质或者通过在热源或光辐射源效应下硬化而硬化以形成介电涂层217a和217b。例如，介电材料可以是适合的环氧树脂或通常被称为聚对二甲苯的聚对二甲苯聚合物。在实施例中，介电涂层217a和217b在电连接线213、焊盘7和10、芯片3以及衬底2的表面之上具有基本上均匀的涂层厚度。
在图5所展示的随后步骤中，例如借助于蚀刻使开口216a和216b穿过在焊盘8和11之上的介电层217a。接下来，附加电连接线(也称为键合接线)216被放置就位在附加的暴露的电连接焊盘8与11之间，并且电结借助于焊接分别形成在电连接线216的两端与焊盘8和11之间。
可以使用专门的接线键合机来实施将电连接线216放置就位的这个操作。
在图6和图7所展示的随后步骤中，局部地分配确定量的导电粘合液体材料，使得此导电材料完全围绕绝缘涂层217b、覆盖局部介电涂层217a并且与电连接线216和/或焊盘8和11相接触，此导电材料潜在地溢流到载体衬底2的以及电子芯片3的正面5和12上。在硬化之后，此导电材料形成局部导电屏蔽219，该局部导电屏蔽尽可能地靠近电连接线213并且连接至电连接线216以及至焊盘8和11。
此操作可以例如使用专门的控制工具来实施，该专门的控制工具包括能够递送该液体导电材料的至少一滴校准的液体导电材料的控制分注注射器220，此液体导电材料具体地借助于润湿效应或者毛细效应流动。
接下来，液体导电材料凭借其在室温下固有的硬化品质或者通过在热源或光辐射源效应下硬化而硬化以形成局部导电屏蔽219。例如，导电材料可以是填充有金属颗粒的环氧树脂。
然后，获得成品电子器件1。
电连接线213旨在传送载体衬底2的以及电子芯片3的焊盘7与10之间的电信号。导电屏蔽219形成对这些电信号的电磁保护。
由电连接线216连接的焊盘8和11形成电子器件1的电气电路的接地焊盘。因此，连接至焊盘8和11以及至电连接线216的导电屏蔽219连接至电子器件1的电气电路的地。
根据一个变体实施例，局部导电屏蔽219可以部分地覆盖局部介电涂层217b。
根据一个变体实施例，将有可能去掉电连接线216。
当然，电子器件1可以包括连接至载体衬底2的以及电子芯片3的其他焊盘7和10的其他电连接线213，以及连接载体衬底2的以及电子芯片3的其他焊盘8和11的其他电连接线216，该载体衬底和该电子芯片还配备有局部介电涂层217b以及局部导电屏蔽219，这些电连接线的对应制造步骤将会是相同的。
根据一个变体实施例，一个局部导电屏蔽219将有可能由多个邻近电连接线213共享并且局部地覆盖载体衬底的正面5和/或电子芯片3的正面12，使得此延伸的局部导电屏蔽219将会形成对电子器件1的电子电路中的一部分的电磁保护。在此情况下，将有可能提供单条接地电连接线216。
根据一个变体实施例，载体衬底2可以包括金属框，该金属框包括电子芯片3将会安装在其上的平台，电连接线213和216将电子芯片3连接至此框的外围引线。

Claims (18)

1.一种用于在电子芯片与载体衬底之间形成电连接的方法，包括以下步骤：
将第一电连接线置于所述电子芯片的第一暴露的电连接焊盘与所述载体衬底的第一暴露的电连接焊盘之间，所述电子芯片安装在所述载体衬底上，并且在所述第一电连接线的两端与所述电子芯片的第一暴露的电连接焊盘和所述载体衬底的第一暴露的电连接焊盘之间形成第一电结；
制造介电层，所述介电层由在所述电子芯片的以及所述载体衬底的区域的顶部上的介电材料制成，所述介电层覆盖所述第一电连接线、所述第一电结、所述电子芯片的第一暴露的电连接焊盘和所述载体衬底的第一暴露的电连接焊盘，使得所述介电层形成局部介电涂层，所述局部介电涂层完全围绕所述第一电连接线并且完全覆盖所述第一电结、所述电子芯片的第一暴露的电连接焊盘和所述载体衬底的第一暴露的电连接焊盘；
在所述电子芯片的第二电连接焊盘以及所述载体衬底的第二电连接焊盘上方的所述介电层中制造开口；
将第二电连接线置于所述电子芯片的所述第二电连接焊盘与所述载体衬底的第二电连接焊盘之间；以及
制造局部导电屏蔽，所述局部导电屏蔽由导电材料制成、至少部分地覆盖所述局部介电涂层、并且直接地接触所述第二电连接线、所述电子芯片的第二电连接焊盘和所述载体衬底的第二电连接焊盘。
2.根据权利要求1所述的方法，其中，制造所述介电层包括分配确定量的液体状态下的所述介电材料以及使所述介电材料硬化。
3.根据权利要求2所述的方法，其中，借助于溅射来分配所述介电材料。
4.根据权利要求1所述的方法，其中，制造所述局部导电屏蔽包括分配确定量的液体状态下的导电材料以及使所述导电材料硬化。
5.根据权利要求4所述的方法，其中，使用控制工具来分配所述导电材料。
6.根据权利要求5所述的方法，其中，所述控制工具为分注注射器。
7.根据权利要求1所述的方法，其中，制造所述局部导电屏蔽包括完全覆盖所述局部介电涂层、并且直接地接触所述第二电连接线、所述电子芯片的第二电连接焊盘和所述载体衬底的第二电连接焊盘。
8.根据权利要求1所述的方法，进一步包括以下步骤：
在所述第二电连接线的两端与所述电子芯片的第二电连接焊盘和所述载体衬底的第二电连接焊盘之间形成第二电结。
9.根据权利要求1所述的方法，其中，制造介电层包括以均匀的厚度沉积所述介电层。
10.一种电子器件，包括：
载体衬底；
电子芯片，所述电子芯片安装在所述载体衬底上，并且所述电子芯片包括第一电连接焊盘和第二电连接焊盘；
第一电连接线，所述第一电连接线连接所述载体衬底的第一电连接焊盘和所述电子芯片的第一电连接焊盘；
第二电连接线，所述第二电连接线连接所述载体衬底的第二电连接焊盘和所述电子芯片的第二连接焊盘；
介电层，所述介电层由在所述电子芯片的以及所述载体衬底的区域的顶部上的介电材料制成，所述介电层覆盖所述第一电连接线、所述电子芯片的第一电连接焊盘和所述载体衬底的第一电连接焊盘，但是所述介电层不覆盖所述第二电连接线、所述电子芯片的第二电连接焊盘和所述载体衬底的第二电连接焊盘，使得所述介电层形成局部介电涂层，所述局部介电涂层完全围绕所述第一电连接线并且完全覆盖所述电子芯片的第一电连接焊盘和所述载体衬底的第一电连接焊盘；以及
局部导电屏蔽，所述局部导电屏蔽由导电材料制成、至少部分地覆盖所述局部介电涂层、并且直接地接触所述第二电连接线、所述电子芯片的第二电连接焊盘和所述载体衬底的第二电连接焊盘。
11.根据权利要求10所述的电子器件，其中，所述局部导电屏蔽完全覆盖所述局部介电涂层、所述第二电连接线、所述电子芯片的第二电连接焊盘和所述载体衬底的第二电连接焊盘。
12.根据权利要求10所述的电子器件，其中，所述介电层具有均匀的厚度。
13.根据权利要求10所述的电子器件，其中，所述介电层沿所述电连接线的长度具有不均匀的厚度。
14.一种用于在电子芯片与载体衬底之间形成电连接的方法，包括以下步骤：
将电子芯片安装至载体衬底；
将第一键合接线连接在所述电子芯片的第一电连接焊盘与所述载体衬底的第一电连接焊盘之间；
使液体介电材料流动以涂覆所述第一键合接线以及所述电子芯片和所述载体衬底各自的第一部分；
使所述液体介电材料硬化以形成介电层，所述介电层围绕所述第一键合接线具有均匀的厚度并且在所述电子芯片和所述载体衬底各自的所述第一部分的表面上；
在所述电子芯片的第二电连接焊盘以及所述载体衬底的第二电连接焊盘上方的所述介电层中制造开口；
将第二键合接线连接于所述电子芯片的所述第二电连接焊盘与所述载体衬底的所述第二电连接焊盘之间；
使液体导电材料流动以涂覆所述介电层、并且与所述第二键合接线物理以及电连接；以及
使所述液体导电材料硬化以形成在所述第一键合接线上围绕所述介电层、并且与所述第二键合接线物理以及电连接的导电屏蔽。
15.如权利要求14所述的方法，进一步包括：
其中，使所述液体导电材料流动进一步包括使所述液体导电材料流动以涂覆所述第二键合接线；并且
其中，使所述液体导电材料硬化进一步包括使所述液体导电材料硬化以形成围绕所述第二键合接线的所述导电屏蔽。
16.一种电子器件，包括：
载体衬底；
电子芯片，所述电子芯片安装在所述载体衬底上；
第一键合接线，所述第一键合接线连接于所述载体衬底的第一电连接焊盘和所述电子芯片的第二电连接焊盘之间；
第二键合接线，所述第二键合接线连接于所述载体衬底的第三电连接焊盘和所述电子芯片的第四电连接焊盘之间；
介电层，所述介电层围绕所述第一键合接线具有均匀的厚度并且在所述电子芯片和所述载体衬底各自的第一部分的表面上，但是所述介电层不围绕所述第二键合接线的任何部分以及所述电子芯片和所述载体衬底的第二部分的任何部分；以及
硬化的液体导电材料，所述硬化的液体导电材料围绕至少在所述第一键合接线处的所述介电层、并且至少与所述第二键合接线物理以及电连接。
17.如权利要求16所述的电子器件，进一步包括：
其中，所述硬化的液体导电材料围绕所述第二键合接线、所述第三电连接焊盘和所述第四电连接焊盘。
18.根据权利要求16所述的电子器件，其中，所述介电层沿所述键合接线的长度具有不均匀的厚度。
CN201710374080.0A 2016-11-03 2017-05-24 在电子芯片与载体衬底之间形成电连接的方法和电子器件 Active CN108022909B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1660622A FR3058259A1 (fr) 2016-11-03 2016-11-03 Procede de realisation d'une connexion electrique entre une puce electronique et une plaque de support et dispositif electronique
FR1660622 2016-11-03

Publications (2)

Publication Number Publication Date
CN108022909A CN108022909A (zh) 2018-05-11
CN108022909B true CN108022909B (zh) 2021-06-04

Family

ID=58213194

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201710374080.0A Active CN108022909B (zh) 2016-11-03 2017-05-24 在电子芯片与载体衬底之间形成电连接的方法和电子器件
CN201720588195.5U Active CN206877990U (zh) 2016-11-03 2017-05-24 电子器件

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201720588195.5U Active CN206877990U (zh) 2016-11-03 2017-05-24 电子器件

Country Status (3)

Country Link
EP (1) EP3319116B1 (zh)
CN (2) CN108022909B (zh)
FR (1) FR3058259A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3058259A1 (fr) * 2016-11-03 2018-05-04 Stmicroelectronics (Grenoble 2) Sas Procede de realisation d'une connexion electrique entre une puce electronique et une plaque de support et dispositif electronique

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2689467B2 (ja) * 1988-03-29 1997-12-10 日本電気株式会社 半導体集積回路装置のパッケージ
JPH05226391A (ja) * 1992-01-13 1993-09-03 Nec Corp Ｉｃチップの封止方法
JPH06268100A (ja) * 1993-03-12 1994-09-22 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の封止構造および封止方法
JP2000058579A (ja) * 1998-08-04 2000-02-25 Hitachi Ltd 半導体装置およびその製造方法
US20040070065A1 (en) * 2002-10-11 2004-04-15 Aritharan Thurairajaratnam Controlled impedance for wire bonding interconnects
KR100575086B1 (ko) * 2004-11-11 2006-05-03 삼성전자주식회사 도전성 몰딩 컴파운드를 구비한 반도체 패키지 및 그제조방법
TW200903769A (en) * 2007-07-13 2009-01-16 Ind Tech Res Inst An integrated circuit package structure with EMI shielding
US20100025864A1 (en) * 2008-07-31 2010-02-04 International Business Machines Corporation Shielded wirebond
KR100950511B1 (ko) * 2009-09-22 2010-03-30 테세라 리써치 엘엘씨 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리
US8377749B1 (en) * 2009-09-15 2013-02-19 Applied Micro Circuits Corporation Integrated circuit transmission line
JP5802695B2 (ja) * 2013-03-19 2015-10-28 株式会社東芝 半導体装置、半導体装置の製造方法
FR3058259A1 (fr) * 2016-11-03 2018-05-04 Stmicroelectronics (Grenoble 2) Sas Procede de realisation d'une connexion electrique entre une puce electronique et une plaque de support et dispositif electronique

Also Published As

Publication number Publication date
EP3319116B1 (fr) 2022-06-29
CN206877990U (zh) 2018-01-12
CN108022909A (zh) 2018-05-11
FR3058259A1 (fr) 2018-05-04
EP3319116A1 (fr) 2018-05-09

Similar Documents

Publication Publication Date Title
US9209081B2 (en) Semiconductor grid array package
US8129824B1 (en) Shielding for a semiconductor package
KR100516816B1 (ko) 반도체장치의 제조 방법
TWI431748B (zh) 具有阻抗控制引線接合及導電參考元件之微電子總成
US20220130686A1 (en) Control of under-fill using an encapsulant and a trench or dam for a dual-sided ball grid array package
US20120199958A1 (en) Method of manufacturing high frequency module and high frequency module
US10529652B2 (en) Integrated circuit (IC) package with a solder receiving area and associated methods
CN102610591A (zh) 半导体模块
CN106486422B (zh) 装备有导电层的电子装置及其制造方法
KR101563910B1 (ko) 반도체 패키지 및 이의 제조 방법
CN110098130B (zh) 一种系统级封装方法及封装器件
TW201340261A (zh) 半導體裝置及其製造方法
US20170117251A1 (en) Fan-out 3D IC Integration Structure without Substrate and Method of Making the Same
CN106876364A (zh) 半导体封装件及其制造方法
KR100788858B1 (ko) 집적 회로 패키지의 구조물 및 어셈블리 방법
US20130320527A1 (en) Semiconductor device and semiconductor device manufacturing method
US8179686B2 (en) Mounted structural body and method of manufacturing the same
CN108022909B (zh) 在电子芯片与载体衬底之间形成电连接的方法和电子器件
US11557566B2 (en) Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device
US10964627B2 (en) Integrated electronic device having a dissipative package, in particular dual side cooling package
CN206877989U (zh) 电子器件
CN212182305U (zh) 电子设备
US20230121780A1 (en) Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device
US10068882B2 (en) High-frequency module
CN207038521U (zh) 电子器件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant