CN107946254A - The silicon substrate fan-out package and wafer-level packaging method of integrated heat dissipation structure - Google Patents
The silicon substrate fan-out package and wafer-level packaging method of integrated heat dissipation structure Download PDFInfo
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- CN107946254A CN107946254A CN201711364900.4A CN201711364900A CN107946254A CN 107946254 A CN107946254 A CN 107946254A CN 201711364900 A CN201711364900 A CN 201711364900A CN 107946254 A CN107946254 A CN 107946254A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/298—Semiconductor material, e.g. amorphous silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses the silicon substrate fan-out package and wafer-level packaging method of a kind of integrated heat dissipation structure, and based on silicon substrate fan-out package technology, the second surface of silicon substrate directly makes radiator structure after chip is embedded to, manufactured by wafer scale processing procedure, high precision machining, process is simple, and price is low.Compared with the heat sink of tradition machinery processing, the present invention can create the heat dissipation area of bigger, realize more preferable heat dissipation effect on silicon substrate directly using the finer radiator structure of bulk silicon process manufactured size in same unit volume.This radiator structure is directly integrated in the chip back of embedment silicon substrate, and integration density is high, small, light-weight.And reduce the interface between external environment and chip, further increase heat dissipation effect.Preferably, the heat-dissipating cover plate with Forced water cooling can be integrated on the radiator structure of silicon substrate second surface, the radiating efficiency of higher is obtained.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, and in particular to a kind of silicon substrate fan-out package of integrated heat dissipation structure
And wafer-level packaging method.
Background technology
Wafer scale is fanned out to encapsulation and refers to, by reconstructing disk and wafer level wire laying mode again, I/O be passed through wiring side battle array again
Row are covered with package surface, in order to expand I/O pitches, meet the pitch requirements of next stage interconnection.
At present, it is traditional using eWLB as in the fan-out package technology of Typical Representative, five face of chip is all by capsulation material
(epoxy molding compound) is wrapped up.However, the general heat conductivity of capsulation material is poor so that the radiating efficiency of chip
Relatively low but the integrated making of extra radiator structure is more complicated, it is necessary to extra integrated heat dissipation structure, and cost of manufacture is high.
The content of the invention
In order to solve the above-mentioned technical problem, the present invention proposes a kind of the silicon substrate fan-out package and wafer of integrated heat dissipation structure
Level packaging methods, based on silicon substrate fan-out package technology (eSiFO), realize more preferable heat dissipation effect, and simple with making,
The advantages of low manufacture cost.
The technical proposal of the invention is realized in this way：
A kind of silicon substrate fan-out package of integrated heat dissipation structure, including a silicon substrate, the silicon substrate have first surface
And second surface, it is described recessed formed with least one groove extended to the second surface on the first surface of the silicon substrate
The chip of an at least pad upwardly is equipped with groove, there is pad on the pad face of the chip, at least one pad
Electrically fanned out to by conductive fan-out structure on the first surface of the silicon substrate, directly made on the second surface of the silicon substrate
Work has radiator structure.
Further, the radiator structure is included in being intervally arranged of directly being made on the second surface of the silicon substrate
Multiple microchannels, the microchannel extend certain distance from the second surface of the silicon substrate to first surface.
Further, the shape of cross section of the microchannel is poroid or channel-like.
Further, the microchannel is including the first microchannel on the bottom of the groove and positioned at described recessed
The second microchannel outside the sidewall extension line of groove.
Further, the depth of second microchannel is more than the depth of first microchannel, and described second micro- logical
Cross the bottom of the groove in the bottom in road.
Further, heat-dissipating cover plate is pasted with the second surface of the silicon substrate, formed with confession in the heat-dissipating cover plate
The import of coolant disengaging, the radiating flow passage for exporting and being connected between inlet and outlet, the heat-dissipating cover plate sealing are described micro-
The opening of passage.
Further, the conductive fan-out structure includes being formed on the first surface of the chip and the silicon substrate
The gold of dielectric layer, the soldered ball being made on the first surface of pad Yu the silicon substrate that the chip is connected on the dielectric layer
Belong to wiring and the passivation layer being layed on the metal wiring layer.
A kind of wafer-level packaging method of the silicon substrate fan-out package of integrated heat dissipation structure, comprises the following steps：
A., one silicon substrate wafer is provided, the silicon substrate disk has first surface and second surface corresponding thereto,
The first surface of the silicon substrate disk etches to form at least one groove with setting shape and depth；
B., at least one chip to be packaged is installed in the groove, makes the pad of the chip face-up；
C. conductive fan-out structure is made on the first surface of the silicon substrate wafer and the pad face of the chip, it is near
A few pad is electrically fanned out on the first surface of the silicon substrate；
D. the radiator structure of corresponding each chip, institute are directly made on the second surface of the silicon substrate wafer after step C
State radiator structure and be included in the multiple microchannels being intervally arranged directly made on the second surface of the silicon substrate, it is described micro- logical
Road extends certain distance from the second surface of the silicon substrate to first surface；
E. cutting crystal wafer, forms the silicon substrate fan-out package of integrated heat dissipation structure.
Further, when the thickness of the silicon substrate wafer is not enough to make radiator structure in the encapsulation of support wafer level,
Silicon substrate wafer after step C is pressure bonded on an interim support plate by interim bonding material, and in the making for completing radiator structure
Afterwards, interim support plate solution is bonded.
Further, the radiator structure is produced by photoetching and etching process in step D, or is cut using machinery
Cut and process the radiator structure with laser technology.
Further, a heat-dissipating cover plate, the heat-dissipating cover plate are mounted on the second surface of the silicon substrate wafer after step D
In there is the import for coolant disengaging, the radiating flow passage that exports and be connected between inlet and outlet, the heat-dissipating cover plate is close
Seal the opening of the microchannel.
The beneficial effects of the invention are as follows：The present invention provides a kind of the silicon substrate fan-out package and wafer scale of integrated heat dissipation structure
Method for packing, based on silicon substrate fan-out package technology (eSiFO), the second surface of silicon substrate, which directly makes, after chip is embedded to dissipates
Heat structure, is manufactured by wafer scale processing procedure, and high precision machining, process is simple, and price is low.With the heat sink phase of tradition machinery processing
Than the present invention can be on silicon substrate directly using the finer radiator structure of bulk silicon process manufactured size, same
Unit volume in create the heat dissipation area of bigger, realize more preferable heat dissipation effect.This radiator structure is directly being embedded to
The chip back of silicon substrate integrates, and integration density is high, small, light-weight.And reduce between external environment and chip
Interface, further increases heat dissipation effect.Preferably, it can be integrated on the radiator structure of silicon substrate second surface with pressure
The heat-dissipating cover plate of water cooling, obtains the radiating efficiency of higher.
Brief description of the drawings
Fig. 1 is the silicon substrate crystal circle structure schematic diagram after step C of the present invention；
When Fig. 2 is that the thickness of the invention in silicon substrate wafer is not enough to make radiator structure in the encapsulation of support wafer level, silicon
The structure diagram that base wafer is bonded with interim support plate；
Fig. 3 is the structure diagram that the present invention directly makes radiator structure in the second surface of silicon substrate wafer；
Fig. 4 is the structure diagram of the silicon substrate wafer after the interim support plate solution bonding of the present invention；
Fig. 5 is the structure diagram of the silicon substrate fan-out package of integrated heat dissipation structure of the present invention；
Fig. 6 is the silicon substrate fan-out-type for the integrated heat dissipation structure that the second microchannel depth of the invention is more than the first microchannel depth
The structure diagram of encapsulation；
Fig. 7 is the structure diagram of the silicon substrate fan-out package of integrated heat dissipation structure of the present invention with cover board.
Embodiment
In order to be more clearly understood that the technology contents of the present invention, described in detail especially exemplified by following embodiments, its purpose is only
It is to be best understood from the protection domain that present disclosure is not intended to limit the present invention.Each part in the structure of embodiment attached drawing
Do not scaled by normal rates, therefore do not represent the actual relative size of each structure in embodiment.
As shown in figure 5, a kind of silicon substrate fan-out package of integrated heat dissipation structure, including a silicon substrate 1, the silicon substrate tool
There are first surface 101 and second surface 102, prolong on the first surface of the silicon substrate formed with least one to the second surface
The groove 103 stretched, the groove is interior to be equipped with the chip 2 of an at least pad upwardly, has weldering on the pad face of the chip
Disk, the electrical of at least one pad are fanned out on the first surface of the silicon substrate by conductive fan-out structure 3, the silicon substrate
Directly being made on the second surface of body has radiator structure.
In said structure, the second surface of silicon substrate directly makes radiator structure after chip is embedded to, and reduces extraneous ring
Interface between border and chip, improves heat dissipation effect.And this radiator structure is directly in the chip back collection of embedment silicon substrate
Into manufacturing process is simple, has the advantages that integration density is high, small, light-weight low with cost etc..
Preferably, it is more to be included in being intervally arranged of directly being made on the second surface of the silicon substrate for the radiator structure
A microchannel 4, the microchannel extend certain distance from the second surface of the silicon substrate to first surface.In this way, same
Unit volume in createed the heat dissipation area of bigger, can realize more preferable heat dissipation effect.Plurality of microchannel can be with
In array-like regular array or irregular arrangement, in order to obtain uniform and stable heat dissipation effect, it is preferred that using being in
The form of array-like regular parallel arrangement.
Preferably, the shape of cross section of the microchannel is poroid or channel-like.That is, multiple microchannels can be
Multiple apertures independent of each other, in netted, the shape of aperture can be with straight hole or inclined hole etc. or multiple ditches independent of each other
Road, in lattice-shaped, the shape of raceway groove can be straight flute road or valley road etc., and Fig. 5 illustrates straight hole or straight communication way, but not
It is limited to this, for example microchannel can also make combination that is poroid and linking up shape.
Preferably, the microchannel is including the first microchannel 401 on the bottom of the groove and positioned at described
The second microchannel 402 outside the sidewall extension line of groove.I.e. multiple first microchannel settings corresponding with chip in groove, it is more
A second microchannel extends to the region in groove outside the extended line of chip sides, to obtain more preferable heat dissipation effect, is dissipating
In the case that heat request is relatively low, the first microchannel of corresponding chip can be only made.
The depth of first microchannel and the second microchannel is not particularly limited, it extends certain to the first surface of silicon substrate
Distance, for example can extend to and be separated by certain thickness silicon substrate material with the bottom of groove, the bottom of groove can also be extended to
Portion, i.e. communication groove, can also further extend to paste in adhesive glue to groove or penetrate adhesive glue chip and terminate in
The back side of chip.Since the second microchannel is not opposite with groove and chip, more preferably, referring to Fig. 6, the depth of the second microchannel 402
Degree is more than the depth of the first microchannel 401, and the bottom of the groove is crossed in the bottom of the second microchannel, is preferably dissipated with obtaining
Thermal effect.Depth between multiple first microchannels or multiple second microchannels may be the same or different, it is preferred that adopt
The form that depth is identical is taken, referring to Fig. 5 and Fig. 6.
It is suitable for air cooling (nature or forced convertion) in the radiator structure that silicon substrate second surface makes.In order to be applicable in
The application of radiating requirements higher, it is preferred that be pasted with heat-dissipating cover plate 5 on the second surface of silicon substrate, in heat-dissipating cover plate formed with
The import passed in and out for coolant, the radiating flow passage for exporting and being connected between inlet and outlet, heat-dissipating cover plate sealing are described micro- logical
The opening in road, that is, make the microchannel radiator structure with heat-dissipating cover plate, can be used as liquid cooling.Wherein, dissipate under normal circumstances
Hot cover board can be made by silicon or glass, and the liquid entrance and radiating flow passage of heat-dissipating cover plate are by corrosion or laser technology system
Make.Cover board can also be made by metal, ceramics or other materials.Connection between cover board and silicon substrate can pass through polymer bonds
Close, metal bonding or other bonding technologies are realized.
Conductive fan-out structure is used for the second surface that the pad of chip is fanned out to silicon substrate, its structure is preferably：Bag
Include the dielectric layer 301 being formed on the first surface of chip and silicon substrate, be made in the pad that the chip is connected on dielectric layer
With the metal line 303 of the soldered ball 302 on the first surface of silicon substrate and the passivation layer 304 being layed on metal wiring layer.
Below in conjunction with attached drawing 1 to 5, to the wafer-level packaging method of the silicon substrate fan-out package of integrated heat dissipation structure of the present invention
It is described in detail.
A kind of wafer-level packaging method of the silicon substrate fan-out package of integrated heat dissipation structure includes the following steps：
A., one silicon substrate wafer 100, the second table of the silicon substrate disk with first surface 101 and corresponding thereto are provided
Face 102, etches to form at least one groove 103 with setting shape and depth in the first surface of the silicon substrate disk；
B. at least one chip 2 to be packaged of installation in the groove 103, makes the pad of the chip face-up；Tool
Body implementation can use, and at least one chip 2 to be packaged is first placed in the groove, faces the pad of the chip
On, then, certain thickness adhesive gel is coated with chip back, makes chip Nian Jie with bottom portion of groove and cures, forms adhesion layer
6, and the pad face of chip is approached or the first surface of parallel silicon substrate, and between having between the side wall of chip and the groove
Gap；
C. referring to Fig. 1, making conduction is fanned out on the first surface of the silicon substrate wafer and the pad face of the chip
Structure 3, by electrically fanning out on the first surface of the silicon substrate at least one pad；Embodiment can use, and lead to
Cross coating process, filled polymer glue in the gap between the side wall and chip of groove, and on the pad face of chip and
The first surface coated polymeric glue of silicon substrate, forms one layer of dielectric layer 301 after curing；Then, above the pad for opening chip
Dielectric layer, and on dielectric layer make connection chip pad metal line 303；Finally, made on metal line
Make one layer of passivation layer 304, need the position for planting soldered ball to open passivation layer on metal line, prepared on the metal line exposed
Required ubm layer, carries out salient point preparation or plants soldered ball 302.
D. referring to Fig. 3, the heat dissipation of corresponding each chip is directly made on the second surface of the silicon substrate wafer after step C
Structure, the radiator structure are included in the multiple microchannels 4 being intervally arranged directly made on the second surface of the silicon substrate,
The microchannel extends certain distance from the second surface of the silicon substrate to first surface；The microchannel is included positioned at described
The first microchannel 401 on the bottom of groove and the second microchannel 402 outside the sidewall extension line of the groove.
In this step, it is possible, firstly, to which not grinding crystal wafer, can be only ground to the overall thickness of the required encapsulation comprising radiator structure
Degree.The radiator structure of corresponding each chip is then produced in wafer scale by photoetching and etching process.It can also be cut using machinery
Cut the radiator structure that corresponding each chip is processed with laser technology.
In this step, can if the thickness of silicon substrate wafer is not enough to make radiator structure in the encapsulation of support wafer level
Silicon substrate wafer is pressure bonded on an interim support plate 8 by interim bonding material 7, referring to Fig. 2, and in the system for completing radiator structure
After work, interim support plate solution is bonded, referring to Fig. 4.If that is, when whole wafer is relatively thin, it is necessary on interim support plate
Complete wafer scale fabrication processing., can be without using interim support plate, directly on independent wafer if whole wafer is thicker
Complete wafer scale fabrication processing.
E. it is last, cutting crystal wafer, the silicon substrate fan-out package of formation integrated heat dissipation structure, referring to Fig. 5.
Air cooling is suitable for (certainly in the radiator structure that silicon substrate second surface makes by above-mentioned wafer-level packaging method
Right or forced convertion).In order to be applicable in the application of radiating requirements higher, it is preferred that referring to Fig. 7, on the second surface of silicon substrate
Heat-dissipating cover plate 5 is pasted with, the import passed in and out in heat-dissipating cover plate formed with confession coolant, export and be connected between inlet and outlet
Radiating flow passage, heat-dissipating cover plate seals the opening of the microchannel, that is, makes the microchannel radiator structure with heat-dissipating cover plate, can
As liquid cooling.
The silicon substrate fan-out package for making the integrated heat dissipation structure for having cover board only need to be on the basis of above-mentioned steps, increasing key
The step of closing heat-dissipating cover plate, that is to say, that after radiator structure can be produced on silicon substrate wafer, then be bonded by wafer scale
Technique, installs heat-dissipating cover plate on radiator structure.In cutting crystal wafer, the silicon substrate fan-out-type envelope of integrated heat dissipation structure can also be formed
After dress, by chip-scale bonding technology, heat-dissipating cover plate is installed on the radiator structure of silicon substrate.The pressure of cover board and wafer or chip
Conjunction can be realized by polymer-bound, metal bonding or other bonding technologies.
Above example is referring to the drawings, to a preferred embodiment of the present invention will be described in detail.Those skilled in the art
Member by above-described embodiment carry out various forms on modification or change, but without departing substantially from the present invention essence in the case of, all
Fall within the scope and spirit of the invention.
Claims (11)
1. a kind of silicon substrate fan-out package of integrated heat dissipation structure, including a silicon substrate, the silicon substrate have first surface and
Second surface, formed with least one groove extended to the second surface, the groove on the first surface of the silicon substrate
It is interior to be equipped with the chip of an at least pad upwardly, there is pad, the electricity of at least one pad on the pad face of the chip
Property is fanned out to by conductive fan-out structure on the first surface of the silicon substrate, it is characterised in that the second table of the silicon substrate
Directly being made on face has radiator structure.
2. the silicon substrate fan-out package of integrated heat dissipation structure according to claim 1, it is characterised in that the radiator structure
It is included in the multiple microchannels being intervally arranged directly made on the second surface of the silicon substrate, the microchannel is from the silicon
The second surface of matrix extends certain distance to first surface.
3. the silicon substrate fan-out package of integrated heat dissipation structure according to claim 2, it is characterised in that the microchannel
Shape of cross section is poroid or channel-like.
4. the silicon substrate fan-out package of integrated heat dissipation structure according to claim 2, it is characterised in that the microchannel bag
Include the first microchannel on the bottom positioned at the groove and second outside the sidewall extension line of the groove micro- logical
Road.
5. the silicon substrate fan-out package of integrated heat dissipation structure according to claim 4, it is characterised in that described second is micro- logical
The depth in road is more than the depth of first microchannel, and the bottom of the groove is crossed in the bottom of second microchannel.
6. according to the silicon substrate fan-out package of claim 2-5 any one of them integrated heat dissipation structures, it is characterised in that described
Heat-dissipating cover plate, import, the outlet passed in and out in the heat-dissipating cover plate formed with confession coolant are pasted with the second surface of silicon substrate
And the radiating flow passage between inlet and outlet is connected to, the heat-dissipating cover plate seals the opening of the microchannel.
7. the silicon substrate fan-out package of integrated heat dissipation structure according to claim 1, it is characterised in that the conduction is fanned out to
Dielectric layer that structure includes being formed on the first surface of the chip and the silicon substrate, be made on the dielectric layer and connect
The metal line of soldered ball on the first surface of the pad of the chip and the silicon substrate and it is layed in the metal wiring layer
On passivation layer.
8. a kind of wafer-level packaging method of the silicon substrate fan-out package of integrated heat dissipation structure, it is characterised in that including following step
Suddenly：
A., one silicon substrate wafer, second surface of the silicon substrate disk with first surface and corresponding thereto, described are provided
The first surface of silicon substrate disk etches to form at least one groove with setting shape and depth；
B., at least one chip to be packaged is installed in the groove, makes the pad of the chip face-up；
C. conductive fan-out structure is made on the first surface of the silicon substrate wafer and the pad face of the chip, will at least one
A pad is electrically fanned out on the first surface of the silicon substrate；
D. the radiator structure of corresponding each chip is directly made on the second surface of the silicon substrate wafer after step C, it is described to dissipate
Heat structure is included in the multiple microchannels being intervally arranged directly made on the second surface of the silicon substrate, and the microchannel is certainly
The second surface of the silicon substrate extends certain distance to first surface；
E. cutting crystal wafer, forms the silicon substrate fan-out package of integrated heat dissipation structure.
9. the wafer-level packaging method of the silicon substrate fan-out package of integrated heat dissipation structure according to claim 8, its feature
It is, when the thickness of the silicon substrate wafer is not enough to make radiator structure in the encapsulation of support wafer level, by silicon substrate after step C
Body wafer is pressure bonded on an interim support plate by interim bonding material, and after the making of radiator structure is completed, by interim support plate
Solution bonding.
10. the wafer-level packaging method of the silicon substrate fan-out package of integrated heat dissipation structure according to claim 8, its feature
It is, the radiator structure is produced by photoetching and etching process in step D, or use machine cuts and laser technology
Process the radiator structure.
11. the wafer-level packaging method of the silicon substrate fan-out package of integrated heat dissipation structure according to claim 8, its feature
It is, a heat-dissipating cover plate is mounted on the second surface of the silicon substrate wafer after step D, is had in the heat-dissipating cover plate for cooling
The import of liquid disengaging, the radiating flow passage for exporting and being connected between inlet and outlet, the heat-dissipating cover plate seal the microchannel
Opening.
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| CN201711364900.4A CN107946254A (en) | 2017-12-18 | 2017-12-18 | The silicon substrate fan-out package and wafer-level packaging method of integrated heat dissipation structure |
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| CN201711364900.4A CN107946254A (en) | 2017-12-18 | 2017-12-18 | The silicon substrate fan-out package and wafer-level packaging method of integrated heat dissipation structure |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010572A (en) * | 2018-12-29 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of big flow liquid cooling heat radiator and preparation method thereof for system class large power mould group |
| CN110379780A (en) * | 2019-07-31 | 2019-10-25 | 中国电子科技集团公司第五十八研究所 | A kind of silicon substrate fan-out-type wafer-level packaging method and structure |
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