CN107919344A - 半导体封装件 - Google Patents
半导体封装件 Download PDFInfo
- Publication number
- CN107919344A CN107919344A CN201710762839.2A CN201710762839A CN107919344A CN 107919344 A CN107919344 A CN 107919344A CN 201710762839 A CN201710762839 A CN 201710762839A CN 107919344 A CN107919344 A CN 107919344A
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- Prior art keywords
- semiconductor chip
- semiconductor
- pad
- package part
- redistributing layer
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Abstract
公开了一种半导体封装件,所述半导体封装件可以包括:第一再分布层(RDL);第一半导体芯片,位于第一RDL的顶表面上,第一半导体芯片包括第一电路表面和第一底表面,第一电路表面具有位于其上的第一I/O垫,第一I/O垫被构造为经由第一键合线将第一半导体芯片电连接到第一RDL;第二半导体芯片,位于第一半导体芯片上,第二半导体芯片包括第二电路表面和第二底表面;以及第二RDL,位于第二半导体芯片上,第二RDL面向第一电路表面和第二电路表面两者。
Description
本申请要求2016年10月10日提交的第10-2016-0130503号韩国专利申请的优先权及由此产生的所有权益,该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
本公开涉及一种半导体封装件。
背景技术
可以在单个晶圆上制造集成电路(IC)。可以将晶圆切割以获得可以被单独封装的单个裸片。半导体装置已变得尺寸越来越紧凑,功能越来越强大。另外,对于在给定的区域内集成尽可能多的元件的需求正在增长。因此,半导体封装件的尺寸已经逐渐减小。
用于半导体装置的小型化的封装方法的示例包括晶圆级封装(WLP),在晶圆级封装的方法中,可以在将晶圆切割成IC裸片之前封装IC。晶圆级封装件通常包括用于将IC裸片内的电路电连接到外部连接件的再分布层(RDL)。RDL可以用于IC裸片的接触垫的扇出布线。
发明内容
至少一些示例实施例涉及一种能够通过在扇出晶圆级封装件中垂直地堆叠多个半导体芯片以减小半导体封装的厚度来改善半导体封装件的良率的半导体封装件。
至少一些示例性实施例还涉及一种能够允许通过在扇出晶圆级封装件中垂直堆叠多个半导体芯片并经由键合线连接再分布层(RDL)与半导体芯片来使用各种连接方法的半导体封装件。
然而,示例实施例不限于在此阐述的那些。通过参照下面给出的本公开的详细描述,上述和其它示例实施例对于本公开所属领域的普通技术人员将变得更加明显。
根据一些示例实施例,半导体封装件可以包括:第一再分布层(RDL);第一半导体芯片,位于第一RDL的顶表面上,第一半导体芯片包括第一电路表面和第一底表面,第一电路表面具有位于其上的第一I/O垫,第一I/O垫被构造为经由第一键合线将第一半导体芯片电连接到第一RDL;第二半导体芯片,位于第一半导体芯片上,第二半导体芯片包括第二电路表面和第二底表面;以及第二RDL,位于第二半导体芯片上,第二RDL面向第一电路表面和第二电路表面两者。
根据一些其它示例性实施例,半导体封装件可以包括:第一半导体芯片,具有位于其顶表面上的第一I/O垫;第二半导体芯片,位于第一半导体芯片上,使得第一I/O垫被暴露,第二半导体芯片具有位于其顶表面上的接触件;第一RDL,位于第一半导体芯片下方,第一RDL经由第一键合线电连接到第一I/O垫;以及第二RDL,位于第二半导体芯片上,使得第二RDL覆盖接触件,第二RDL电连接到接触件。
根据一些其它示例性实施例,半导体封装件可以包括:多个半导体芯片,顺序地堆叠在第一再分布层(RDL)与第二RDL之间,多个半导体芯片均具有面向同一方向的电路表面,多个半导体芯片的占位面积从第一RDL向第二RDL减小,使得多个半导体芯片中的至少一个包括位于与其相关联的电路表面的暴露部分上的至少一个输入/输出(I/O)垫。
其它特征和示例性实施例可以通过以下详细描述、附图和权利要求而明显。
附图说明
通过参照附图详细描述本公开的一些示例实施例,本公开的以上和其它示例实施例以及特征将变得更加明显,在附图中:
图1是根据本公开的一些示例实施例的半导体封装件的平面图;
图2是沿图1的线A-A'截取的剖视图;
图3是根据本公开的一些示例实施例的半导体封装件的平面图;
图4是沿图3的线B-B'截取的剖视图;
图5是根据本公开的一些示例实施例的半导体封装件的平面图;
图6是沿图5的线C-C'截取的剖视图;
图7是根据本公开的一些示例实施例的半导体封装件的平面图;
图8是沿图7的线D-D'截取的剖视图;
图9是根据本公开的一些示例实施例的半导体封装件的平面图;
图10是沿图9的线E-E'截取的剖视图;
图11是根据本公开的一些示例实施例的半导体封装件的平面图;以及
图12是沿图11的线F-F'截取的剖视图。
具体实施方式
除非另有定义,否则在此使用的所有技术和科学术语具有与这些示例实施例所属领域的普通技术人员所通常理解的含义相同的含义。注意的是,除非另有规定,否则在此使用的任何和所有示例或提供的示例性术语仅仅旨在更好地阐明示例实施例,而不是对示例实施例的范围的限制。此外,除非另有定义,否则不会过度诠释在通常使用的字典中定义的所有术语。
本公开的示例实施例可以适用于集成扇出(InFO)封装件,但是示例实施例不限于此。例如,本公开的示例实施例也可以适用于各种其它半导体封装件。
在下文中将参照图1和图2描述根据本公开的一些示例实施例的半导体封装件。
图1是根据本公开的一些示例实施例的半导体封装件的平面图。图2是沿图1的线A-A'截取的剖视图。
参照图1和图2,根据一些示例实施例的半导体封装件可以包括第一再分布层(RDL)101和第二再分布层102、第一半导体芯片121和第二半导体芯片122以及第一键合线171。为了清楚起见,图1中未示出第二RDL 102和绝缘材料140。
第一RDL 101可以包括彼此相对的顶表面101U和底表面101L。第一RDL 101可以包括设置在第一RDL 101的底表面101L上的第一底指垫(pad,焊盘)101-1和设置在第一RDL101的顶表面101U上的第一顶指垫101-2。图1和图2示出了第一底指垫101-1和第一顶指垫101-2全部掩埋在第一RDL101中并且仅第一底指垫101-1的底表面和第一顶指垫101-2的顶表面部分别在第一RDL 101的底表面101L和顶表面101U处暴露的示例,但是示例实施例不限于该示例。
例如,在其它示例实施例中,第一底指垫101-1中的仅一些和第一顶指垫101-2中的仅一些可以掩埋在第一RDL 101中,而其它第一底指垫101-1和其它第一顶指垫101-2可以从第一RDL 101突出。又在其它示例实施例中,第一顶指垫101-2可以全部从第一RDL 101的顶表面101U突出,并且第一底指垫101-1可以全部从第一RDL 101的底表面101L突出。仍又在其它示例实施例中,第一底指垫101-1和第一顶指垫101-2可以以前述示例的任意组合来布置。
图1和图2示出了将期望的(或者,可选地,预定的)数量的第一底指垫101-1和期望的(或者,可选地,预定的)数量的第一顶指垫101-2设置在第一RDL 101中的示例,但是示例实施例不限于此。也就是说,在其它示例实施例中,必要时可以将不同数量的第一底指垫101-1和不同数量的第一顶指垫101-2设置在第一RDL 101中。
第一底指垫101-1和第一顶指垫101-2可以包括例如导电材料。第一底指垫101-1和第一顶指垫101-2可以电连接第一RDL 101与设置在第一RDL101外部(例如,设置在第一RDL 101的顶表面101U或底表面101L上)的组件。
第一RDL 101可以包括设置在第一RDL 101中的特别是设置在第一RDL101的顶表面101U与底表面101L之间的导电图案。导电图案的示例可以包括图案化的通孔和垫。例如,第一顶指垫101-2和第一底指垫101-1可以经由第一RDL 101中的图案化的导电图案来电连接。
第一下接触垫101P1可以设置在第一RDL 101的顶表面101U中或上。例如,如图2中所示,第一下接触垫101P1可以全部掩埋在第一RDL 101中,并且仅第一下接触垫101P1的顶表面可以在第一RDL 101的顶表面101U处暴露。然而,示例实施例不限于图2的示例。也就是说,在其它示例实施例中,第一下接触垫101P1中的至少一些可以掩埋在第一RDL 101中。又在其它示例实施例中,第一下接触垫101P1可以全部设置在第一RDL 101上,以从第一RDL101的顶表面101U突出。
第一下接触垫101P1可以包括例如导电材料。
第一下接触垫101P1可以连接到第一键合线171,并且可以因此使第一半导体芯片121与第一RDL 101电连接。
外部连接端子100可以设置在第一RDL 101的底表面101L上。外部连接端子100可以分别接触多个第一底指垫101-1,并且可以分别电连接到第一底指垫101-1。外部连接端子100可以电连接到半导体封装件外部的组件。例如,外部连接端子100可以将半导体封装件与具有与所述半导体封装件类似的设计的另一半导体封装件电连接。在其它示例实施例中,外部连接端子100可以使半导体封装件与外部半导体装置电连接。
图1和图2示出了外部连接端子100为焊球的示例,但是示例实施例不限于该示例。也就是说,在其它示例实施例中,外部连接端子100可以是焊料凸块、栅格阵列和/或导电接线片。
多个外部连接端子100可以形成在第一RDL 101的底表面101L上。
第一半导体芯片121可以设置在第一RDL 101的顶表面101U上。第一半导体芯片121可以包括彼此相对的第一电路表面121U和第一底表面121L。第一半导体芯片121的第一底表面121L可以与例如第一RDL 101的顶表面101U接触。
第一半导体芯片121的第一电路表面121U可以是例如形成电路图案的表面。另外,第一半导体芯片121的第一电路表面121U可以是例如形成第一输入/输出(I/O)垫121P的表面。第一半导体芯片121的第一底表面121L可以是例如与形成电路图案的表面相对的表面。
在一些示例实施例中,第一半导体芯片121的第一电路表面121U可以设置为面向第一方向D1+。例如,第一半导体芯片121的第一电路表面121U可以设置为面向稍后将描述的第二RDL 102。
第一半导体芯片121可以是例如逻辑芯片,但是示例实施例不限于此。也就是说,可以根据需要使用各种其它芯片作为第一半导体芯片121。
第一半导体芯片121的第一电路表面121U可以包括第一I/O垫121P。换句话说,第一I/O垫121P可以设置在第一半导体芯片121的第一电路表面121U上。图1和图2示出了第一I/O垫121P全部设置在第一半导体芯片121的第一电路表面121U上以从第一半导体芯片121的第一电路表面121U突出的示例,但是示例实施例不限于该示例。
也就是说,在其它示例实施例中,第一I/O垫121P中的至少一些可以设置在第一半导体芯片121的第一电路表面121U上。又在其它示例实施例中,第一I/O垫121P可以全部设置在第一半导体芯片121的第一电路表面121U下方,使得仅第一I/O垫121P的顶表面可以在第一半导体芯片121的第一电路表面121U处暴露。
第一I/O垫121P可以包括例如导电材料。
第一键合线171可以连接第一I/O垫121P和第一下接触垫101P1。也就是说,第一半导体芯片121可以经由与第一I/O垫121P连接的第一键合线171电连接到第一RDL 101。
在根据一些示例实施例的半导体封装件中,第一半导体芯片121(垂直堆叠的多个半导体芯片中的一个)经由第一键合线171连接到第一RDL 101。因此,可以使用各种连接方法。另外,可以减小根据至少一些示例实施例的半导体封装件的厚度,结果,可以改善根据至少一些示例实施例的半导体封装件的良率。
第二半导体芯片122可以设置在第一半导体芯片121上。更具体地,第二半导体芯片122可以设置在第一半导体芯片121的第一电路表面121U上。在一些示例实施例中,第二半导体芯片122可以设置在第一半导体芯片121上,以暴露第一半导体芯片121的第一I/O垫121P。第二半导体芯片122可以包括彼此相对的第二电路表面122U和第二底表面122L。第二半导体芯片122的第二电路表面122U可以接触例如稍后将描述的第二RDL 102的底表面102L。
第二半导体芯片122的第二电路表面122U可以是例如形成电路图案的表面。另外,第二半导体芯片122的第二电路表面122U可以是例如形成接触件122C的表面。第二半导体芯片122的第二底表面122L可以是例如与形成接触件122C的表面相对的表面。
在一些示例实施例中,第二半导体芯片122的第二电路表面122U可以设置为面向第一方向D1+。例如,第二半导体芯片122的第二电路表面122U可以设置为面向稍后将描述的第二RDL 102。
也就是说,第一半导体芯片121的第一电路表面121U和第二半导体芯片122的第二电路表面122U可以设置为面向同一方向,例如,第一方向D1+。
在根据一些示例实施例的半导体封装件中,第一半导体芯片121的第一电路表面121U和第二半导体芯片122的第二电路表面122U可以设置为面向同一方向,例如,第一方向D1+。因此,可以使用各种连接方法,并且可以减小根据至少一些示例实施例的半导体封装件的厚度。
第二半导体芯片122可以是NAND闪存芯片、动态随机存取存储器(DRAM)芯片、闪存芯片或电阻可变存储器芯片,但是本公开不限于此。
第二半导体芯片122的第二电路表面122U可以包括接触件122C。换句话说,接触件122C可以设置在第二半导体芯片122的第二电路表面122U上。接触件122C可以置于第二半导体芯片122的第二电路表面122U与第二RDL102之间。
接触件122C可以包括例如导电材料。
接触件122C可以使第二半导体芯片122和第二RDL 102电连接。
绝缘材料140可以设置在第二半导体芯片122与第二RDL 102之间。绝缘材料140可以设置在接触件122C之间。
电连接到接触件122C的I/O垫(未示出)可以进一步设置在第二半导体芯片122的第二电路表面122U上。例如,在第二半导体芯片122的第二电路表面122U进一步包括I/O垫的情况下,第二半导体芯片122可以经由I/O垫电连接到第二RDL 102。接触件122C可以置于I/O垫与第二RDL 102之间,并且可以因此使第二半导体芯片122和第二RDL 102电连接。
第二RDL 102可以设置在第二半导体芯片122上。第二RDL102可以设置在第二半导体芯片122上,以覆盖第二半导体芯片122的接触件122C。
第二RDL 102可以包括彼此相对的顶表面102U和底表面102L。第二RDL 102可以包括设置在第二RDL 102的底表面102L上的第二底指垫102-2。图1和图2示出了第二底指垫102-2全部掩埋在第二RDL 102中并且仅第二底指垫102-2的底表面暴露于第二RDL 102外部的示例,但是本公开不限于该示例。
也就是说,在其它示例实施例中,仅第二底指垫102-2中的一些可以掩埋在第二RDL 102中,其它第二底指垫102-2可以从第二RDL 102突出。又在其它示例实施例中,第二底指垫102-2可以全部从第二RDL 102的底表面102L突出。仍又在其它实例中,第二底指垫102-2可以以前述示例的任意组合来布置。
图1和图2示出了期望的(或者,可选地,预定的)数量的第二底指垫102-2设置在第二RDL 102中的示例,但是示例实施例不限于该示例。也就是说,在其它示例实施例中,必要时可以将不同数量的第二底指垫102-2设置在第二RDL 102中。
第二底指垫102-2可以包括例如导电材料。第二底指垫102-2可以使第二RDL 102与设置在第二RDL 102外部的组件电连接。
第二顶指垫(未示出)可以进一步设置在第二RDL 102的顶表面102U上。第二顶指垫可以使第二RDL 102与设置在第二RDL 102外部的组件电连接。
第二RDL 102可以包括设置在第二RDL 102的顶表面102U与底表面102L之间的导电图案。导电图案的示例可以包括图案化的通孔和垫。例如,第二底指垫102-2可以经由第二RDL 102中的图案化的导电图案电连接到第二RDL 102的顶表面102U。
上接触垫102P可以设置在第二RDL 102的底表面102L上或中。图1和图2示出了上接触垫102P掩埋在第二RDL 102中并且仅上接触垫102P的底表面在第二RDL 102的底表面102L处暴露的示例,但是示例实施例不限于该示例。也就是说,在其它示例实施例中,上接触垫102P中的至少一些可以掩埋在第二RDL 102中。又在其它示例实施例中,上接触垫102P可以全部设置在第二RDL 102的底表面102L上,以从第二RDL 102的底表面102L突出。
上接触垫102P可以包括例如导电材料。
上接触垫102P可以连接到接触件122C,并且可以因此使第二半导体芯片122与第二RDL 102电连接。
第一粘合层131可以置于第一半导体芯片121与第二半导体芯片122之间。更具体地,第一粘合层131使第一半导体芯片121的第一电路表面121U与第二半导体芯片122的第二底表面122L接触。
第一粘合层131可以设置为提供第一半导体芯片121与第二半导体芯片122之间的粘附。第一粘合层131可以包括紫外(UV)胶、压敏粘合剂、可辐射固化粘合剂、环氧树脂或它们的组合。
第一过孔151和第二过孔152可以设置在第一RDL 101与第二RDL 102之间,并且可以连接第一RDL 101和第二RDL 102。第一过孔151和第二过孔152可以彼此间隔开。由于第一过孔151和第二过孔152可以彼此间隔开,所以第一半导体芯片121和第二半导体芯片122可以设置在第一过孔151与第二过孔152之间。第一过孔151和第二过孔152可以连接第二底指垫102-2和第一顶指垫101-2。
在下文中将参照图3和图4来描述根据本公开的一些示例实施例的半导体封装件,为了清楚起见,避免了冗余的描述。
图3是根据本公开的一些示例实施例的半导体封装件的平面图。图4是沿图3的线B-B'截取的剖视图。为了清楚起见,未在图3中示出第二RDL 102和绝缘材料140。
参照图3和图4,根据一些示例实施例的半导体装置可以进一步包括设置在第一半导体芯片121与第二半导体芯片122之间的第三半导体芯片123。更具体地,第三半导体芯片123可以设置在第一半导体芯片121的第一电路表面121U与第二半导体芯片122的第二底表面122L之间。
第三半导体芯片123可以设置在第一半导体芯片121上,以暴露第一半导体芯片121的第一I/O垫121P。第三半导体芯片123可以具有比第一半导体芯片121的占位面积小的占位面积,以暴露第一I/O垫121P。
第三半导体芯片123可以包括彼此相对的第三电路表面123U和第三底表面123L。第三半导体芯片123的第三电路表面123U可以是例如形成电路图案的表面。另外,第三半导体芯片123的第三电路表面123U可以是例如形成第三I/O垫123P的表面。第三半导体芯片123的第三底表面123L可以是例如与形成电路图案的表面相对的表面。
在一些示例实施例中,第三半导体芯片123的第三电路表面123U可以设置为面向第一方向D1+。例如,第三半导体芯片123的第三电路表面123U可以设置为面向第二RDL102。
也就是说,第一半导体芯片121至第三半导体芯片123的第一电路表面121U至第三电路表面123U可以设置为面向同一方向,例如,第一方向D1+。
第三半导体芯片123的第三电路表面123U可以包括第三I/O垫123P。换句话说,第三I/O垫123P可以设置在第三半导体芯片123的第三电路表面123U上。第二半导体芯片122可以设置在第三半导体芯片123上,以暴露第三半导体芯片123的第三I/O垫123P。第二半导体芯片122可以具有比第三半导体芯片123的占位面积的小的占位面积,以暴露第三I/O垫123P。
图3和图4示出了第三I/O垫123P全部设置在第三半导体芯片123的第三电路表面123U上以从第三半导体芯片123的第三电路表面123U突出的示例,但是示例实施例不限于该示例。
例如,第三I/O垫123P中的至少一些可以设置在第三半导体芯片123的第三电路表面123U上。在其它示例实施例中,第三I/O垫123P可以设置在第三半导体芯片123的第三电路表面123U下方,使得仅第三I/O垫123P的顶表面可以在第三半导体芯片123的第三电路表面123U处暴露。
第三I/O垫123P可以包括例如导电材料。
第二键合线172可以使第三I/O垫123P和第二下接触垫101P2连接。也就是说,第三半导体芯片123可以经由与第三I/O垫123P连接的第二键合线172电连接到第一RDL 101。
第一RDL 101可以进一步包括与第一下接触垫101P1间隔开的第二下接触垫101P2。第二下接触垫101P2可以连接到第二键合线172。第二下接触垫101P2可以与例如第一下接触垫101P1基本上相同。
第二粘合层132可以置于第二半导体芯片122与第三半导体芯片123之间。更具体地,第二粘合层132可以使第三半导体芯片123的第三电路表面123U和第二半导体芯片122的第二底表面122L接触。
在下文中将参照图5和图6描述根据本公开的一些示例实施例的半导体封装件,为了清楚起见,避免了冗余的描述。
图5是根据本公开的一些示例实施例的半导体封装件的平面图。图6是沿图5的线C-C'截取的剖视图。为了清楚起见,未在图5中示出第二RDL 102和绝缘材料140。
参照图5和图6,第二半导体芯片122可以经由第三键合线173连接到第一RDL 101,而不是经由图2的接触件122C连接到第二RDL 102。
第二半导体芯片122可以包括设置在第二半导体芯片122的第二电路表面122U上的第二I/O垫122P。第二半导体芯片122可以经由第三键合线173电连接到第一RDL 101。
例如,第三键合线173可以使第二I/O垫122P和第二下接触垫101P2接触。
第二RDL 102可以设置在第二半导体芯片122上,以覆盖第二半导体芯片122的第二I/O垫122P。
在本示例实施例中,与前面的示例实施例中相似,第一半导体芯片121的第一电路表面121U和第二半导体芯片122的第二电路表面122U可以设置为面向同一方向,例如,第一方向D1+。
在下文中将参照图7和图8描述根据本公开的一些示例实施例的半导体封装件,为了清楚起见,避免了冗余的描述。
图7是根据本公开的一些示例性实施例的半导体封装件的平面图。图8是沿图7的线D-D'截取的剖视图。为了清楚起见,未在图7中示出第二RDL102和绝缘材料140。
参照图7和图8,第一半导体芯片121和第二半导体芯片122可以具有基本上相同的尺寸。第一键合线171可以穿透第一粘合层131,以使第一I/O垫121P和第一下接触垫101P1连接。
第一I/O垫121P可以掩埋在第一粘合层131中,但是示例实施例不限于此。第一I/O垫121P可以形成为不从例如第一半导体芯片121的第一电路表面121U突出。
在下文中将参照图9和图10描述根据本公开的一些示例实施例的半导体封装件,为了清楚起见,避免了冗余的描述。
图9是根据本公开的一些示例实施例的半导体封装件的平面图。图10是沿图9的线E-E'截取的剖视图。为了清楚起见,未在图9中示出第二RDL 102和绝缘材料140。
参照图9和图10,根据一些示例实施例的半导体封装件可以进一步包括设置在第二半导体芯片122与第一RDL 101之间的第四半导体芯片124。
第四半导体芯片124可以设置在第一RDL 101的顶表面101U上,特别是设置在第一RDL 101与第二半导体芯片122的第二底表面122L之间。第四半导体芯片124可以与第一半导体芯片121间隔开。
第四半导体芯片124可以包括彼此相对的第四电路表面124U和第四底表面124L。第四半导体芯片124的第四底表面124L可以与例如第一RDL 101的顶表面101U接触。
第四半导体芯片124的第四电路表面124U可以是例如形成电路图案的表面。另外,第四半导体芯片124的第四电路表面124U可以是例如形成第四I/O垫124P的表面。第四半导体芯片124的第四电路表面124U可以是例如与形成电路图案的表面相对的表面。第二半导体芯片122可以具有比其间具有间隙的第一半导体芯片121和第四半导体芯片124的占位面积小的占位面积,以暴露第四I/O垫124P。
在一些示例实施例中,第四半导体芯片124的第四电路表面124U可以设置为面向第一方向D1+。例如,第四半导体芯片124的第四电路表面124U可以设置为面向第二RDL102。
也就是说,第一半导体芯片121的第一电路表面121U、第二半导体芯片122的第二电路表面122U和第四半导体芯片124的第四电路表面124U可以设置为面向同一方向,例如,第一方向D1+。
第四半导体芯片124的第四电路表面124U可以包括第四I/O垫124P。换句话说,第四I/O垫124P可以设置在第四半导体芯片124的第四电路表面124U上。图9和图10示出了第四I/O垫124P全部设置在第四半导体芯片124的第四电路表面124U上以从第四半导体芯片124的第四电路表面124U突出的示例,但是示例实施例不限于该示例。
也就是说,在其它示例实施例中,第四I/O垫124P中的至少一些可以设置在第四半导体芯片124的第四电路表面124U上。又在其它示例实施例中,第四I/O垫124P可以全部设置在第四半导体芯片124的第四电路表面124U下方,使得仅第四I/O垫124P的顶表面可以在第四半导体芯片124的第四电路表面124U处暴露。
第四I/O垫124P可以包括例如导电材料。
第四键合线174可以使第四I/O垫124P和第三下接触垫101P3连接。也就是说,第四半导体芯片124可以经由与第四I/O垫124P连接的第四键合线174电连接到第一RDL 101。
第一RDL 101可以进一步包括第三下接触垫101P3。第三下接触垫101P3可以与第一下接触垫101P1间隔开。第三下接触垫101P3可以与例如第一下接触垫101P1基本上相同。
第一粘合层131可以置于第一半导体芯片121的第一电路表面121U与第二半导体芯片122的第二底表面122L之间以及第四半导体芯片124的第四电路表面124U与第二半导体芯片122的第二底表面122L之间。例如,第一粘合层131的一部分可以接触第一半导体芯片121的第一电路表面121U,并且第一粘合层131的另一部分可以接触第四半导体芯片124的第四电路表面124U。
第二半导体芯片122可以设置在第一半导体芯片121和第四半导体芯片124上,以暴露第一半导体芯片121的第一I/O垫121P和第四半导体芯片124的第四I/O垫124P。换句话说,第一半导体芯片121和第四半导体芯片124的部分可以在第一方向D1+上与第二半导体芯片122叠置。
在一些示例实施例中,第一半导体芯片121和第四半导体芯片124可以均设置为与第二半导体芯片122叠置,在这种情况下,第一键合线171可以穿透第一粘合层131以分别连接到第一下接触垫101P1,并且第四键合线174可以穿透第一粘合层131以分别连接到第三下接触垫101P3。第一I/O垫121P可以形成为不从第一半导体芯片121的第一电路表面121U突出,并且第四I/O垫124P可以形成为不从第四半导体芯片124的第四电路表面124U突出。
在下文中将参照图11和图12描述根据本公开的一些示例实施例的半导体封装件,为了清楚起见,避免了冗余的描述。
图11是根据本公开的一些示例实施例的半导体封装件的平面图。图12是沿图11的线F-F'截取的剖视图。为了清楚起见,未在图11中示出第二RDL102和绝缘材料140。
参照图11和图12,根据本示例实施例的半导体封装件可以进一步包括设置在第一半导体芯片121与第四半导体芯片124之间的第五半导体芯片125。
第五半导体芯片125可以设置在第一RDL 101的顶表面101U上,特别是设置在第一RDL 101与第二半导体芯片122的第二底表面122L之间。第五半导体芯片125可以与第一半导体芯片121和第四半导体芯片124间隔开,并且可以设置在第一半导体芯片121与第四半导体芯片124之间。
第五半导体芯片125可以包括彼此相对的第五电路表面125U和第五底表面125L。
第五半导体芯片125的第五电路表面125U可以是例如形成电路图案的表面。另外,第五半导体芯片125的第五电路表面125U可以是例如形成第五I/O垫125P的表面。第五半导体芯片125的第五电路表面125U可以是例如与形成电路图案的表面相对的表面。
在一些示例实施例中,第五半导体芯片125的第五电路表面125U可以设置为面向第二方向D1-。例如,第五半导体芯片125的第五电路表面125U可以设置为面向第一RDL101。例如,第五半导体芯片125可以以倒装芯片的形式设置在第一RDL 101上。
也就是说,第一半导体芯片121的第一电路表面121U、第二半导体芯片122的第二电路表面122U和第四半导体芯片124的第四电路表面124U可以设置为与第五半导体芯片125的第五电路表面125U面向相反的方向。
第五半导体芯片125的第五电路表面125U可以包括第五I/O垫125P。
第一RDL 101可以进一步包括第四下接触垫101P4。第四下接触垫101P4可以与第一下接触垫101P1和第三下接触垫101P3间隔开。
第五半导体芯片125可以经由连接端子180电连接到第一RDL 101。连接端子180可以设置在第五半导体芯片125的第五电路表面125U与第一RDL101的顶表面101U之间。连接端子180可以连接到第五I/O垫125P和第四下接触垫101P4。
第一粘合层131可以置于第一半导体芯片121的第一电路表面121U与第二半导体芯片122的第二底表面122L之间、第四半导体芯片124的第四电路表面124U与第二半导体芯片122的第二底表面122L之间以及第五半导体芯片125的第五底表面125L与第二半导体芯片122的第二底表面122L之间。例如,第一粘合层131的一部分可以接触第一半导体芯片121的第一电路表面121U,第一粘合层131的另一部分可以接触第四半导体芯片124的第四电路表面124U,并且第一粘合层131的另一部分可以接触第五半导体芯片125的第五底表面125L。
虽然已经参照发明构思的一些示例实施例具体地示出和描述了发明构思的示例实施例,但是本领域普通技术人员将理解的是,在不脱离由权利要求所限定的发明构思的示例实施例的精神和范围的情况下,在此可以做出形式上和细节上的各种改变。因此期望的是,示例性实施例在各方面被认为是说明性的而不是限制性的,参照所附权利要求而不是前述描述来指示示例实施例的范围。
Claims (20)
1.一种半导体封装件,所述半导体封装件包括:
第一再分布层;
第一半导体芯片,位于第一再分布层的顶表面上,第一半导体芯片包括第一电路表面和第一底表面,第一电路表面具有位于其上的第一输入/输出垫,第一输入/输出垫被构造为经由第一键合线将第一半导体芯片电连接到第一再分布层;
第二半导体芯片,位于第一半导体芯片上,第二半导体芯片包括第二电路表面和第二底表面;以及
第二再分布层,位于第二半导体芯片上,第二再分布层面向第一电路表面和第二电路表面两者。
2.根据权利要求1所述的半导体封装件,其中,第二半导体芯片包括位于其第二电路表面上的接触件,接触件置于第二电路表面与第二再分布层之间,使得接触件将第二半导体芯片电连接到第二再分布层。
3.根据权利要求1所述的半导体封装件,其中,第二半导体芯片包括第二输入/输出垫,第二输入/输出垫经由第二键合线将第二半导体芯片电连接到第一再分布层。
4.根据权利要求1所述的半导体封装件,所述半导体封装件还包括:
第三半导体芯片,位于第一半导体芯片与第二半导体芯片之间,第三半导体芯片包括第三电路表面和第三底表面,第三电路表面面向第二再分布层。
5.根据权利要求4所述的半导体封装件,其中,
第三半导体芯片包括经由第三键合线将第三半导体芯片电连接到第一再分布层的第三输入/输出垫,并且
第二半导体芯片包括位于其第二电路表面上的接触件,接触件置于第二电路表面与第二再分布层之间,使得接触件将第二半导体芯片电连接到第二再分布层。
6.根据权利要求1所述的半导体封装件,所述半导体封装件还包括:
第三半导体芯片,位于第一再分布层的顶表面上,使得第三半导体芯片与第一半导体芯片之间具有间隙,第三半导体芯片包括第三电路表面和第三底表面,第三电路表面面向第二再分布层,第三半导体芯片包括位于第三电路表面上的第三输入/输出垫,第三输入/输出垫经由第三键合线将第三半导体芯片电连接到第一再分布层。
7.根据权利要求6所述的半导体封装件,所述半导体封装件还包括:
第四半导体芯片,位于第一半导体芯片与第三半导体芯片之间的间隙中,第四半导体芯片包括第四电路表面和第四底表面,第四电路表面面向第一再分布层,使得第四电路表面与第一输入/输出垫面向相反的方向。
8.根据权利要求6所述的半导体封装件,其中,第二半导体芯片包括位于其第二电路表面上的接触件,接触件位于第二电路表面与第二再分布层之间,使得接触件将第二半导体芯片电连接到第二再分布层。
9.根据权利要求1所述的半导体封装件,所述半导体封装件还包括:
第一过孔和第二过孔,位于第一再分布层与第二再分布层之间,第一过孔和第二过孔均连接第一再分布层和第二再分布层,第一过孔和第二过孔彼此间隔开,并且在它们之间具有第一半导体芯片和第二半导体芯片。
10.一种半导体封装件,所述半导体封装件包括:
第一半导体芯片,具有位于其顶表面上的第一输入/输出垫;
第二半导体芯片,位于第一半导体芯片上,使得第一输入/输出垫被暴露,第二半导体芯片具有位于其顶表面上的接触件;
第一再分布层,位于第一半导体芯片下方,第一再分布层经由第一键合线电连接到第一输入/输出垫;以及
第二再分布层,位于第二半导体芯片上,使得第二再分布层覆盖接触件,第二再分布层电连接到接触件。
11.根据权利要求10所述的半导体封装件,所述半导体封装件还包括:
第三半导体芯片,位于第一半导体芯片与第二半导体芯片之间,并且具有比第一半导体芯片的占位面积小的占位面积,以暴露第一输入/输出垫,第三半导体芯片包括位于其顶表面上的第二输入/输出垫,其中,
第二半导体芯片具有比第三半导体芯片的占位面积的小的占位面积,以暴露第二输入/输出垫,并且
第三半导体芯片经由第二输入/输出垫和第二键合线电连接到第一再分布层。
12.根据权利要求10所述的半导体封装件,其中,第一半导体芯片的顶表面和第二半导体芯片的顶表面面向同一方向,使得第一输入/输出垫和接触件面向同一方向。
13.根据权利要求10所述的半导体封装件,所述半导体封装件还包括:
第三半导体芯片,位于第一再分布层上,使得第三半导体芯片与第一半导体芯片之间具有间隙,第三半导体芯片包括位于其顶表面上的第二输入/输出垫,第二输入/输出垫将第三半导体芯片电连接到第一再分布层,其中,
第二半导体芯片具有比其间具有间隙的第一半导体芯片和第三半导体芯片的占位面积小的占位面积,以暴露第二输入/输出垫。
14.根据权利要求13所述的半导体封装件,其中,第一半导体芯片的顶表面、第二半导体芯片的顶表面和第三半导体芯片的顶表面面向同一方向,使得第一输入/输出垫、接触件和第二输入/输出垫面向同一方向。
15.根据权利要求13所述的半导体封装件,所述半导体封装件还包括:
第四半导体芯片,位于第一半导体芯片与第三半导体芯片之间的间隙中,第四半导体芯片包括位于其表面上的第三输入/输出垫,第四半导体芯片的所述表面与第一半导体芯片的顶表面和第三半导体芯片的顶表面面向相反的方向,使得第三输入/输出垫与第一输入/输出垫和第二输入/输出垫面向相反的方向。
16.一种半导体封装件,所述半导体封装件包括:
多个半导体芯片,顺序地堆叠在第一再分布层与第二再分布层之间,所述多个半导体芯片均具有面向同一方向的电路表面,所述多个半导体芯片的占位面积从第一再分布层向第二再分布层减小,使得所述多个半导体芯片中的至少一个包括位于与其相关联的电路表面的暴露部分上的至少一个输入/输出垫。
17.根据权利要求16所述的半导体封装件,其中,所述多个半导体芯片包括顺序地堆叠在第一再分布层与第二再分布层之间的第一半导体芯片和第二半导体芯片,第二半导体芯片的占位面积小于第一半导体芯片的占位面积,第一半导体芯片的电路表面包括其上具有所述至少一个输入/输出垫的第一输入/输出垫的暴露部分,第一输入/输出垫经由第一键合线电连接到第一再分布层。
18.根据权利要求17所述的半导体封装件,其中,第二半导体芯片包括位于与其相关联的电路表面上的接触件,使得接触件将第二半导体芯片电连接到第二再分布层。
19.根据权利要求17所述的半导体封装件,其中,第二半导体芯片的电路表面包括其上具有所述至少一个输入/输出垫的第二输入/输出垫的暴露部分,第二输入/输出垫经由第二键合线将第二半导体芯片电连接到第一再分布层。
20.根据权利要求17所述的半导体封装件,其中,第一半导体芯片包括位于第一再分布层上的其间具有间隙的两个第一半导体芯片,所述两个第一半导体芯片中的每个包括位于其上的第一输入/输出垫中的至少一个,第二半导体芯片的占位面积小于其间具有间隙两个第一半导体芯片的占位面积,以暴露第一输入/输出垫。
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