CN107887261A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN107887261A CN107887261A CN201610871131.6A CN201610871131A CN107887261A CN 107887261 A CN107887261 A CN 107887261A CN 201610871131 A CN201610871131 A CN 201610871131A CN 107887261 A CN107887261 A CN 107887261A
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 83
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 62
- 239000000463 material Substances 0.000 claims description 33
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 239000000126 substance Substances 0.000 claims description 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 239000000908 ammonium hydroxide Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 125000004429 atom Chemical group 0.000 claims description 2
- 238000005253 cladding Methods 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910002804 graphite Inorganic materials 0.000 description 6
- 239000010439 graphite Substances 0.000 description 6
- -1 graphite Alkene Chemical class 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 4
- 229910052582 BN Inorganic materials 0.000 description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- HADKRTWCOYPCPH-UHFFFAOYSA-M trimethylphenylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C1=CC=CC=C1 HADKRTWCOYPCPH-UHFFFAOYSA-M 0.000 description 3
- 150000001336 alkenes Chemical class 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 150000003377 silicon compounds Chemical class 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02527—Carbon, e.g. diamond-like carbon
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- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- Carbon And Carbon Compounds (AREA)
Abstract
本发明公开了一种半导体装置及其制造方法,涉及半导体工艺技术领域。该方法包括:形成生长衬底,形成生长衬底包括:提供衬底结构,衬底结构包括牺牲衬底和在牺牲衬底上的第一电介质层,衬底结构中形成有贯穿第一电介质层的多个凹陷,并且凹陷的底部和部分侧壁位于牺牲衬底中,在凹陷的底部和部分侧壁上形成垫层,选择性地在所述垫层上生长石墨烯层,以及在凹陷中填充第二电介质层;以第二电介质层的顶部面对接合衬底的方式,将生长衬底附接到接合衬底之上;去除牺牲衬底;去除垫层,从而露出石墨烯层。本发明采用在垫层上选择性生长石墨烯的方式,避免了现有技术中图案化工艺对石墨烯的影响。
Description
技术领域
本发明涉及半导体工艺技术领域,尤其涉及半导体装置及其制造方法,更具体地,涉及石墨烯半导体装置及其制造方法。
背景技术
石墨烯是一种以碳原子构成的二维材料,具有零禁带宽度和高载流子迁移率的特点。在2004年被发现以来,石墨烯被期待可用来发展更薄、导电速度更快的新一代电子元件或晶体管。
现有的图案化石墨烯的方法,主要包括光刻法和激光直写法。激光直写法虽然在图案化石墨烯的过程中不会引入其它试剂,但是该方法得到的图案化的石墨烯层存在不够精细、生产周期长的缺点。而光刻法在刻蚀中会引入其它试剂,其使用的显影液、剥离液会带来增加得到的图案化的石墨烯方阻等问题。
因此,如何制造具有图案化的石墨烯层的器件,是目前半导体工艺中的挑战之一。
发明内容
本发明的发明人发现了上述现有技术中存在问题,并针对上述问题中的至少一个问题提出了本发明。
根据本发明的一个方面,提供一种半导体装置的制造方法,包括:形成生长衬底,形成生长衬底包括:提供衬底结构,衬底结构包括牺牲衬底和在牺牲衬底上的第一电介质层,衬底结构中形成有多个凹陷,凹陷贯穿第一电介质层,并且凹陷的底部和部分侧壁位于牺牲衬底中,在凹陷的底部和部分侧壁上形成垫层,选择性地在垫层上生长石墨烯层,以及在凹陷中填充第二电介质层;以第二电介质层的顶部面对接合衬底的方式,将生长衬底附接到接合衬底之上;去除牺牲衬底;去除垫层,从而露出石墨烯层。
在一个实施例中,形成生长衬底还包括:在填充第二电介质层之后,进行平坦化,以使得第二电介质层的顶部与第一电介质层的顶部基本齐平。
在一个实施例中,在凹陷的底部和部分侧壁上形成垫层包括:利用外延生长工艺,在凹陷的底部和部分侧壁生长垫层。
根据本发明的另一个方面,提供了半导体装置的另一种制造方法,包括:提供生长衬底,生长衬底包括:牺牲衬底和在牺牲衬底上的第一电介质层,牺牲衬底中形成有多个凹陷,凹陷贯穿第一电介质层,并且凹陷的底部和部分侧壁位于牺牲衬底中,以及在凹陷的底部和部分侧壁上的垫层;选择性地在垫层上生长石墨烯层;在凹陷中填充第二电介质层;以第二电介质层的顶部面对接合衬底的方式,将生长衬底附接到接合衬底之上;去除牺牲衬底;以及去除垫层,从而露出石墨烯层。
在一个实施例中,填充第二电介质层包括:利用原子层沉积工艺或物理气相沉积工艺在凹陷中填充第二电介质层。
在一个实施例中,第二电介质层的材料包括:不导电的硼的氮化物,或硅的氧化物。
在一个实施例中,生长石墨烯层包括:利用甲烷和氢气,选择性地在垫层上生长石墨烯层。
在一个实施例中,牺牲衬底的材料包括硅。
在一个实施例中,其中去除牺牲衬底是通过湿法工艺利用蚀刻剂进行的。
在一个实施例中,蚀刻剂包括四甲基氢氧化铵。
在一个实施例中,垫层的材料包括锗硅。
在一个实施例中,去除垫层包括:利用氢氧化铵和盐酸的混合液,去除垫层。
在一个实施例中,上述方法还包括:形成第三电介质层以至少包覆所露出的石墨烯层。
在一个实施例中,第三电介质层的材料包括:不导电的、硼的氮化物,或硅的氧化物。
在一个实施例中,还包括:在第三电介质层上形成栅极。
在一个实施例中,其中:凹陷为细长沟槽的形式,其中填充在凹陷中的第二电介质层被形成为鳍片,露出的石墨烯层包覆第二电介质层的鳍片的顶部和至少上部侧壁,石墨烯层和第二电介质层构成鳍片式结构。
在一个实施例中,方法还包括:形成第三电介质层以至少包覆所露出的石墨烯层;以及在第三电介质层上形成栅极。
在一个实施例中,第一电介质层由其上不能选择性地生长石墨烯的电介质材料形成。
根据本发明的又一方面,提供了一种半导体装置,包括:
衬底,衬底之上的鳍片式结构,包覆鳍片式结构顶部和至少上部侧壁的石墨烯层。
在一个实施例中,还包括:在衬底之上的、在各鳍片式结构之间的第一电介质层。
在一个实施例中,石墨烯层在第一电介质层的上方。
在一个实施例中,其中鳍片式结构由第二电介质材料形成。
在一个实施例中,其中鳍片式结构包括由绝缘材料形成的表面层。
在一个实施例中,其中第二电介质材料是硅的氧化物。
在一个实施例中,第一电介质层由其上不能选择性地生长石墨烯的电介质材料形成。
在一个实施例中,第二电介质层的材料包括:不导电的硼的氮化物,或硅的氧化物。
在一个实施例中,衬底层的材料包括硅。
在一个实施例中,还包括:包覆石墨烯层的第三电介质层。
在一个实施例中,第三电介质层的材料包括:不导电的硼的氮化物,或硅的氧化物。
在一个实施例中,还包括:包覆鳍片结构的部分顶部和部分侧壁的栅极。
通过以下参照附图对本发明的示例性实施例的详细描述,本发明的其他特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例,并且连同说明书一起用于解释本发明的原理。
参照附图,根据下面的详细描述,可以更加清楚地理解本发明,其中:
图1为根据本发明一个实施例的半导体装置的制造方法的示意流程图。
图2-图11示意性地示出了根据本发明一个实施例的半导体装置的制造过程若干阶段的剖面示意图。
图12示意性地示出了根据本发明一个实施例的半导体装置的立体示意图。
图13示意性地示出了根据本发明另一个实施例的半导体装置的剖面示意图。
图14示意性地示出了根据本发明另一个实施例的半导体装置的立体示意图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到:除非另外具体说明,否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
同时,应当明白,为了便于描述,附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的,决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论,但在适当情况下,技术、方法和设备应当被视为说明书的一部分。
在这里示出和讨论的所有示例中,任何具体值应被解释为仅仅是示例性的,而不是作为限制。因此,示例性实施例的其它示例可以具有不同的值。
应注意:相似的标号和字母在下面的附图中表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步讨论。
图1为根据本发明一个实施例的半导体装置的制造方法的示意流程图。图2-图11示意性地示出了根据本发明一个实施例的半导体装置的制造过程若干阶段的剖面示意图。图12示意性地示出了根据本发明一个实施例的半导体装置的立体示意图。图13和图14示意性地示出了根据本发明另一个实施例的半导体装置的剖面和立体示意图。下面将结合图1、图2-图12和图13-图14来进行说明本发明的实施例。
如图1所示,在步骤101,形成生长衬底。
首先,提供衬底结构,如图2所示,该衬底结构可以包括牺牲衬底200和在牺牲衬底200上的第一电介质层202。衬底结构中形成有多个凹陷203,凹陷203可以贯穿第一电介质层202,并且凹陷203的底部和部分侧壁可以位于牺牲衬底200中。牺牲衬底200的材料可以包括硅等半导体材料。
在一种实现方式中,第一电介质层202的材料由其上不能选择性地生长石墨烯的电介质材料(避免在之后的选择性生长石墨烯层的步骤中在其上生长石墨烯,见步骤105),例如硅的氧化物等材料形成。
应理解,可以利用本领域中已知的方法、工艺步骤、材料等来形成本发明的衬底结构,因此,在此不再就形成该衬底结构的工艺的细节进行详细说明。
在一种实现方式中,凹陷203为细长沟槽的形式。
回到图1,在步骤103,在凹陷底部和部分侧壁上形成垫层。
在一种实现方式中,如图3所示,可以利用外延生长工艺,在凹陷203的底部和部分侧壁生长垫层204。垫层204的材料可以包括锗硅,也可以包括本领域技术人员了解的其它能够在其上选择性地生长石墨烯的材料。
接着,如图1所示,在步骤105,选择性地在垫层上生长石墨烯层。
在一种实现方式中,可以利用甲烷和氢气,选择性地在垫层204上生长石墨烯层206,如图4所示。也可以利用本领域技术人员了解的其它选择性生长石墨烯的工艺在垫层204上选择性地生长石墨烯层206。
在一种实现方式中,由于第一电介质层202的材料由其上不能选择性地生长石墨烯的电介质材料,因此第一电介质层202的顶部和侧壁没有生长石墨烯层,如图4所示。
接着,如图1所示,在步骤107,在凹陷中填充第二电介质层。
在一种实现方式中,如图5所示,优选地利用原子层沉积(ALD)工艺或物理气相沉积(PVD)工艺在凹陷203中填充第二电介质层207,以避免如化学气相沉积(CVD)等工艺过程那样在石墨烯层206引入氧,进而影响器件性能。第二电介质层207的材料可以包括不导电的硼的氮化物或者硅的氧化物。当第二电介质层207的材料为硅的氧化物时,优选的,利用物理气相沉积工艺沉积第二电介质层207。
在一种实现方式中,可以在步骤107之后,进行平坦化工艺,以使得第二电介质层207的顶部与第一电介质层202的顶部基本齐平。在一个具体实施例中,凹陷203为细长沟槽的形式,从而填充在凹陷203中的第二电介质层207形成为鳍片208,如图6所示。
在另一种实现方式中,在步骤103,形成的垫层204可以覆盖第一电介质层202的顶部。之后,在步骤105,选择性地在垫层204上生长石墨烯层206。接着,在步骤107,沉积第二电介质层207以覆盖石墨烯层206,第二电介质层207还填充凹陷203。然后,进行平坦化工艺,使得第二电介质层207的顶部与第一电介质层202的顶部基本齐平。在该实现方式中,第一电介质层202的侧壁也生长有垫层204和石墨烯层206。
在另一实施例中,在步骤103,形成的垫层204可以覆盖第一电介质层202的顶部,例如,可以通过沉积(例如,原子层沉积(ALD)等)在图2所示结构上形成例如氧化铝层;之后可以利用图案化的掩模去除顶部的部分氧化铝层,从而形成图3所示的结构。之后,在步骤105,选择性地在垫层204上生长石墨烯层206。之后可以进行与前述类似的工序步骤。
回到图1,在步骤109,将生长衬底附接到接合衬底之上。
在一种实现方式中,如图7所示,以第二电介质层207的顶部(即鳍片208的底部)面对接合衬底300,将生长衬底附接到接合衬底300之上。例如,可以采用固溶、压合或键合(例如,通过表面的氢键键合)等,将生长衬底附接到接合衬底300之上。接合衬底300的材料可以包括硅等半导体材料。可选的,接合衬底300的与和生长衬底接合的接合表面相反的表面上还可以形成有电介质层302,如图7所示。
接着,在步骤111,去除牺牲衬底。
在一种实现方式中,通过湿法工艺利用蚀刻剂去除牺牲衬底200,如图8所示。根据待蚀刻的衬底材料的不同,蚀刻剂可以包括,例如,四甲基氢氧化铵(TMAH)或氢氧化铵和盐酸的混合液等。
然后,在步骤113,去除垫层,从而露出石墨烯层。
在一种实现方式中,可以利用氢氧化铵和盐酸的混合液,去除由锗硅(SiGe)形成的垫层204,从而露出石墨烯层206,如图9所示。也可以利用本领域技术人员了解的其它方法,在不破坏石墨烯层206的条件下去除垫层204。
可选的,如图1所示,还可以包括步骤115,形成第三电介质层210。
如图10所示,第三电介质层210至少包覆露出的石墨烯层206。第三电介质层210的材料可以包括不导电的硼的氮化物或硅的氧化物。例如可以利用物理气相沉积工艺,形成第三电介质层210。也可以利用本领域技术人员了解的其它方法,形成第三电介质层210。
可选的,如图1所示,还可以包括步骤117,在第三电介质层上形成栅极。
如图11所示,在第三电介质层210上形成栅极212。应理解,可以利用本领域中已知的方法、工艺步骤、材料等来形成本发明的栅极,因此,在此不再就形成该栅极的工艺的细节进行详细说明。得到的半导体装置的立体示意图如图12所示。
根据上述半导体装置的制造方法另一种实现方式得到的半导体装置的剖面示意图如13所示,第一电介质层202的侧壁也生长有石墨烯层206。该方法得到的半导体装置的立体示意图如图14所示。
本实施例的半导体装置的制造方法,通过在垫层上选择性生长石墨烯层,可以降低图案化石墨烯层的复杂度,避免了采用激光刻蚀或光刻等工艺图案化石墨烯带来的的影响。
将理解,当一元件(诸如,层、区域或者基板)被称为在另一元件上时,其可以是直接在其它元件上或者也可以存在中间元件。此外,这里可以使用相对术语例如“在……下”或“在……上”来描述一层或区域对于另一层或区域的关系。还将理解,这些术语旨在包括除了附图中描述的取向之外还包括装置的不同取向。如这里使用的,术语“和/或”包括相关联的所列项中的一个或多个的任何和全部组合,并且也可以缩写为“/”。
应理解,本公开还教导了一种半导体装置,包括:衬底,所述衬底之上的鳍片式结构,包覆所述鳍片式结构顶部和至少上部侧壁的石墨烯层。
在一种实现方式中,还包括:在所述衬底之上的、在各鳍片式结构之间的第一电介质层。
在一种实现方式中,石墨烯层在第一电介质层的上方。
在一种实现方式中,其中鳍片式结构由第二电介质材料形成。
在一种实现方式中,其中鳍片式结构包括由绝缘材料形成的表面层。
在一种实现方式中,其中第二电介质材料是硅的氧化物。
在一种实现方式中,第一电介质层由其上不能选择性地生长石墨烯的电介质材料形成。
在一种实现方式中,第二电介质层的材料包括:不导电的、硼的氮化物,或硅的氧化物。
在一种实现方式中,衬底层的材料包括硅。
在一种实现方式中,还包括:包覆石墨烯层的第三电介质层。
在一种实现方式中,第三电介质层的材料包括:不导电的、硼的氮化物,或硅的氧化物。
在一种实现方式中,还包括:包覆鳍片结构的部分顶部和部分侧壁的栅极。
至此,已经详细描述了根据本公开实施例的半导体装置及其制造方法。为了避免模糊本公开的教导,没有描述本领域所公知的一些细节,本领域技术人员根据上面的描述,完全可以明白如何实施这里公开的技术方案。另外,本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解,可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本公开的精神和范围。
Claims (30)
1.一种半导体装置的制造方法,其特征在于,包括:
形成生长衬底,所述形成生长衬底包括:
提供衬底结构,所述衬底结构包括牺牲衬底和在所述牺牲衬底上的第一电介质层,所述衬底结构中形成有多个凹陷,所述凹陷贯穿所述第一电介质层,并且所述凹陷的底部和部分侧壁位于所述牺牲衬底中,
在所述凹陷的所述底部和所述部分侧壁上形成垫层,
选择性地在所述垫层上生长石墨烯层,以及
在所述凹陷中填充第二电介质层;
以所述第二电介质层的顶部面对接合衬底的方式,将所述生长衬底附接到接合衬底之上;
去除所述牺牲衬底;
去除所述垫层,从而露出所述石墨烯层。
2.根据权利要求1所述的方法,其特征在于,所述形成生长衬底还包括:
在填充第二电介质层之后,进行平坦化,以使得所述第二电介质层的顶部与所述第一电介质层的顶部基本齐平。
3.根据权利要求1所述的方法,其特征在于,在所述凹陷的所述底部和所述部分侧壁上形成垫层包括:
利用外延生长工艺,在所述凹陷的所述底部和所述部分侧壁生长垫层。
4.一种半导体装置的制造方法,其特征在于,包括:
提供生长衬底,所述生长衬底包括:
牺牲衬底和在所述牺牲衬底上的第一电介质层,所述牺牲衬底中形成有多个凹陷,所述凹陷贯穿所述第一电介质层,并且所述凹陷的底部和部分侧壁位于所述牺牲衬底中,以及
在所述凹陷的所述底部和所述部分侧壁上的垫层;
选择性地在所述垫层上生长石墨烯层;
在所述凹陷中填充第二电介质层;
以所述第二电介质层的顶部面对接合衬底的方式,将所述生长衬底附接到接合衬底之上;
去除所述牺牲衬底;以及
去除所述垫层,从而露出所述石墨烯层。
5.根据权利要求1或4所述的方法,其特征在于,填充第二电介质层包括:
利用原子层沉积工艺或物理气相沉积工艺在所述凹陷中填充所述第二电介质层。
6.根据权利要求1或4所述的方法,其特征在于,所述第二电介质层的材料包括:
不导电的硼的氮化物,或
硅的氧化物。
7.根据权利要求1或4所述的方法,其特征在于,所述生长石墨烯层包括:
利用甲烷和氢气,选择性地在所述垫层上生长石墨烯层。
8.根据权利要求1或4所述的方法,其特征在于,所述牺牲衬底的材料包括硅。
9.根据权利要求1或4所述的方法,其特征在于,其中去除所述牺牲衬底是通过湿法工艺利用蚀刻剂进行的。
10.根据权利要求9所述的方法,其特征在于,所述蚀刻剂包括四甲基氢氧化铵。
11.根据权利要求1或4所述的方法,其特征在于,所述垫层的材料包括锗硅。
12.根据权利要求11所述的方法,其特征在于,去除所述垫层包括:
利用氢氧化铵和盐酸的混合液,去除所述垫层。
13.根据权利要求1或4所述的方法,其特征在于,还包括:
形成第三电介质层以至少包覆所露出的石墨烯层。
14.根据权利要求13所述的方法,其特征在于,所述第三电介质层的材料包括:
不导电的硼的氮化物,或
硅的氧化物。
15.根据权利要求13所述的方法,其特征在于,还包括:
在所述第三电介质层上形成栅极。
16.根据权利要求1或4所述的方法,其特征在于,其中:
所述凹陷为细长沟槽的形式,
其中填充在所述凹陷中的第二电介质层被形成为鳍片,露出的石墨烯层包覆所述第二电介质层的鳍片的顶部和至少上部侧壁,所述石墨烯层和所述第二电介质层构成鳍片式结构。
17.根据权利要求16所述的方法,其特征在于,所述方法还包括:
形成第三电介质层以至少包覆所露出的石墨烯层;以及
在所述第三电介质层上形成栅极。
18.根据权利要求1或4所述的方法,其特征在于,所述第一电介质层由其上不能选择性地生长石墨烯的电介质材料形成。
19.一种半导体装置,其特征在于,包括:
衬底,
所述衬底之上的鳍片式结构,
包覆所述鳍片式结构顶部和至少上部侧壁的石墨烯层。
20.根据权利要求19所述的半导体装置,其特征在于,还包括:
在所述衬底之上的、在各鳍片式结构之间的第一电介质层。
21.根据权利要求20所述的半导体装置,其特征在于,所述石墨烯层在所述第一电介质层的上方。
22.根据权利要求19所述的半导体装置,其特征在于,其中所述鳍片式结构由第二电介质材料形成。
23.根据权利要求19所述的半导体装置,其特征在于,其中所述鳍片式结构包括由绝缘材料形成的表面层。
24.根据权利要求22所述的半导体装置,其特征在于,其中所述第二电介质材料是硅的氧化物。
25.根据权利要求20所述的半导体装置,其特征在于,所述第一电介质层由其上不能选择性地生长石墨烯的电介质材料形成。
26.根据权利要求22所述的半导体装置,其特征在于,所述第二电介质层的材料包括:
不导电的硼的氮化物,或
硅的氧化物。
27.根据权利要求19所述的半导体装置,其特征在于,所述衬底层的材料包括硅。
28.根据权利要求19所述的半导体装置,其特征在于,还包括:
包覆所述石墨烯层的第三电介质层。
29.根据权利要求28所述的半导体装置,其特征在于,所述第三电介质层的材料包括:
不导电的硼的氮化物,或
硅的氧化物。
30.根据权利要求28所述的半导体装置,其特征在于,还包括:
包覆所述鳍片结构的部分顶部和部分侧壁的栅极。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130146846A1 (en) * | 2011-12-13 | 2013-06-13 | International Business Machines Corporation | Graphene field effect transistor |
US20140015015A1 (en) * | 2012-07-10 | 2014-01-16 | Globalfoundries Inc. | Finfet device with a graphene gate electrode and methods of forming same |
CN104616991A (zh) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的形成方法 |
US20160013184A1 (en) * | 2014-07-08 | 2016-01-14 | International Business Machines Corporation | Method and structure to suppress finfet heating |
CN105322018A (zh) * | 2014-06-13 | 2016-02-10 | 台湾积体电路制造股份有限公司 | 薄片式finfet器件 |
CN105575814A (zh) * | 2014-10-17 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管及其形成方法 |
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---|---|---|---|---|
US9972537B2 (en) * | 2016-02-24 | 2018-05-15 | Globalfoundries Inc. | Methods of forming graphene contacts on source/drain regions of FinFET devices |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130146846A1 (en) * | 2011-12-13 | 2013-06-13 | International Business Machines Corporation | Graphene field effect transistor |
US20140015015A1 (en) * | 2012-07-10 | 2014-01-16 | Globalfoundries Inc. | Finfet device with a graphene gate electrode and methods of forming same |
CN104616991A (zh) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管的形成方法 |
CN105322018A (zh) * | 2014-06-13 | 2016-02-10 | 台湾积体电路制造股份有限公司 | 薄片式finfet器件 |
US20160013184A1 (en) * | 2014-07-08 | 2016-01-14 | International Business Machines Corporation | Method and structure to suppress finfet heating |
CN105575814A (zh) * | 2014-10-17 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管及其形成方法 |
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