CN107863331A - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
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- CN107863331A CN107863331A CN201611015952.6A CN201611015952A CN107863331A CN 107863331 A CN107863331 A CN 107863331A CN 201611015952 A CN201611015952 A CN 201611015952A CN 107863331 A CN107863331 A CN 107863331A
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- conducting shell
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 116
- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 111
- 239000011241 protective layer Substances 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 71
- 238000001465 metallisation Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000011368 organic material Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 10
- 239000004020 conductor Substances 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
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- 239000010949 copper Substances 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 5
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- 229910052763 palladium Inorganic materials 0.000 description 5
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- 230000008901 benefit Effects 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
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- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 150000002500 ions Chemical class 0.000 description 1
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- 239000001301 oxygen Substances 0.000 description 1
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- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
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Classifications
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Abstract
本公开提供一种半导体结构及其制造方法,该半导体结构包含一基板,该基板包含一第一表面、与该第一表面对立的一第二表面、以及自该第一表面朝向该第二表面凹陷的一凹部;一传导层,位于该第一表面上方且位于该凹部内;以及一保护层,位于该第一表面上方且局部覆盖该传导层,其中位于该凹部内的该传导层自该保护层暴露。
Description
技术领域
本公开涉及一种包括传导层的半导体结构及其制造方法,该传导层位于一基板上方且位于一凹部内,该凹部凹陷至该基板中。
背景技术
半导体装置对于许多现代应用而言是重要的。随着电子技术的进展,半导体装置的尺寸越来越小,而功能越来越大且整合的电路量越来越多。由于半导体装置的规模微小化,晶圆级晶片规模封装(wafer level chip scale packaging,WLCSP)广泛用于制造。在此等小半导体装置内,实施许多制造步骤。
然而,微型化规模的半导体装置的制造变得越来越复杂。制造半导体装置的复杂度增加可造成缺陷,例如电互连不良、发生破裂、或元件脱层(delamination)。因此,修饰结构与制造半导体装置面临许多挑战。
上文的「现有技术」说明仅是提供背景技术,并未承认上文的「现有技术」说明公开本公开的标的,不构成本公开的现有技术,且上文的「现有技术」的任何说明均不应作为本案的任一部分。
发明内容
本公开的实施例提供一种半导体结构,包括一基板,该基板包含一第一表面、与该第一表面对立的一第二表面、以及自该第一表面朝向该第二表面凹陷的一凹部;一传导层,位于该第一表面上方且位于该凹部内;以及一保护层,位于该第一表面上方且局部覆盖该传导层,其中位于该凹部内的该传导层自该保护层暴露。
在本公开的实施例中,该传导层经配置与该凹部的一侧壁共形。
在本公开的实施例中,自该保护层暴露的该传导层经配置以接收一互连结构,以及该互连结构为一传导凸块、一传导线、或一传导柱。
在本公开的实施例中,该互连结构的至少一部分受到该传导层与该基板环绕。
在本公开的实施例中,该半导体结构另包含一传导结构,该传导结构位于该基板内且电连接至该传导层。
在本公开的实施例中,该传导结构为一金属件或一晶体管。
在本公开的实施例中,该半导体结构另包含一凸块下金属(UBM)层于该凹部内,其中该UBM层经配置以接收一互连结构。
在本公开的实施例中,该基板包含硅、氧化硅、玻璃、陶瓷、或有机材料。
本公开的实施例另提供一种半导体结构,包括一基板,该基板包含一第一表面、与该第一表面对立的一第二表面、以及自该第一表面朝向该第二表面凹陷的一凹部;一传导层,位于该第一表面上方;一保护层,位于该第一表面上方且至少局部覆盖该传导层;一互连结构,位于该凹部内且电连接至该传导层。
在本公开的实施例中,该互连结构的至少一部分受到该基板环绕。
在本公开的实施例中,该半导体结构另包含一凸块下金属(UBM)层于自该保护层暴露的凹部内。
在本公开的实施例中,该UBM层受到该传导层与该基板的环绕。
在本公开的实施例中,该互连结构经由该传导层而电连接至位于该基板内的一传导结构。
本公开的实施例另提供一种半导体结构的制造方法,包含提供一基板;形成一凹部于该基板上方;配置一传导层于该基板上方;配置一保护层于该基板上方以至少局部覆盖该传导层。
在本公开的实施例中,该传导层位于该凹部内或与该凹部的一侧壁共形。
在本公开的实施例中,配置该传导层包含进行电镀或溅镀工艺。
在本公开的实施例中,形成该凹部包含配置一图案化掩模于该基板上方且移除该基板的一部分而。
在本公开的实施例中,形成该凹部包含配置图案化掩模于该保护层上,并且移除该保护层的一部、该传导层的一部分、以及该基板的一部分。
在本公开的实施例中,形成该凹部包含进行光微影与蚀刻工艺。
在本公开的实施例中,该制造方法另包含配置一凸块下金属(UBM)层于自该保护层暴露的该凹部内;或配置一互连结构于该传导层上方以电连接该互连结构与该传导层;或回焊该互连结构;或附接该半导体结构于一第二基板上方;或打线接合该传导层与一第二基板。
上文已相当广泛地概述本公开的技术特征及优点,俾使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本领域技术人员应了解,可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本公开相同的目的。本领域技术人员亦应了解,这类等效建构无法脱离后附的权利要求所界定的本公开的精神和范围。
附图说明
参阅详细说明与权利要求结合考虑附图时,可得以更全面了解本申请案的公开内容,附图中相同的元件符号是指相同的元件。
图1为剖面示意图,例示本公开实施例的半导体结构。
图2为剖面示意图,例示本公开实施例的半导体结构。
图3为剖面示意图,例示本公开实施例的具有互连结构的半导体结构。
图4为剖面示意图,例示本公开实施例的具有互连结构的半导体结构。
图5为剖面示意图,例示本公开实施例的具有UBM层的半导体结构。
图6为剖面示意图,例示本公开实施例的具有UBM层的半导体结构。
图7为剖面示意图,例示本公开实施例的具有打线接合结构的半导体结构。
图8为剖面示意图,例示本公开实施例的具有打线接合结构的半导体结构。
图9为剖面示意图,例示本公开实施例的封装,该封装包含整合基板的半导体结构。
图10为剖面示意图,例示本公开实施例的半导体结构,该半导体结构具有位于基板上方的传导层。
图11为剖面示意图,例示本公开实施例的半导体结构,该半导体结构具有自保护层暴露的传导层的一暴露部分。
图12为剖面示意图,例示本公开实施例的半导体结构,该半导体结构具有位于基板上方的传导层。
图13为流程图,例示本公开实施例的半导体结构的制造方法。
图14至图25为剖面图,例示本公开实施例的通过图13的方法制造半导体结构。
图26为流程图,例示本公开实施例的制造半导体结构的方法。
图27至图31为剖面图,例示本公开实施例的通过图26的方法制造半导体结构。
图32为流程图,例示本公开实施例的制造半导体结构的方法。
图33至图46为剖面图,例示本公开实施例的通过图32的方法制造半导体结构。
其中,附图标记说明如下:
100 半导体结构
101 基板
101a 第一表面
101b 第二表面
101c 凹部
101d 传导结构
103 传导层
104 保护层
105 互连结构
105a 柱体
105b 接线
106 凸块下金属层
107 第二基板
107a 接合垫
108 粘着物
109 第一图案化掩模
110 第二图案化掩模
111 第三图案化掩模
112 第四图案化掩模
113 第五图案化掩模
114 第六图案化掩模
200 半导体结构
300 半导体结构
400 半导体结构
500 半导体结构
600 半导体结构
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图,说明本公开的实施例,然而本公开并不受限于该实施例。此外,以下的实施例可适当整合以下实施例以完成另一实施例。
「一实施例」、「实施例」、「例示实施例」、「其他实施例」、「另一实施例」等是指本公开所描述的实施例可包含特定特征、结构或是特性,然而并非每一实施例必须包含该特定特征、结构或是特性。再者,重复使用「在实施例中」一语并非必须指相同实施例,然而可为相同实施例。
本公开涉及一种半导体结构,该半导体结构包括位于基板上方且位于凹部之内的传导层,该凹部凹陷至基板中。为了使得本公开可被完全理解,以下说明提供详细的步骤与结构。显然,本公开的实施不会限制本领域技术人员已知的特定细节。此外,已知的结构与步骤不再详述,以免不必要地限制本公开。本公开的较佳实施例详述如下。然而,除了详细说明之外,本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容,而是由权利要求定义。
半导体结构经由互连结构,例如凸块(bump)、柱体(pillar)、杆体(post)或类似物而电连接另一晶片或封装。该互连结构位于该半导体结构上方。在配置该互连结构之后,应力或力会作用于该半导体结构上方并且对于该互连结构与互连结构下方的元件造成破坏。因此,互连结构中可能产生破裂或甚至遍及至半导体结构的元件中。可能发生元件的脱层。因此,发生电连接故障。
在本公开中,提供一种半导体结构,该半导体结构包括基板与传导层,该基板具有凹部,以及该传导层为于该基板与该凹部上方。该凹部凹陷至基板中,以及传导层位于该凹部内或与该凹部共形。传导层凹陷至基板中。互连结构位于传导层上方与凹部内,该互连结构例如传导凸块、接线或柱体。互连结构至少局部位于基板内,可降低半导体结构的整体厚度或高度。
再者,凹陷的传导层可接收更大尺寸的互连结构。互连结构可提供弹性,并且可释放制造过程中或是热工艺过程中发生的半导体基板上方的应力。因此,可最小化或是防止半导体结构中的破裂与元件的脱层。可改良半导体结构的可信赖度。
图1为剖面图,例示本公开实施例的半导体结构100。在本公开的实施例中,半导体结构100包含基板101、传导层103以及保护层104。在本公开的实施例中,半导体结构100为晶粒、晶片或半导体封装的一部分。
在本公开的实施例中,基板101为半导体基板。在本公开的实施例中,基板101为晶圆。在本公开的实施例中,基板101包含半导体材料,例如硅、锗、镓、砷、以及其组合。在本公开的实施例中,基板101为硅基板。在本公开的实施例中,基板101包含材料例如陶瓷、玻璃或类似物。在本公开的实施例中,基板101包含有机材料。在本公开的实施例中,基板101为玻璃基板。在本公开的实施例中,基板101为封装基板。在本公开的实施例中,基板101为四边形、矩形、正方形、多边形、或任何其他合适的形状。
在本公开的实施例中,基板101包含第一表面101a以及与第一表面101a对立的第二表面101b。在本公开的实施例中,第一表面101a为正面或是主动面,电路或电子元件位于其上。在本公开的实施例中,第二表面101b为背面或非主动面。
在本公开的实施例中,基板101包含凹部101c凹陷至基板101中。在本公开的实施例中,凹部101c自第一表面101a朝向第二表面101b凹陷。在本公开的实施例中,凹部101c自第二表面101b朝向第一表面101a凹陷。在本公开的实施例中,凹部101c延伸方向垂直于第一表面101a或第二表面101b。
在本公开的实施例中,基板101经制造具有功能性电路于其上。在本公开的实施例中,基板101包含数个传导迹线,以及位于基板101内的数个电子元件。在本公开的实施例中,传导结构101d位于基板内。在本公开的实施例中,传导结构101d为金属件。在本公开的实施例中,传导结构101d包含彼此堆叠且通过通路而电连接的数层。在本公开的实施例中,传导结构101d延伸于第一表面101a与第二表面101b之间。在本公开的实施例中,传导结构101d包含金、银、铜、镍、钨、铝、钯、以及/或其合金。在本公开的实施例中,传导结构101d为晶体管或二极管。在本公开的实施例中,传导结构101d通过传导迹线而电连接。
在本公开的实施例中,传导层103位于第一表面101a上方与凹部101c内。在本公开的实施例中,传导层103沿着第一表面101a与凹部101c配置。在本公开的实施例中,传导层经配置与凹部101c的侧壁共形。在本公开的实施例中,传导层103电连接至传导结构101d。在本公开的实施例中,传导层103耦合传导结构101d的至少一部分。在本公开的实施例中,传导层103包含金、银、铜、镍、钨、铝、钯、以及/或其合金。
在本公开的实施例中,保护层104位于第一表面101a上方,并且局部覆盖传导层103。在本公开的实施例中,保护层104经配置以对于传导层103与基板101提供电性绝缘与湿度保护。在本公开的实施例中,保护层104包含彼此堆叠的一或多层介电材料。在本公开的实施例中,以介电材料形成保护层,例如弹性体、环氧化合物、聚亚酰胺、聚合物、树脂、氧化物、或类似者。
在本公开的实施例中,自保护层104暴露传导层103的至少一暴露部分。在本公开的实施例中,自保护层104暴露位于凹部101c内的传导层103。在本公开的实施例中,自保护层104暴露的传导层103经配置以接收互连结构,例如传导凸块、传导线、传导柱、接合线等。
图2为半导体结构100的剖面图,半导体结构100具有上述或图1所示的类似架构。在本公开的实施例中,如图2所示,凹部101c的侧壁为半球形,以及传导层103经配置与凹部101c的侧壁共形为半球形。
图3与图4为剖面图,例示本公开实施例的半导体结构200。在本公开的实施例中,半导体结构200具有上述或图1或图2所示半导体结构10的类似架构。
在本公开的实施例中,半导体结构200包含互连结构105,该互连结构105位于自保护层104暴露的传导层103上方。在本公开的实施例中,互连结构105位于凹部101c内。在本公开的实施例中,互连结构105与传导层103电连接或耦合。在本公开的实施例中,互连结构105经由传导层103电耦合至传导结构101d。在本公开的实施例中,互连结构105至少局部受到基板101、传导层103与保护层104环绕。在本公开的实施例中,互连结构105至少局部自保护层104突出。
在本公开的实施例中,互连结构105经配置以接合另一传导件、晶片、或封装。在本公开的实施例中,互连结构105为传导凸块、传导柱、传导线、或接合线或类似者。在本公开的实施例中,互连结构105包含传导材料,例如铅、锡、铜、金、银、镍、或其组合。在本公开的实施例中,互连结构105为焊料接合(solder joint)、焊料凸块、焊球、球栅阵列(ball gridarray,BGA)球、受控的塌陷晶片连接(controlled collapse chip connection,C4)凸块、微凸块、或类似者。在本公开的实施例中,互连结构105为圆柱形、球形、或半球形。
图5与图6为剖面图,例示本公开实施例的半导体结构300。在本公开的实施例中,半导体结构300具有上述或图1或图2所示半导体结构100的类似架构或与上述或图3或图4所示半导体结构200的类似架构。
在本公开的实施例中,半导体结构300包含凸块下金属(under bumpmetallization,UBM)层106于传导层103上方。在本公开的实施例中,UBM层106位于凹部101c内。在本公开的实施例中,UBM层106经配置与传导层103共形。在本公开的实施例中,UBM层106受到基板101、传导层103以及保护层104环绕。在本公开的实施例中,UBM层106位于自保护层104暴露的传导层103上方。
在本公开的实施例中,UBM层106经配置以接收互连结构。在本公开的实施例中,UBM层106位于互连结构105与传导层103之间。在本公开的实施例中,互连结构105经由UBM层106与传导层103而电连接至传导结构101d。在本公开的实施例中,UBM层106环绕互连结构105。
在本公开的实施例中,UBM层106包含铬、铜、金、钛、钨、镍、或其他。在本公开的实施例中,UBM层106包含粘着层、阻障层、或可湿性层。在本公开的实施例中,粘着层包含钛、钨、或其他。在本公开的实施例中,阻障层包含镍或其他。在本公开的实施例中,可湿性层包含铜、金或其他。
图7与图8为剖面图,例示本公开实施例的半导体结构400。在本公开的实施例中,半导体结构400具有上述或图1或图2所示半导体结构100的类似架构。
在本公开的实施例中,半导体结构400包含互连结构105,其为打线接合结构。在本公开的实施例中,互连结构105包含柱体105a与接线105b,柱体105a位于传导层103上方,以及接线105b自柱体105a延伸且经配置以接合或电连接传导件或另一互连结构。
图9为剖面图,例示本公开实施例的封装500。在本公开的实施例中,封装500包含半导体结构400,其具有上述或图7或图8所示的类似架构。
在本公开的实施例中,封装500包含第二基板107。在本公开的实施例中,第二基板107为基板或晶圆。在本公开的实施例中,第二基板107为印刷电路板(PCB)。在本公开的实施例中,第二基板107包含接合垫107a,该接合垫107a位于第二基板107上方并且经配置以接收传导件或互连结构。
在本公开的实施例中,半导体结构400位于第二基板107上方。在本公开的实施例中,半导体结构400通过粘着物而附接至第二基板107,该粘着物例如晶粒附接膜(dieattach film,DAF)。在本公开的实施例中,柱体105a与接合垫107a接合,因而基板101经由传导层103、柱体105a、接线105b与接合垫107a而电连接至第二基板107。
图10至图12为剖面图,例示本公开实施例的半导体结构600。在本公开的实施例中,半导体结构600具有上述或图5或图6所示半导体结构300的类似架构。
在本公开的实施例中,传导层103非位于凹部101c内。在本公开的实施例中,传导层103仅位于第一表面101a上方。在本公开的实施例中,传导层103的一部分自保护层104暴露。在本公开的实施例中,传导层103的侧部自保护层104暴露。
在本公开的实施例中,UBM层106位于凹部101c内,并且位于自保护层104暴露的传导层103上方。在本公开的实施例中,UBM层106经配置与凹部101c共形,并且耦合传导层103的至少一部分,因而UBM层106电连接至传导层103。在本公开的实施例中,UBM层106经由传导层103而电连接至传导结构101d。在本公开的实施例中,UBM层106受到传导层103与基板101环绕。
在本公开的实施例中,互连结构105位于凹部101c内,并且受到UBM层106环绕。在本公开的实施例中,互连结构105经由传导层103与UBM层106而电连接至传导结构101d。
在本公开中,亦提供一种半导体结构的制造方法。在本公开的实施例中,半导体可由图13的方法700形成。方法700包含一些操作,并且描述与说明不视为操作顺序的限制。方法700包含一些步骤(701、702、703与704)。
在步骤701中,提供或接收基板101,如图14所示。在本公开的实施例中,基板101为半导体基板。在本公开的实施例中,基板101为晶圆。在本公开的实施例中,基板101包含半导体材料,例如硅、锗、镓、砷、以及其组合。在本公开的实施例中,基板101为硅基板。
在本公开的实施例中,基板101包含第一表面101a以及与第一表面101a对立的第二表面101b。在本公开的实施例中,第一表面101a为正面或是主动面,电路或电子元件位于其上。在本公开的实施例中,第二表面101b为背面或非主动面。
在本公开的实施例中,基板101经制造具有功能性电路于其上。在本公开的实施例中,基板101包含数个传导迹线,以及位于基板101内的数个电子元件。在本公开的实施例中,传导结构101d位于基板内。在本公开的实施例中,通过移除基板101的一些部分并且配置传导材料,而形成传导结构101d。在本公开的实施例中,通过光微影、蚀刻、或任何其他合适的工艺,移除基板101的该等部分。在本公开的实施例中,通过溅镀、电镀、或任何其他合适的工艺,配置传导材料。在本公开的实施例中,传导结构101d为金属件。在本公开的实施例中,传导结构101d包含彼此堆叠且通过通路而电连接的数层。在本公开的实施例中,传导结构101d延伸于第一表面101a与第二表面101b之间。在本公开的实施例中,传导结构101d包含金、银、铜、镍、钨、铝、钯、以及/或其合金。在本公开的实施例中,传导结构101d为晶体管或二极管。在本公开的实施例中,传导结构101d通过传导迹线而电连接。在本公开的实施例中,传导结构101d具有上述或第1至12图所示的类似架构。
在步骤702中,形成凹部101c,如第15至17图所示。在本公开的实施例中,通过移除基板101的一部分,形成凹部101c。在本公开的实施例中,通过微影、蚀刻或任何其他合适的工艺,形成凹部101c。在本公开的实施例中,通过配置第一图案化掩模109于基板101上方,如图15所示,移除自第一图案化掩模109暴露的基板101的该部分,如图16所示,而后移除第一图案化掩模109,如图17所示,而形成凹部101c。在本公开的实施例中,通过配置光致抗蚀剂(photoresist,PR)于基板101上方,而后移除对应于基板101待移除的一部分的该PR的一部分,而形成第一图案化掩模109。在本公开的实施例中,第一图案化掩模109位于第一表面101a上方。在本公开的实施例中,在形成凹部101c之后,通过蚀刻、剥除或任何其他合适的工艺,移除第一图案化掩模109。
在本公开的实施例中,凹部101c自第一表面101a凹陷至第二表面101b。在本公开的实施例中,凹部101c延伸方向垂直于第一表面101a或第二表面101b。在本公开的实施例中,凹部101c具有上述或第1至12图任一者所示的类似架构。
在步骤703中,传导层103位于基板101上方,如图18所示。在本公开的实施例中,传导层103位于第一表面101a上方且位于凹部101c内。在本公开的实施例中,传导层103经配置与凹部101c的侧壁共形。在本公开的实施例中,通过电镀、溅镀或任何其他合适的操作,配置传导层103。在本公开的实施例中,传导层103包含金、银、铜、镍、钨、铝、钯、以及/或其合金。在本公开的实施例中,传导层103电连接至传导结构101d。在本公开的实施例中,传导层103耦合传导结构101d的至少一部分。
在本公开的实施例中,位于第一表面101a上方的传导层103的一些部分被移除。如图19至图21所示。在本公开的实施例中,第二图案化掩模110位于传导层103上方,如图19所示,以及自第二图案化掩模110暴露的传导层103的一些暴露部分被移除,如图20所示,而后第二图案化掩模110被移除,如图21所示。在本公开的实施例中,通过配置光致抗蚀剂(PR)于传导层103上方,而后移除对应于待移除的传导层103的该部分的该PR的一部分,而形成第二图案化掩模110。在本公开的实施例中,在形成传导层103之后,通过蚀刻、剥除或任何其他合适的工艺,移除第二图案化掩模110。在本公开的实施例中,传导层103具有上述或图1至图9任一者所示的类似架构。
在步骤704中,保护层104位于基板101与传导层103上方,如图22所示。在本公开的实施例中,保护层104至少局部覆盖传导层103,因而位于凹部101c内的传导层103自保护层104暴露。在本公开的实施例中,通过化学气相沉积(chemical vapor deposition,CVD)、等离子体辅助气相沉积(plasma-enhanced chemical vapor deposition,PECVD)、旋涂、或任何其他合适的工艺,配置保护层104。在本公开的实施例中,保护层104包含彼此堆叠的一或多层介电材料。在本公开的实施例中,保护层由介电材料形成,例如弹性体、环氧化合物、聚亚酰胺、聚合物、树脂、氧化物、或类似者。
在本公开的实施例中,保护层104具有上述或图1至图12任一者所示的类似架构。在本公开的实施例中,形成半导体结构100。在本公开的实施例中,半导体结构100具有上述或图1或图2所示的类似架构。
在本公开的实施例中,在配置保护层104之后,配置互连结构105,如图23与图24所示。在本公开的实施例中,互连结构105位于凹部101c内,并且受到传导层103与保护层104环绕。在本公开的实施例中,互连结构105位于传导层103上方并且电连接至传导层103。
如图23所示,在本公开的实施例中,通过配置传导材料于自保护层104暴露的传导层103上方,而后回焊该传导材料,形成互连结构105。在本公开的实施例中,互连结构105为传导凸块。在本公开的实施例中,通过模板粘合(stencil pasting)、植球、回焊、硬化、或任何其他合适的工艺,形成互连结构105。在本公开的实施例中,形成半导体结构200。在本公开的实施例中,半导体结构具有上述或图3或图4所示的类似架构。
在本公开的实施例中,包含柱体105a与接线105b的互连结构105位于传导层103上方,如图24所示。在本公开的实施例中,互连结构105为打线接合结构。在本公开的实施例中,柱体105a位于传导层103上方,且位于凹部101c内,以及接线105b自凹部101c外的柱体105a延伸。在本公开的实施例中,通过打线接合工艺,形成互连结构105。在本公开的实施例中,形成互连结构400。在本公开的实施例中,半导体结构400具有上述或图7至图9任一者所示的类似架构。
在本公开的实施例中,半导体结构400位于第二基板107上方,并且电连接至第二基板107,如图25所示。在本公开的实施例中,半导体结构400通过粘着物108而附接至第二基板107。在本公开的实施例中,接线105b接合第二基板107的接合垫107a。在本公开的实施例中,传导层103通过接合工艺而电连接至第二基板107。在本公开的实施例中,形成封装500,其具有上述或图9所示的类似架构。
在本公开中,一提供一种半导体结构的制造方法。在本公开的实施例中,可通过图26的方法800形成半导体结构。方法800包含一些操作,并且描述与说明不视为操作顺序的限制。方法800包含一些步骤(801、802、803、804、805与806)。
在步骤801中,提供或接收基板101,其类似于步骤701。在步骤802中形成凹部101c,其类似于步骤702。在步骤803中,配置传导层103,其类似于步骤703。在步骤804中,配置保护层104,其类似于步骤704。
在步骤805中,配置UBM层106,如图27所示。在本公开的实施例中,UBM层106位于保护层104与自保护层104暴露的传导层103上方。在本公开的实施例中,UBM层106经配置与传导层103共形。在本公开的实施例中,通过进行溅镀、电镀、或任何其他合适的工艺,配置UBM层106。
在步骤806中,互连结构105位于UBM层106上方,如图28至图31所示。在本公开的实施例中,通过配置第三图案化掩模111于UBM层上方,如图28所示,配置传导材料于自第三图案化掩模111暴露的传导层103上方,如图29所示,而后移除第三图案化掩模111,如图30所示,而配置互连结构105。在本公开的实施例中,通过模板粘合(stencil pasting)、植球、回焊、硬化、或任何其他合适的工艺,形成互连结构105。在本公开的实施例中,互连结构105受到UBM层106、传导层103以及基板101环绕。在本公开的实施例中,互连结构105至少局部位于凹部101c内。在本公开的实施例中,互连结构105具有上述或图5或图6所示的类似架构。
在本公开的实施例中,在互连结构105形成之后,位于保护层104上方的UBM层106的一部分被移除,如图31所示。在本公开的实施例中,通过蚀刻或任何其他合适的工艺,移除位于保护层104上方的UBM层106的该部分。在本公开的实施例中,形成半导体结构300,其具有上述或图5或图6所示的类似架构。
在本公开中,亦提供半导体结构的制造方法。在本公开的实施例中,可通过图32的方法900,形成半导体结构。方法900包含一些操作,并且描述与说明不视为操作顺序的限制。方法900包含一些步骤(901、902、903、904、905与906)。
在步骤901中,提供或接收基板,如图33所示,其类似于步骤701或801。
在步骤902中,传导层103位于基板101上方,如图34所示。在本公开的实施例中,传导层103位于第一表面101a上方。在本公开的实施例中,通过电镀、溅镀或任何其他合适的操作,配置传导层103。在本公开的实施例中,传导层103包含金、银、铜、镍、钨、铝、钯、以及/或其合金。在本公开的实施例中,传导层103电连接至传导结构101d。在本公开的实施例中,传导层103耦合传导结构101d的至少一部分。
在本公开的实施例中,传导层103的一些部分被移除,如图35至图37所示。在本公开的实施例中,第四图案化掩模112位于传导层103上方,如图35所示,以及自第四图案化掩模112暴露的传导层103的一些暴露部分被移除,如图36所示,而后第四图案化掩模112被移除,如图37所示。
在本公开的实施例中,通过配置光致抗蚀剂(PR)于传导层103上方,而后移除对应于待移除的传导层103的该部分的该PR的一部分,形成第四图案化掩模112。在本公开的实施例中,在形成传导层103之后,通过蚀刻、剥除、或任何其他合适的工艺,移除第四图案化掩模112。
在步骤903中,配置保护层104,如图38所示。在本公开的实施例中,保护层104位于第一表面101a与传导层103上方。在本公开的实施例中,通过CVD、PECVD、旋涂、或任何其他合适的工艺,配置保护层104。
在步骤904中,形成凹部101c,如图39至图41所示。在本公开的实施例中,通过配置第五图案化掩模113于保护层104上方,如图39所示,移除自第五图案化掩模113暴露的保护层104的暴露部分、传导层103的一部分以及基板101的一部分,如图40所示,而后移除第五图案化掩模113,如图41所示,形成凹部101c。在本公开的实施例中,通过光微影、蚀刻与任何其他合适的工艺,形成凹部101c。在本公开的实施例中,通过配置光致抗蚀剂(PR)于保护层104上方,而后移除对应于待移除的保护层104的该部分的该PR的一部分,而形成第五图案化掩模113。在本公开的实施例中,在凹部101c形成之后,通过蚀刻、剥除、或任何其他合适的工艺,移除第五图案化掩模113。
在本公开的实施例中,凹部101c自第一表面101a朝向第二表面101b凹陷。在本公开的实施例中,凹部101c延伸方向垂直于第一表面101a或第二表面101b。在本公开的实施例中,凹部101c具有上述或图10至图12任一者所示的类似架构。
在步骤905中,配置UBM层106,如图42所示。在本公开的实施例中,UBM层106位于保护层104上方并且位于凹部101c内。在本公开的实施例中,UBM层106的至少一部分耦合自保护层104暴露的传导层103。在本公开的实施例中,通过溅镀、电镀、或任何其他合适的工艺,配置UBM层106。
在步骤906中,配置互连结构105,如图43至图46所示。在本公开的实施例中,藉一配置第六图案化掩模114于UBM层106上方,如图43所示,配置传导材料于自第六图案化掩模114暴露的传导层103上方,如图44所示,而后移除第六图案化掩模,如图45所示,而配置互连结构105。在本公开的实施例中,通过模板粘合(stencil pasting)、植球、回焊、硬化、或任何其他合适的工艺,形成互连结构105。在本公开的实施例中,互连结构105受到UBM层106、传导层103以及基板101环绕。在本公开的实施例中,互连结构105至少局部位于凹部101c内。在本公开的实施例中,互连结构105具有上述或图10至图12所示的类似架构。
在本公开的实施例中,在形成互连结构105之后,位于保护层104上方的UBM层106的一部分被移除,如图46所示。在本公开的实施例中,通过蚀刻或任何其他合适的工艺,移除位于保护层104上方的UBM层106的该部分。在本公开的实施例中,互连结构105经由传导层103与UBM层106而电连接至传导结构101d。在本公开的实施例中,形成半导体结构600,其具有上述或图10或图11所示的类似架构。
虽然已详述本公开及其优点,然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的精神与范围。例如,可用不同的方法实施上述的许多工艺,并且以其他工艺或其组合替代上述的许多工艺。
再者,本申请案的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。本领域技术人员可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此,此等工艺、机械、制造、物质组成物、手段、方法、或步骤包含于本申请案的权利要求内。
Claims (20)
1.一种半导体结构,包括:
一基板,包含一第一表面、与该第一表面对立的一第二表面、以及自该第一表面朝向该第二表面凹陷的一凹部;
一传导层,位于该第一表面上方且位于该凹部内;以及
一保护层,位于该第一表面上方,并且局部覆盖该传导层,
其中位于该凹部内的该传导层自该保护层暴露。
2.如权利要求1所述的半导体结构,其中该传导层经配置与该凹部的一侧壁共形。
3.如权利要求1所述的半导体结构,其中自该保护层暴露的该传导层经配置以接收一互连结构,以及该互连结构为一传导凸块、一传导线、或一传导柱。
4.如权利要求3所述的半导体结构,其中该互连结构的至少一部分受到该传导层与该基板的环绕。
5.如权利要求1所述的半导体结构,还包括一传导结构,该传导结构位于该基板内并且电连接至该传导层。
6.如权利要求5所述的半导体结构,其中该传导结构为一金属件或一晶体管。
7.如权利要求1所述的半导体结构,还包括一凸块下金属(UBM)层,其中该UBM层位于该凹部内并且经配置以接收一互连结构。
8.如权利要求1所述的半导体结构,其中该基板包含硅、氧化硅、玻璃、陶瓷、或有机材料。
9.一种半导体结构,包括:
一基板,包含一第一表面、与该第一表面对立的一第二表面、以及自该第一表面朝向该第二表面凹陷的一凹部;
一传导层,位于该第一表面上方;
一保护层,位于该第一表面上方,并且至少局部覆盖该传导层;以及
一互连结构,位于该凹部内并且电连接至该传导层。
10.如权利要求9所述的半导体结构,其中该互连结构的至少一部分受到该基板环绕。
11.如权利要求9所述的半导体结构,还包括一凸块下金属(UBM)层,该UBM层位于自该保护层暴露的该凹部内。
12.如权利要求11所述的半导体结构,其中该UBM层受到该传导层与该基板环绕。
13.如权利要求9所述的半导体结构,其中该互连结构经由该传导层而电连接至位于该基板内的一传导结构。
14.一种半导体结构的制造方法,包括:
提供一基板;
形成一凹部于该基板内;
配置一传导层于该基板上方;以及
配置一保护层于该基板上方以至少局部覆盖该传导层。
15.如权利要求14所述的制造方法,其中该传导层形成于该凹部内或是与该凹部的一侧壁共形。
16.如权利要求14所述的制造方法,其中配置该传导层包含进行电镀或溅镀工艺。
17.如权利要求14所述的制造方法,其中形成该凹部包含配置一图案化掩模于该基板上方并且移除该基板的一部分。
18.如权利要求14所述的制造方法,其中形成该凹部包含配置一图案化掩模于该保护层上方,并且移除该保护层的一部分、该传导层的一部分、以及该基板的一部分。
19.如权利要求14所述的制造方法,其中形成该凹部包含进行光微影与蚀刻工艺。
20.如权利要求14所述的制造方法,还包括:
配置一凸块下金属(UBM)层于自该保护层暴露的该凹部内;或
配置一互连结构于该传导层上方,以电连接该互连结构与该传导层;或
回焊该互连结构;或
附接该半导体结构于一第二基板上方;或
打线接合该传导层与一第二基板。
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US7772115B2 (en) * | 2005-09-01 | 2010-08-10 | Micron Technology, Inc. | Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure |
KR101028051B1 (ko) * | 2009-01-28 | 2011-04-08 | 삼성전기주식회사 | 웨이퍼 레벨 패키지 및 그 제조방법 |
US9620469B2 (en) * | 2013-11-18 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming post-passivation interconnect structure |
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US5289038A (en) * | 1991-10-30 | 1994-02-22 | Fuji Electric Co., Ltd. | Bump electrode structure and semiconductor chip having the same |
US20040245630A1 (en) * | 2003-06-09 | 2004-12-09 | Min-Lung Huang | [chip structure] |
US20130134573A1 (en) * | 2007-09-28 | 2013-05-30 | Thorsten Meyer | Semiconductor device and methods of manufacturing semiconductor devices |
FR2969381A1 (fr) * | 2010-12-21 | 2012-06-22 | St Microelectronics Crolles 2 | Puce electronique comportant des piliers de connexion, et procede de fabrication |
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