CN107564851A - 双镶嵌填充 - Google Patents
双镶嵌填充 Download PDFInfo
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- CN107564851A CN107564851A CN201710512993.4A CN201710512993A CN107564851A CN 107564851 A CN107564851 A CN 107564851A CN 201710512993 A CN201710512993 A CN 201710512993A CN 107564851 A CN107564851 A CN 107564851A
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- 230000009977 dual effect Effects 0.000 title abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 120
- 229910052751 metal Inorganic materials 0.000 claims abstract description 117
- 239000010949 copper Substances 0.000 claims abstract description 104
- 230000008021 deposition Effects 0.000 claims abstract description 104
- 229910001092 metal group alloy Inorganic materials 0.000 claims abstract description 98
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 87
- 229910052802 copper Inorganic materials 0.000 claims abstract description 87
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000000565 sealant Substances 0.000 claims abstract description 28
- 239000000945 filler Substances 0.000 claims abstract description 27
- 238000011049 filling Methods 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims description 108
- 229910017052 cobalt Inorganic materials 0.000 claims description 26
- 239000010941 cobalt Substances 0.000 claims description 26
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 26
- 238000004140 cleaning Methods 0.000 claims description 22
- 229910052707 ruthenium Inorganic materials 0.000 claims description 21
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 17
- 238000005229 chemical vapour deposition Methods 0.000 claims description 15
- 229910045601 alloy Inorganic materials 0.000 claims description 13
- 239000000956 alloy Substances 0.000 claims description 13
- 229910052721 tungsten Inorganic materials 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 11
- 229910052741 iridium Inorganic materials 0.000 claims description 11
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 11
- 229910052750 molybdenum Inorganic materials 0.000 claims description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 11
- 229910052702 rhenium Inorganic materials 0.000 claims description 11
- 239000003344 environmental pollutant Substances 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 231100000719 pollutant Toxicity 0.000 claims description 9
- 229910001080 W alloy Inorganic materials 0.000 claims description 8
- 239000002253 acid Substances 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 238000004070 electrodeposition Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 71
- 238000007747 plating Methods 0.000 description 13
- 238000007772 electroless plating Methods 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- 229910052796 boron Inorganic materials 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 230000005611 electricity Effects 0.000 description 6
- 230000009257 reactivity Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 230000003197 catalytic effect Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000002105 nanoparticle Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000003638 chemical reducing agent Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229910021645 metal ion Inorganic materials 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000008139 complexing agent Substances 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910020674 Co—B Inorganic materials 0.000 description 1
- 229910016978 MnOx Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000011149 active material Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 238000003287 bathing Methods 0.000 description 1
- RJTANRZEWTUVMA-UHFFFAOYSA-N boron;n-methylmethanamine Chemical compound [B].CNC RJTANRZEWTUVMA-UHFFFAOYSA-N 0.000 description 1
- BVKZGUZCCUSVTD-UHFFFAOYSA-N carbonic acid Chemical compound OC(O)=O BVKZGUZCCUSVTD-UHFFFAOYSA-N 0.000 description 1
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000412 dendrimer Substances 0.000 description 1
- 229920000736 dendritic polymer Polymers 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000469 dry deposition Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002905 metal composite material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000813 microcontact printing Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000005554 pickling Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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Abstract
本发明涉及双镶嵌填充。提供了一种用于用金属或金属合金填充电介质层中形成的通孔的方法,所述金属或金属合金对含铜互连件上的铜具有低溶解度,其中所述通孔是具有沟槽和通孔的双镶嵌结构的一部分。直接在通孔的底部的含铜互连件上选择性沉积对铜具有低溶解度的第一金属或金属合金的密封层,其中形成通孔的电介质层的侧壁暴露于沉积密封层,并且其中具有低溶解度的第一金属或金属合金被选择性沉积以仅在含铜互连件上形成层。在密封层上无电沉积对铜具有低溶解度的第二金属或金属合金的通孔填充物,从而填充通孔。
Description
技术领域
本发明涉及在半导体晶片上形成半导体器件的方法。更具体地,本发明涉及形成具有通孔和沟槽的金属特征。
背景技术
在形成半导体器件中,在金属互连件上的电介质层中形成导电金属特征。导电金属触点可以由通孔和沟槽的双镶嵌特征形成。
发明内容
为了实现上述并根据本公开的目的,提供了一种用金属或金属合金填充电介质层中形成的通孔的方法,所述金属或金属合金对含铜互连件上的铜具有低溶解度,其中所述通孔是具有沟槽和通孔的双镶嵌结构的一部分。直接在所述通孔底部的所述含铜互连件上选择性地沉积对铜具有低溶解度的第一金属或金属合金的密封层,其中形成所述通孔的电介质层的侧壁暴露于所述沉积第一金属或金属合金,并且其中选择性沉积具有低溶解度的所述第一金属或金属合金,以仅在所述含铜互连件上形成密封层。在所述密封层上无电沉积对铜具有低溶解度的第二金属或金属合金的通孔填充物,从而填充所述通孔。
在另一个表现方式中,提供了一种用金属或金属合金填充在电介质层中形成的通孔的方法,所述金属或金属合金对含铜互连件上的铜具有低溶解度,其中所述通孔是具有沟槽和通孔的双镶嵌结构的一部分。在所述含铜互连件上无电沉积对铜具有低溶解度的第一金属或金属合金的层,以在所述含铜互连件上形成层。漂洗并干燥所述无电沉积的层。在所述层上无电沉积对铜具有低溶解度的第二金属或金属合金通孔填充物,从而填充所述通孔。所述通孔填充包括:执行对铜具有低溶解度的所述第二金属或金属合金的无电沉积,其中所述通孔填充物的所述无电沉积使用比用于无电沉积所述层的无电沉积浴更具反应性的无电沉积浴。可以提供酸清洗以去除金属污染物。
在另一种表现方式中,提供了一种用金属或金属合金填充在电介质层中形成的通孔的方法,所述金属或金属合金对含铜互连件上的铜具有低溶解度,其中所述通孔是具有沟槽和通孔的双镶嵌结构的一部分。在所述含铜互连件上沉积对铜具有低溶解度的化学气相沉积(CVD)的第一金属或金属合金的层。在所述层上无电沉积对铜具有低溶解度的第二金属或金属合金通孔填充物,从而填充所述通孔。所述通孔填充包括:执行对铜具有低溶解度的所述第二金属或金属合金的无电沉积;以及可选地提供酸清洗以去除金属污染物。
具体而言,本发明的一些方面可以阐述如下:
1.一种用金属或金属合金填充电介质层中形成的通孔的方法,所述金属或金属合金对含铜互连件上的铜具有低溶解度,其中所述通孔是具有沟槽和通孔的互连结构的一部分,所述方法包括:
直接在所述通孔底部的所述含铜互连件上选择性地沉积对铜具有低溶解度的第一金属或金属合金的密封层,其中形成所述通孔的电介质层的侧壁暴露于所述沉积所述第一金属或金属合金,并且其中选择性沉积具有低溶解度的所述第一金属或金属合金,以仅在所述含铜互连件上形成层;以及
在所述密封层上无电沉积对铜具有低溶解度的第二金属或金属合金的通孔填充物,从而填充所述通孔。
2.根据条款1所述的方法,其中所述无电沉积所述通孔填充物包括:
提供清洗;
执行对铜具有低溶解度的所述第二金属或金属合金的无电沉积;以及
提供酸清洗以去除金属污染物。
3.根据条款2所述的方法,其中所述选择性沉积所述密封层包括化学气相沉积(CVD)对铜具有低溶解度的所述第一金属或金属合金。
4.根据条款3所述的方法,其中对铜具有低溶解度的所述第一金属或金属合金是钴、钌或铱中的一种或多种或其与其它元素的合金,所述其它元素例如但不限于W、Mo、Re、P和B。
5.根据条款4所述的方法,其还包括:
在所述通孔填充物和邻近所述通孔的沟槽上方形成阻挡层;以及
用包含铜、钴、钌、镍或钨中的至少一种的导电金属或金属合金填充所述沟槽。
6.根据条款2所述的方法,其中所述选择性沉积所述密封层包括:
提供预沉积清洗;
在所述含铜互连件上无电沉积对铜具有低溶解度的所述第一金属或金属合金的层,以在所述含铜互连件上形成层,其中所述通孔填充物的所述无电沉积使用比用于无电沉积所述密封层的无电沉积浴更具反应性的无电沉积浴;
提供后沉积清洗;以及
漂洗并干燥所述无电沉积的层。
7.根据条款6所述的方法,其中对铜具有低溶解度的所述第一金属或金属合金是钴、钌或铱中的一种或多种或其与其它元素的合金,所述其它元素例如但不限于W、Mo、Re、P和B.
8.根据条款7所述的方法,其还包括:
在所述通孔填充物和邻近所述通孔的沟槽上方形成阻挡层;以及
用包含铜、钴、钌、镍或钨中的至少一种的导电金属或金属合金填充所述沟槽。
9.根据条款2所述的方法,其中所述沉积所述密封层包括:在所述含铜互连件上无电沉积对铜具有低溶解度的所述第一金属或金属合金的层,以在所述含铜互连件上形成层,其中所述通孔填充物的所述无电沉积使用与用于无电沉积所述层的无电沉积浴相比对铜更具反应性的无电沉积浴;以及
漂洗并干燥所述无电沉积的层。
10.根据条款9所述的方法,其中对铜具有低溶解度的所述第一金属或金属合金是钴、钌或铱中的一种或多种或其与其它元素的合金,所述其它元素例如但不限于W、Mo、Re、P和B。
11.根据条款10所述的方法,其还包括:
在所述通孔填充物和邻近所述通孔的沟槽上方形成阻挡层;以及
用包含铜、钴、钌、镍或钨中的至少一种的导电金属或金属合金填充所述沟槽。
12.根据条款1所述的方法,其中对铜具有低溶解度的所述第一金属或金属合金是钴、钌或铱中的一种或多种或其与其它元素的合金,所述其它元素例如但不限于W、Mo、Re、P和B。
13.根据条款1所述的方法,其还包括:
在所述通孔填充物和邻近所述通孔的沟槽上方形成阻挡层;以及
用包含铜、钴、钌、镍或钨中的至少一种的导电金属或金属合金填充所述沟槽。
14.根据条款1所述的方法,其中所述密封层的厚度介于之间。
15.一种用金属或金属合金填充在电介质层中形成的通孔的方法,所述金属或金属合金对含铜互连件上的铜具有低溶解度,其中所述通孔是具有沟槽和通孔的互连结构的一部分,所述方法包括:
在所述含铜互连件上无电沉积对铜具有低溶解度的第一金属或金属合金的层,以在所述含铜互连件上形成层;
干燥所述无电沉积的层;以及
在所述层上无电沉积对铜具有低溶解度的第二金属或金属合金的通孔填充物,从而填充所述通孔;其包括:
执行对铜具有低溶解度的所述第二金属或金属合金的无电沉积,其中所述通孔填充物的所述无电沉积使用比用于无电沉积所述层的无电沉积浴更具反应性的无电沉积浴;以及
提供酸清洗以去除金属污染物。
16.根据条款15所述的方法,其中对铜具有低溶解度的所述第一金属或金属合金是钴、钌或铱中的一种或多种或其与其它元素的合金,所述其它元素例如但不限于W、Mo、Re、P和B。
17.根据条款16所述的方法,其还包括:
在所述通孔填充物和邻近所述通孔的沟槽上方形成阻挡层;以及
用包含铜、钴、钌、镍或钨中的至少一种的导电金属或金属合金填充所述沟槽。
18.一种用金属或金属合金填充在电介质层中形成的通孔的方法,所述金属或金属合金对含铜互连件上的铜具有低溶解度,其中所述通孔是具有沟槽和通孔的互连结构的一部分,所述方法包括:
通过化学气相沉积(CVD)在所述含铜互连件上沉积对铜具有低溶解度的第一金属或金属合金的层;以及
在所述层上无电沉积对铜具有低溶解度的第二金属或金属合金的通孔填充物,从而填充所述通孔;其包括:
执行对铜具有低溶解度的所述第二金属或金属合金的无电沉积;以及
提供酸清洗以去除金属污染物。
19.根据条款18所述的方法,其中对铜具有低溶解度的所述第一金属或金属合金是钴、钌或铱中的一种或多种或其与其它元素的合金,所述其它元素例如但不限于W、Mo、Re、P和B。
20.根据条款19所述的方法,其还包括:
在所述通孔填充物和邻近所述通孔的沟槽上方形成阻挡层;以及
用包含铜、钴、钌、镍或钨中的至少一种的导电金属或金属合金填充所述沟槽。
下面将在本发明的详细描述中并结合以下附图对本发明的这些和其它特征进行更详细的描述。
附图说明
在附图的图中以示例而非限制的方式示出了本发明,并且附图中相同的附图标记表示相似的元件,并且其中:
图1是本发明的实施方式的流程图。
图2A-F是使用本发明的工艺的结构的形成的示意图。
具体实施方式
现在将参照附图中所示的几个优选实施方式来详细描述本发明。在下面的描述中,阐述了许多具体细节以便提供对本发明的透彻理解。然而,对于本领域技术人员显而易见的是,可以在没有这些具体细节中的一些或全部的情况下实践本发明。在其他情况下,未详细描述公知的工艺步骤和/或结构,以免不必要地模糊本发明。例如,本发明不限于如何形成通孔和沟槽。在描述中,大多数双镶嵌情况被突出说明,但是本发明可以应用于在单镶嵌工艺中形成的通孔。
在半导体器件的形成中,在电介质层中形成特征。特征可以是通孔和沟槽的形式。通孔可以穿过电介质层到达下面的互连件。沟槽仅部分地穿过电介质层并且在特征之间在相同金属水平提供导电连接,而通孔在沟槽之间在不同金属水平提供连接。
在许多应用中,在衬底上执行选择性无电沉积(electroless deposition),从电化学角度而言,所述衬底比沉积在衬底上的金属是较惰性的(noble)。这些衬底通常在无电沉积之前被需要去除的金属氧化物膜覆盖。在去除氧化物时或通常在清洗处理中,来自衬底的金属离子进入沉积溶液或吸附在晶片表面的其它非金属部分上。释放到沉积溶液中的这些金属离子可能导致在镀液(plating solution)中形成纳米颗粒,这导致半导体衬底上的颗粒形成增加,从而增加缺陷率并降低电产量。当需要使用高反应性沉积化学物质来在表面上镀覆最孤立的特征时,这尤其是问题。
在具体情况下,在具有暴露的Cu的混合表面上的无电Co沉积通常导致选择性损失。这是由于在Cu的清洗处理中,Cu(I)和Cu(II)两种Cu离子都被释放到溶液中。在漂洗清洁化学物质时这些离子可能保留在晶片表面上,并进入沉积溶液,这是在镀覆工艺中的清洗后的后续步骤。Cu离子会与镀液经过几次反应。Cu离子可以与还原剂相互作用并在镀液中形成Cu纳米颗粒,或者在Cu(I)离子的情况下,它们可能不成比例并形成Cu纳米颗粒。这些Cu纳米颗粒对Co镀覆具有催化活性。根据表面类型,这些Co涂覆的Cu颗粒将粘附到表面,在表面上产生Co瘤状物(nodule),如果颗粒粘附到非催化表面(例如晶片的电介质部分)上,这也称为选择性损失。
随着工业朝着更窄的特征和更薄的衬垫/晶种/阻挡物(liner/seed/barrier)发展,由无电沉积提供的优点更具吸引力。
图1是本发明的实施方式的高级流程图。在该实施方式中,在在电介质层中形成特征(步骤104)。这些特征具有延伸到互连件的通孔。在通孔底部的互连件上选择性地沉积对铜具有低溶解度的第一金属或金属合金的密封层(步骤108)。在说明书和权利要求书中,金属或金属合金可以是纯金属或金属合金。对铜具有低溶解度定义为铜在金属或金属合金中的溶解度小于1%(原子百分比)。在这种低溶解度下,金属或金属合金被认为与铜不混溶。该层的厚度为更优选为介于之间。这种干沉积之后是无电镀(electroless plating)以用对铜具有低溶解度的第二金属或金属合金填充通孔(步骤112)。在一些实施方式中,第一金属或金属合金与第二金属或金属合金相同。在其他实施方式中,第一金属或金属合金与第二金属或金属合金不同。在填充的通孔上形成阻挡层(步骤116)。用诸如铜之类的导电金属或金属合金填充沟槽(步骤120)。
在本发明的优选实施方式中,在电介质层中形成特征(步骤104)。图2A是具有衬底204的堆叠200的示意性横截面图,衬底204具有第一电介质层208,第一电介质层208具有形成在第一电介质层208中的导电互连件212。第二电介质层216形成在第一电介质层208上,第二电介质层216具有特征,该特征包括至少一个通孔220和至少一个沟槽224。该特征形成具有沟槽和通孔的双镶嵌结构。在该示例中,一个或多个层216可以设置在衬底204和第一电介质层208之间。在该实施方式中,第二电介质层216是致密的低k电介质材料。在该实施方式中,导电互连件212是铜。尽管该示例提供了使用选择性通孔填充物的双镶嵌结构的简化视图。但在其它实施方式中,电介质层由几种不同的电介质组成,所述不同的电介质是但不限于:一或多个蚀刻停止层、层间电介质、ARC层、甚至(如果需要)硬掩模。
在通孔底部的互连件上选择性地沉积对铜具有低溶解度的第一金属或金属合金的密封层(步骤108)。选择性沉积仅在催化活性材料上沉积,使得该层仅沉积在通孔底部的互连件上。在一个实施方式中,通过首先清洗特征来实现选择性沉积。铜清洗可以通过等离子体处理、通过溶剂清洗、或通过可能含有或不含有溶剂的湿式清洗来实现。湿式清洗化学物质本质上通常是酸性的,并含有羧基/羟基羧酸。在这种湿式清洗处理中产生的Cu离子对于随后的形成密封层的干(非水)沉积工艺不是活性的,因此预期不形成Co颗粒。如果铜离子没有被去除,并且经受反应性无电镀浴(electroless bath)以沉积对铜具有低溶解度的第一金属或金属合金,则铜离子倾向于更具反应性并且将被还原,从而使特征被铜金属污染并且在干金属或金属合金层的选择性沉积期间引起选择性损失。
然后使用无电沉积来在密封层上选择性地沉积对铜具有低溶解度的金属或金属合金。优选地,对铜具有低溶解度的金属或金属合金是钴、钌或铱中的一种或多种或其与其它元素(例如但不限于W、Mo、Re、P和B)的合金。在该示例中,沉积的金属或金属合金是纯钴,其对铜的溶解度为约0.8%。优选地,无电金属或金属合金镀覆浴提供对铜具有低溶解度的初始纯金属或金属组合物。在X.C.Wu、A.M.Bittner和K.Kern的Spatially SelectiveElectroless Deposition of Cobalt on Oxide Surfaces Directed by MicrocontactPrinting of Dendrimers,Langmuir 2002,18,4984-4988,I.A.L.E.Norkus的Electroless Co-BDeposition Using Dimethylamine Borane as Reducing Agent in the Presence ofDifferent Amines,ECS Transactions 2015,64(30),17-24,以及F.Pearlstein和R.F.Weightman的Electroless Cobalt Deposition from Acid BathsJ.Electrochem.Soc.1974,121(8),1023-1028中描述了用于沉积钴的配方的示例,其全部内容通过引用并入本文。在另一个示例中,无电沉积浴(electroless deposition bath)对铜具有低反应性,以减少沉积溶液与来自导电互连件212的溶解的铜相互作用。该沉积选择性沉积在铜互连件上,因为电介质侧壁不具有催化活性,因此提供了与在侧壁上进行沉积的共形沉积不同的结果。然后可以提供后沉积清洗。后沉积清洗的示例将是用于从暴露表面去除任何金属污染物和成核中心的酸洗。后沉积清洗比预沉积清洗具有较弱的反应性,使得沉积层不被损坏。
然后将该层漂洗并干燥。漂洗并干燥可以通过为此目的设计的半导体湿法加工工具上的任何常用模块完成。图2B是在选择性地沉积钴密封层228之后的堆叠200的示意性横截面图。
使用无电沉积用对铜具有低溶解度的第二金属或金属合金填充通孔(步骤112)。优选地,对铜具有低溶解度的第二金属或金属合金是钴、钌或铱中的一种或多种或其与其它元素(例如但不限于W、Mo、Re、P和B)的合金。在该示例中,沉积的第二金属或金属合金是纯钴。优选地,该无电镀浴比用于选择性地将层沉积在互连件上的无电镀浴具有更强的反应性。现在允许较强的反应性,因为铜互连件已经被第一金属/金属合金层密封,并且期望提供更快的沉积以填充通孔。较强的反应性可以通过许多方式实现,这对于本领域技术人员来说应该是显而易见的。一些示例是升高沉积温度、较高的还原剂浓度、较强反应性的还原剂、使用较弱的络合剂、使用较低浓度的络合剂、改变沉积溶液的pH。再次,这些是示例,并不意味着涵盖所有可能性,这可能对于给定的镀覆制剂是特定的。图2C是在通孔已经用钴232填充之后的堆叠200的示意性横截面图(步骤112)。
在填充的通孔上形成阻挡层(步骤116)。在本实施方式中,阻挡层包括含Ta、Ti、W或Mn的阻挡层,例如但不限于Ta、TaN、Ti、TiN、TiW、WN、WCN、Mn、MnOx或MnN。在该示例中,使用物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)沉积阻挡层。图2D是在沉积阻挡层236之后的堆叠200的示意性横截面图。
阻挡层沉积之后通常是衬垫沉积。这通常由含Ta、Co或Ru的膜组成。
通常但不一定,在用导电金属填充沟槽之前沉积晶种层。晶种层通常是铜或铜合金,但在其它实施方案中可以是Co、Ni、Ru或W中的一种或多种。使用物理气相沉积沉积晶种层。在其它实施方式中,根据衬垫类型和衬垫厚度,其他技术如电镀和无电镀(electrolessplating)也是可能的。化学气相沉积或原子层沉积晶种也是可能的。用导电金属或金属合金(通常是铜)填充沟槽(步骤120)。可以使用各种常规工艺,用含铜金属填充沟槽,各种常规工艺例如但不限于电镀、无电镀、物理气相沉积和化学气相沉积。图2E是在沉积晶种层240并且用铜244填充沟槽之后的堆叠200的示意性横截面图。
可以提供其他步骤以进一步处理该堆叠。例如,可以使用化学机械抛光(CMP)来平坦化该堆叠。图2F是在堆叠被平坦化之后的堆叠200的示意性横截面图。
在其它实施方式中,密封层在互连件上的选择性沉积可以使用对铜具有低溶解度的第一金属或金属合金的化学气相沉积(CVD)来实现。在另一个实施方式中,可以在铜互连件上选择性地沉积金属或金属合金之后并且在填充通孔之前提供阻挡层。
已经出人意料地发现,使用上述实施方式沉积对铜具有低溶解度的金属或金属合金将缺陷减少了10倍。不受理论的约束,相信上述实施方式减少了来自铜互连件的铜污染,从而减少了缺陷。更具体地,将铜表面密封以与反应性沉积溶液隔离,因此不会将Cu离子注入反应性镀液中。提供沉积对铜具有低反应性的薄膜的第一步骤减少了来自铜互连件的污染。然而,这种方法具有较慢的沉积速率并且可能不完全沉积在隔离区域中。一旦铜互连件受到保护,就可以使用更具反应性的沉积工艺来更快速地用金属或金属合金填充通孔,该金属或金属合金对铜具有低溶解度并且将完全填充隔离区域。在铜互连件上选择性沉积对铜具有低溶解度的第一金属或金属合金之后的后续清洗将进一步清洗在第一沉积工艺之后可能留下的任何铜污染物。进行密封层的干燥以从通孔中除去在沉积步骤之后在晶片表面上留下的含有铜离子的液体。
各种实施方式用反应性较低但有催化活性的金属或金属合金密封反应性表面,然后将反应性无电镀液施加到衬底上。因此,各种实施方式由两个步骤组成。第一步骤可以通过经由CVD、ALD或低反应性无电沉积工艺在反应性催化表面的顶部上选择性镀覆第一金属或金属合金膜来完成。在第二步骤中,使用更具反应性的无电镀液。由于在应用第二步骤之后没有反应性金属离子可以进入沉积溶液中,所以缺陷率将显著降低。虽然选择性的CVD和ALD沉积不产生任何Cu离子,但是低反应性Co镀覆预期仍然形成一些Cu离子。为了完全消除(可以吸附在表面上的)Cu离子效应,可能需要从电介质去除金属污染物的后清洗步骤和干燥步骤,以获得密封Cu表面的全部益处。优选地,密封层由与通孔填充物相同的金属或金属合金形成。在一些实施方式中,密封层的金属或金属合金可以不同于通孔填充物的金属或金属合金。
虽然已经根据几个优选实施方式描述了本发明,但是存在落在本发明范围内的改变、置换和各种替代等同方案。还应当注意,存在实现本发明的方法和装置的许多替代方式。因此,意图是将以下所附权利要求解释为包括落在本发明的真实精神和范围内的所有这样的改变、置换和各种替代等同方案。
Claims (10)
1.一种用金属或金属合金填充电介质层中形成的通孔的方法,所述金属或金属合金对含铜互连件上的铜具有低溶解度,其中所述通孔是具有沟槽和通孔的互连结构的一部分,所述方法包括:
直接在所述通孔底部的所述含铜互连件上选择性地沉积对铜具有低溶解度的第一金属或金属合金的密封层,其中形成所述通孔的电介质层的侧壁暴露于所述沉积所述第一金属或金属合金,并且其中选择性沉积具有低溶解度的所述第一金属或金属合金,以仅在所述含铜互连件上形成层;以及
在所述密封层上无电沉积对铜具有低溶解度的第二金属或金属合金的通孔填充物,从而填充所述通孔。
2.根据权利要求1所述的方法,其中所述无电沉积所述通孔填充物包括:
提供清洗;
执行对铜具有低溶解度的所述第二金属或金属合金的无电沉积;以及
提供酸清洗以去除金属污染物。
3.根据权利要求2所述的方法,其中所述选择性沉积所述密封层包括化学气相沉积(CVD)对铜具有低溶解度的所述第一金属或金属合金。
4.根据权利要求3所述的方法,其中对铜具有低溶解度的所述第一金属或金属合金是钴、钌或铱中的一种或多种或其与其它元素的合金,所述其它元素例如但不限于W、Mo、Re、P和B。
5.根据权利要求4所述的方法,其还包括:
在所述通孔填充物和邻近所述通孔的沟槽上方形成阻挡层;以及
用包含铜、钴、钌、镍或钨中的至少一种的导电金属或金属合金填充所述沟槽。
6.根据权利要求2所述的方法,其中所述选择性沉积所述密封层包括:
提供预沉积清洗;
在所述含铜互连件上无电沉积对铜具有低溶解度的所述第一金属或金属合金的层,以在所述含铜互连件上形成层,其中所述通孔填充物的所述无电沉积使用比用于无电沉积所述密封层的无电沉积浴更具反应性的无电沉积浴;
提供后沉积清洗;以及
漂洗并干燥所述无电沉积的层。
7.根据权利要求6所述的方法,其中对铜具有低溶解度的所述第一金属或金属合金是钴、钌或铱中的一种或多种或其与其它元素的合金,所述其它元素例如但不限于W、Mo、Re、P和B。
8.根据权利要求7所述的方法,其还包括:
在所述通孔填充物和邻近所述通孔的沟槽上方形成阻挡层;以及
用包含铜、钴、钌、镍或钨中的至少一种的导电金属或金属合金填充所述沟槽。
9.根据权利要求2所述的方法,其中所述沉积所述密封层包括:在所述含铜互连件上无电沉积对铜具有低溶解度的所述第一金属或金属合金的层,以在所述含铜互连件上形成层,其中所述通孔填充物的所述无电沉积使用与用于无电沉积所述层的无电沉积浴相比对铜更具反应性的无电沉积浴;以及
漂洗并干燥所述无电沉积的层。
10.根据权利要求9所述的方法,其中对铜具有低溶解度的所述第一金属或金属合金是钴、钌或铱中的一种或多种或其与其它元素的合金,所述其它元素例如但不限于W、Mo、Re、P和B。
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