SG10201705050UA - Dual damascene fill - Google Patents
Dual damascene fillInfo
- Publication number
- SG10201705050UA SG10201705050UA SG10201705050UA SG10201705050UA SG10201705050UA SG 10201705050U A SG10201705050U A SG 10201705050UA SG 10201705050U A SG10201705050U A SG 10201705050UA SG 10201705050U A SG10201705050U A SG 10201705050UA SG 10201705050U A SG10201705050U A SG 10201705050UA
- Authority
- SG
- Singapore
- Prior art keywords
- dual damascene
- damascene fill
- fill
- dual
- damascene
- Prior art date
Links
- 230000009977 dual effect Effects 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
- H01L21/28562—Selective deposition
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemically Coating (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/199,632 US9768063B1 (en) | 2016-06-30 | 2016-06-30 | Dual damascene fill |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201705050UA true SG10201705050UA (en) | 2018-01-30 |
Family
ID=59828330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201705050UA SG10201705050UA (en) | 2016-06-30 | 2017-06-19 | Dual damascene fill |
Country Status (5)
Country | Link |
---|---|
US (1) | US9768063B1 (en) |
KR (1) | KR102455123B1 (en) |
CN (1) | CN107564851B (en) |
SG (1) | SG10201705050UA (en) |
TW (1) | TWI783939B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11164780B2 (en) * | 2019-06-07 | 2021-11-02 | Applied Materials, Inc. | Process integration approach for selective metal via fill |
US11101171B2 (en) | 2019-08-16 | 2021-08-24 | Micron Technology, Inc. | Apparatus comprising structures including contact vias and conductive lines, related methods, and memory devices |
KR20230136217A (en) | 2021-02-08 | 2023-09-26 | 맥더미드 엔쏜 인코포레이티드 | Methods and wet chemical compositions for forming diffusion barriers |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4567066A (en) | 1983-08-22 | 1986-01-28 | Enthone, Incorporated | Electroless nickel plating of aluminum |
US4840820A (en) | 1983-08-22 | 1989-06-20 | Enthone, Incorporated | Electroless nickel plating of aluminum |
US6294836B1 (en) | 1998-12-22 | 2001-09-25 | Cvc Products Inc. | Semiconductor chip interconnect barrier material and fabrication method |
JP2002043315A (en) | 2000-07-26 | 2002-02-08 | Sony Corp | Semiconductor device and manufacturing method thereof |
EP1405336A2 (en) * | 2000-12-04 | 2004-04-07 | Ebara Corporation | Substrate processing method |
WO2003011410A1 (en) * | 2001-08-03 | 2003-02-13 | Walker Digital, Llc | Method and apparatus for generating directives for personnel |
US8241701B2 (en) * | 2005-08-31 | 2012-08-14 | Lam Research Corporation | Processes and systems for engineering a barrier surface for copper deposition |
US7049234B2 (en) | 2003-12-22 | 2006-05-23 | Intel Corporation | Multiple stage electroless deposition of a metal layer |
US7268074B2 (en) | 2004-06-14 | 2007-09-11 | Enthone, Inc. | Capping of metal interconnects in integrated circuit electronic devices |
US7476618B2 (en) * | 2004-10-26 | 2009-01-13 | Asm Japan K.K. | Selective formation of metal layers in an integrated circuit |
KR100690881B1 (en) * | 2005-02-05 | 2007-03-09 | 삼성전자주식회사 | Fabrication method of dual damascene interconnections of microelectronics and microelectronics having dual damascene interconnections fabricated thereby |
US20060188659A1 (en) | 2005-02-23 | 2006-08-24 | Enthone Inc. | Cobalt self-initiated electroless via fill for stacked memory cells |
US7273814B2 (en) | 2005-03-16 | 2007-09-25 | Tokyo Electron Limited | Method for forming a ruthenium metal layer on a patterned substrate |
US7514353B2 (en) * | 2005-03-18 | 2009-04-07 | Applied Materials, Inc. | Contact metallization scheme using a barrier layer over a silicide layer |
US20060280860A1 (en) | 2005-06-09 | 2006-12-14 | Enthone Inc. | Cobalt electroless plating in microelectronic devices |
US8771804B2 (en) | 2005-08-31 | 2014-07-08 | Lam Research Corporation | Processes and systems for engineering a copper surface for selective metal deposition |
US8258057B2 (en) | 2006-03-30 | 2012-09-04 | Intel Corporation | Copper-filled trench contact for transistor performance improvement |
US8916232B2 (en) | 2006-08-30 | 2014-12-23 | Lam Research Corporation | Method for barrier interface preparation of copper interconnect |
US7829454B2 (en) * | 2007-09-11 | 2010-11-09 | Tokyo Electron Limited | Method for integrating selective ruthenium deposition into manufacturing of a semiconductior device |
US7776740B2 (en) * | 2008-01-22 | 2010-08-17 | Tokyo Electron Limited | Method for integrating selective low-temperature ruthenium deposition into copper metallization of a semiconductor device |
BR112015001113B1 (en) | 2012-07-17 | 2021-05-18 | Coventya, Inc | method of forming a black autocatalytic nickel coating of a substrate |
US9514983B2 (en) * | 2012-12-28 | 2016-12-06 | Intel Corporation | Cobalt based interconnects and methods of fabrication thereof |
US8921167B2 (en) * | 2013-01-02 | 2014-12-30 | International Business Machines Corporation | Modified via bottom for BEOL via efuse |
US9312203B2 (en) | 2013-01-02 | 2016-04-12 | Globalfoundries Inc. | Dual damascene structure with liner |
US8673779B1 (en) * | 2013-02-27 | 2014-03-18 | Lam Research Corporation | Interconnect with self-formed barrier |
US9425092B2 (en) * | 2013-03-15 | 2016-08-23 | Applied Materials, Inc. | Methods for producing interconnects in semiconductor devices |
US9040421B2 (en) * | 2013-05-03 | 2015-05-26 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits with improved contact structures |
US9236292B2 (en) | 2013-12-18 | 2016-01-12 | Intel Corporation | Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) |
US9659856B2 (en) * | 2014-10-24 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Two step metallization formation |
US9583386B2 (en) * | 2014-10-25 | 2017-02-28 | Lam Research Corporation | Interlevel conductor pre-fill utilizing selective barrier deposition |
US10727122B2 (en) * | 2014-12-08 | 2020-07-28 | International Business Machines Corporation | Self-aligned via interconnect structures |
-
2016
- 2016-06-30 US US15/199,632 patent/US9768063B1/en active Active
-
2017
- 2017-06-19 SG SG10201705050UA patent/SG10201705050UA/en unknown
- 2017-06-26 TW TW106121193A patent/TWI783939B/en active
- 2017-06-27 KR KR1020170081177A patent/KR102455123B1/en active IP Right Grant
- 2017-06-29 CN CN201710512993.4A patent/CN107564851B/en active Active
Also Published As
Publication number | Publication date |
---|---|
KR102455123B1 (en) | 2022-10-14 |
US9768063B1 (en) | 2017-09-19 |
TW201810467A (en) | 2018-03-16 |
CN107564851B (en) | 2020-09-04 |
CN107564851A (en) | 2018-01-09 |
KR20180003447A (en) | 2018-01-09 |
TWI783939B (en) | 2022-11-21 |
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