TWI783939B - 雙重鑲嵌填充 - Google Patents

雙重鑲嵌填充 Download PDF

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TWI783939B
TWI783939B TW106121193A TW106121193A TWI783939B TW I783939 B TWI783939 B TW I783939B TW 106121193 A TW106121193 A TW 106121193A TW 106121193 A TW106121193 A TW 106121193A TW I783939 B TWI783939 B TW I783939B
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metal
copper
metal alloy
layer
solubility
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亞圖 寇力克斯
普文 那拉
烈 趙
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美商蘭姆研究公司
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Abstract

提供一種使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，該金屬或金屬合金對含銅互連線上的銅具有低溶解度，其中該貫孔係具有溝槽及貫孔之一雙重鑲嵌結構的一部分。具有低銅溶解度之一第一金屬或金屬合金的一密封層係在該貫孔的底部在該含銅互連線之正上方選擇性地加以沉積，其中形成該貫孔之該介電層的側壁係曝露於該沉積密封層的操作，且其中具有低銅溶解度的該第一金屬或金屬合金係選擇性地加以沉積，以僅在該含銅互連線上形成一層。具有低銅溶解度之一第二金屬或金屬合金的一貫孔填充物係在該密封層上無電沉積，該貫孔填充物填充該貫孔。

Description

雙重鑲嵌填充
本發明關於在半導體晶圓上形成半導體元件的一種方法。更具體而言，本發明關於使用貫孔及溝形成金屬特徵部的一種方法。
在形成半導體元件的過程中，導電金屬特徵部係在介電質中在金屬互連線上加以形成。導電金屬接觸可藉由貫孔及溝的雙重鑲嵌特徵部加以形成。
為實現上述內容且根據本揭示內容之目的，提供一種使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，該金屬或金屬合金對含銅互連線上的銅具有低溶解度，其中該貫孔係具有溝槽及貫孔之一雙重鑲嵌結構的一部分。具有低銅溶解度之一第一金屬或金屬合金的一密封層係在該貫孔的底部在該含銅互連線之正上方選擇性地加以沉積，其中形成該貫孔之該介電層的側壁係曝露於該沉積該第一金屬或金屬合金之操作，且其中具有低銅溶解度的該第一金屬或金屬合金係選擇性地加以沉積，以僅在該含銅互連線上形成一密封層。具有低銅溶解度之一第二金屬或金屬合金的一貫孔填充物係在該密封層上無電沉積，該貫孔填充物填充該貫孔。
在另一種實施態樣中，提供一種使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，該金屬或金屬合金對含銅互連線上的銅具有低溶解度，其中該貫孔係具有溝槽及貫孔之一雙重鑲嵌結構的一部分。一層具有低銅溶解度的一第一金屬或金屬合金，係在該含銅互連線上加以無電沉積，以在該含銅互連線上形成一層。該無電沉積的層係加以潤洗及乾燥。具有低銅溶解度之一第二金屬或金屬合金的一貫孔填充物，係在該層上加以無電沉積，該貫孔填充物填充該貫孔。該貫孔填充的步驟包含執行具有低銅溶解度之該第二金屬或金屬合金的無電沉積，其中該貫孔填充物的無電沉積係使用與用於無電沉積該層的無電沉積槽液相比較具反應性的無電沉積槽液。一酸清潔可加以提供以移除金屬污染物。
在另一種實施態樣中，提供一種使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，該金屬或金屬合金對含銅互連線上的銅具有低溶解度，其中該貫孔係具有溝槽及貫孔之一雙重鑲嵌結構的一部分。一層具有低銅溶解度的一第一（密封）金屬或金屬合金之化學氣相沉積物（CVD），係在該含銅互連線上加以沉積。在該層上具有低銅溶解度之一第二金屬或金屬合金的一貫孔填充物係加以無電沉積，該貫孔填充物填充該貫孔。該貫孔填充的步驟包含執行具有低銅溶解度之該第二金屬或金屬合金的無電沉積，及選用性地提供一酸清潔以移除金屬污染物。
本發明的這些及其他特徵將以下列本發明的詳細敘述結合下列圖示更詳細地加以描述。
本發明現將參照如隨附圖式中所說明的幾個較佳的實施例詳細描述。在以下說明中，為了提供本發明的透徹理解，說明許多具體細節。然而，顯然地，對於精於本項技術之人士而言，本發明可不具有某些或全部這些具體細節而實施。另一方面，為了不要不必要地模糊本發明，未詳細說明眾所周知的製程步驟及/或結構。舉例而言，本發明係不限於如何形成貫孔及溝。在描述中，大多數雙重鑲嵌實例係加以強調，但本發明可應用於在單一鑲嵌製程中形成的貫孔。
在半導體元件的形成中，特徵部係在介電層中加以形成。該等特徵部可能呈貫孔及溝的形式。貫孔可通過介電層至下方的互連線。溝僅部分地通過介電層，且在相同金屬層的特徵部之間提供導電連接，而貫孔則在不同金屬層的溝之間提供連接。
在許多應用中，選擇性的無電沉積係在基板上加以執行，該等基板相較於在基板上沉積的金屬在電化學上係較惰性的。這些基板係通常覆蓋需要在無電沉積之前加以移除的金屬氧化物膜。在氧化物移除或在一般的清潔過程中，來自基板的金屬離子進入沉積溶液或吸附在晶圓表面的其他非金屬部分上。釋放進沉積溶液中的這些金屬離子可能導致電鍍溶液中的奈米顆粒形成，其導致增加在半導體基板上的顆粒形成，從而增加缺陷率及降低電產率。此當高反應性的沉積化學品需要在表面上用以電鍍甚至是最孤立的特徵部時，特別是個問題。
在特定的情況下，在具有曝露的Cu之混合表面上的無電Co沉積，通常造成選擇性損失。這是因為在Cu的清潔過程期間，Cu離子（Cu(I)和Cu(II)兩者）係被釋放進溶液中。當潤洗清潔化學品時的這些離子可能在晶圓表面上保留且進入在電鍍製程中在清潔之後的後續步驟之沉積溶液。Cu離子可與電鍍溶液進行一些反應。Cu離子可與還原劑交互作用且在電鍍溶液中形成Cu奈米顆粒，或在Cu(I)離子的情況下，它們可能起歧化反應而形成Cu奈米顆粒。這些Cu奈米顆粒對於Co電鍍係具催化活性的。依據表面類型，受Cu顆粒包覆的這些Co將附著於在表面上產生Co結節的表面，若顆粒黏附於不具催化性的表面（諸如晶圓的介電部分），上述情形係亦被週知為選擇性損失。
隨著工業朝較窄的特徵部及較薄的襯墊/晶種/阻障推移，由無電沉積提供的優點係更具吸引力。
圖1係本發明實施例的高階流程圖。在此實施例中，特徵部係在介電層中加以形成（步驟104）。該等特徵部具有延伸至互連線的貫孔。具有低銅溶解度之第一金屬或金屬合金的密封層係在貫孔底部的互連線上選擇性地加以沉積（步驟108）。在說明書及發明申請專利範圍中，金屬或金屬合金可為純金屬或金屬合金。具有低的銅溶解度係定義為表示銅對金屬或金屬合金具有小於1%（原子百分比）的溶解度。在此種低溶解度下，金屬或金屬合金係被視為與銅不互溶。此層的厚度係5Ǻ-100Ǻ，且較佳是在10Ǻ和50Ǻ之間。此乾沉積係接著無電式電鍍，以使用具有低之銅溶解度的第二金屬或金屬合金填充貫孔（步驟112）。在一些實施例中，第一金屬或金屬合金係與第二金屬或金屬合金相同。在其他實施例中，第一金屬或金屬合金係不同於第二金屬或金屬合金。阻障層係在填充的貫孔上加以形成（步驟116）。溝槽係使用諸如銅的導電金屬或金屬合金加以填充（步驟120）。
在本發明的一較佳實施例中，特徵部係在介電層中加以形成（步驟104）。圖2A係具有基板204及第一介電層208之堆疊200的示意性橫剖面圖，導電互連線212形成在第一介電層208中。具有特徵部的第二介電層216係在第一介電層208上加以形成，該等特徵部包含至少一貫孔220及至少一溝槽224。該等特徵部形成具有溝槽及貫孔的雙重鑲嵌結構。在此示例中，一或多層216可在基板204與第一介電層208之間加以設置。在此實施例中，第二介電層216係緻密的低k介電材料。在此實施例中，導電互連線212係銅。雖然此示例提供使用選擇性的貫孔填充之雙重鑲嵌結構的簡化視圖，但在其他實施例中，介電層係由一些不同的介電質構成，該一些不同的介電質係不限於蝕刻停止層、層間介電質、ARC層、且甚至硬遮罩（若需要）。
具有低銅溶解度之第一金屬或金屬合金的密封層係在貫孔底部的互連線上選擇性地加以沉積（步驟108）。該選擇性的沉積係僅在具催化活性的材料上加以沉積，使得該層係僅在貫孔底部的互連線上加以沉積。在一實施例中，選擇性沉積係藉由首先清潔特徵部而加以實現。銅清潔可藉由電漿處理、溶劑清潔、或可能包含或可能不包含溶劑的濕清潔加以達成。濕清潔化學品本質上係通常酸性的且包含羧酸/羥基羧酸。在此濕清潔製程中產生的Cu離子對於形成密封層的後續乾（無水）沉積製程係不起作用，因此不預期有Co顆粒形成。若銅離子係沒有加以移除且經歷反應性的無電式電鍍槽液以沉積具有低銅溶解度的第一金屬或金屬合金，則銅離子傾向較具反應性且將被還原、污染具有銅金屬的特徵部且在乾金屬或金屬合金層的選擇性沉積期間造成選擇性損失。
無電沉積係接著用以在密封層上選擇性地沉積具有低銅溶解度的金屬或金屬合金。較佳是，具有低銅溶解度的金屬或金屬合金係下列其中一者以上：鈷、釕、或銥、或其他元素（諸如但不限於W、Mo、Re、P、及B）與鈷、釕、或銥的合金。在此示例中，沉積的金屬或金屬合金係純鈷，其對銅具有約0.8%的溶解度。較佳是，無電式金屬或金屬合金電鍍槽液提供具有低銅溶解度的初始純金屬或金屬組合。用於沉積鈷之配方的示例係在下列文獻中加以描述：由X. C. Wu, A. M. Bittner, and K. Kern發表於Langmuir 2002 ,18 , 4984-4988, I的“Spatially Selective Electroless Deposition of Cobalt on Oxide Surfaces Directed by Microcontact Printing of Dendrimers”；由Stankevičienė, A. Jagminienė, L. Tamašauskaitė-Tamašiūnaitė, E. Norkus發表於ECS Transactions 2015 ,64(30) , 17-24的“Electroless Co-B Deposition Using Dimethylamine Borane as Reducing Agent in the Presence of Different Amines”；及由F. Pearlstein and R. F. Weightman 發表於J. Electrochem. Soc. 1974 ,121(8) , 1023-1028的“Electroless Cobalt Deposition from Acid Baths”，其係藉由參照及為了所有目的納入本案揭示內容。在另一實例中，無電沉積槽液對銅具有低反應性，以減少沉積溶液與自導電互連線212溶解的銅之交互作用。因為介電側壁係不具催化活性，沉積物在銅互連線上選擇性地加以沉積，這因而相對於在側壁上沉積的保形沉積提供不同的結果。後沉積清潔可接著加以提供。後沉積清潔的示例將為用以從曝露的表面移除任何金屬污染及成核中心的酸清潔。後沉積清潔係比預沉積清潔較低反應性，使得沉積層係未被損壞。
該層係接著加以潤洗及乾燥。潤洗及乾燥可藉由在為此目的設計的半導體濕處理工具上之任何常用的模組加以進行。圖2B係在鈷228的密封層已選擇性地沉積之後之堆疊200的示意性橫剖面圖。
貫孔係利用無電沉積使用具有低銅溶解度的第二金屬或金屬合金加以填充（步驟112）。較佳是，具有低銅溶解度的第二金屬或金屬合金係下列其中一者以上：鈷、釕、或銥、或其他元素（諸如但不限於W、Mo、Re、P、及B）與鈷、釕、或銥的合金。在此示例中，沉積的第二金屬或金屬合金係純鈷。較佳是，該無電式槽液相較於用以在互連線上選擇性地沉積該層的無電式槽液具有較高的反應性。較高的反應性現在係可被允許的，因為銅互連線已藉由第一金屬/金屬合金層加以密封，且係期望提供較快的沉積以填充貫孔。較高的反應性可以許多方式加以達成，且對精於本項技術之人士而言應為顯而易見的。一些示例係增加沉積溫度、較高的還原劑濃度、較具反應性的還原劑、使用較弱的錯合劑、使用較低濃度的錯合劑、改變沉積溶液的pH。再次說明這些係示例且不意味著涵蓋所有可能性，其可能針對一給定電鍍配方。圖2C係在貫孔已使用鈷232加以填充之後之堆疊200的示意性橫剖面圖（步驟112）。
阻障層係在填充的貫孔上加以形成（步驟116）。在此實施例中，阻障層包含含Ta、Ti、W、或Mn的阻障，諸如但不限於Ta、TaN、Ti、TiN、TiW、WN、WCN、Mn、MnOx、或MnN。在此示例中，阻障層係使用物理氣相沉積（PVD）、化學氣相沉積（CVD）、或原子層沉積（ALD）加以沉積。圖2D係在阻障層236已加以沉積之後之堆疊200的示意性橫剖面圖。
阻障沉積之後係通常接著襯墊沉積。此係通常由含Ta、Co或Ru的膜所構成。
通常但不一定，晶種層係在使用導電金屬填充溝槽之前加以沉積。晶種層通常是銅或銅合金，但在其他實施例中可為Co、Ni、Ru、或W的其中一者以上。晶種層係使用物理氣相沉積加以沉積。在其他實施例中，依據襯墊類型及襯墊厚度，其他技術（諸如電鍍及無電式電鍍）係亦可能的。晶種之化學氣相沉積或原子層沉積係亦可能的。溝槽係使用導電金屬或金屬合金（通常係銅）加以填充（步驟120）。各種傳統製程（諸如但不限於電鍍、無電式電鍍、物理氣相沉積、及化學氣相沉積）可用於使用含銅金屬填充溝槽。圖2E係在晶種層240已加以沉積且溝槽係使用銅244加以填充之後之堆疊200的示意性橫剖面圖。
其他步驟可加以提供以進一步處理堆疊。舉例而言，化學機械拋光（CMP）可用以平坦化堆疊。圖2F係在堆疊已加以平坦化之後之堆疊200的示意性橫剖面圖。
在其他實施例中，在互連線上之密封層的選擇性沉積可使用具有低銅溶解度之第一金屬或金屬合金的化學氣相沉積（CVD）加以實現。在另一實施例中，阻障層可在選擇性地沉積金屬或金屬合金在銅互連線上之後及在填充貫孔之前加以提供。
吾人出人意料地發現，使用上述實施例沉積具有低銅溶解度的金屬或金屬合金將減少十倍的缺陷。不受理論拘束，吾人相信上述實施例減少來自銅互連線的銅污染，因而減少缺陷。更具體而言，銅表面係針對反應性沉積溶液加以密封，因此沒有Cu離子注入反應性電鍍溶液的情況發生。提供沉積對銅具低反應性的薄膜之第一步驟減少來自銅互連線的污染。然而，此等製程具有較慢的沉積速率且可能沒有在隔離的區域中完全沉積。一旦銅互連線係受到保護，則較具反應性的沉積製程可用以使用具低銅溶解度的金屬或金屬合金較迅速地填充貫孔，且如此將完全填充隔離的區域。在銅互連線上在具有低銅溶解度之第一金屬或金屬合金的選擇性沉積之後的後續清潔步驟，係進一步清潔在該第一沉積製程之後可能留下的任何銅污染物。密封層的乾燥係加以提供，以在沉積步驟之後自在晶圓表面上留下的貫孔移除含銅離子液體。
在將反應性的無電式電鍍溶液施加於基板上之前，各種實施例使用較低反應性但具催化活性的金屬或金屬合金密封具反應性的表面。因此，各種實施例係由兩個步驟所構成。第一步驟可藉由CVD、ALD、或低反應性的無電沉積製程，在具反應性的催化表面之頂部上選擇性電鍍第一金屬或金屬合金膜而加以完成。在第二步驟中，較具反應性的無電式電鍍溶液係加以使用。由於在進行第二步驟期間沒有反應性的金屬離子可進入沉積溶液，缺陷率將為顯著較低的。雖然選擇性的CVD及ALD沉積沒有產生任何Cu離子，但低反應性的Co電鍍係被預期仍形成一些。為了完全消除Cu離子的影響（其可吸附在表面上），可能需要自介電質移除金屬污染物的後清潔步驟及乾燥步驟，以獲得密封Cu表面的全部優點。較佳是，密封層係由與貫孔填充物相同的金屬或金屬合金加以形成。在一些實施例中，密封層的金屬或金屬合金可能與貫孔填充物的金屬或金屬合金不同。
雖然本發明已由幾個較佳的實施例加以描述，但仍存在變更、置換、及各種替代等同物，其皆落入本發明的範疇之內。亦應注意有許多替代的方式實施本發明的方法及設備。因此，下列隨附申請專利範圍意欲被解釋為包含落入本發明的真實精神及範圍內的所有這些變更、置換及各種替代等同物。
104‧‧‧步驟108‧‧‧步驟112‧‧‧步驟116‧‧‧步驟120‧‧‧步驟200‧‧‧堆疊204‧‧‧基板208‧‧‧第一介電層212‧‧‧導電互連線216‧‧‧第二介電層220‧‧‧貫孔224‧‧‧溝槽228‧‧‧鈷232‧‧‧鈷236‧‧‧阻障層240‧‧‧晶種層244‧‧‧銅
在隨附圖式的圖中，本發明係以示例為目的而不是以限制為目的加以說明，且其中類似的參考數字係關於相似的元件，且其中：
圖1係本發明實施例的流程圖。
圖2A-F係使用發明製程的結構之形成示意圖。
104‧‧‧步驟
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116‧‧‧步驟
120‧‧‧步驟

Claims (11)

  1. 一種使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，該金屬或金屬合金對含銅互連線上的銅具有低溶解度，其中該貫孔係具有溝槽及貫孔之一互連線結構的一部分，該方法包含：在該貫孔的底部在含銅互連線正上方，選擇性地沉積具有低銅溶解度之一第一金屬或具有低銅溶解度之金屬合金的一密封層，其中形成該貫孔之該介電層的側壁係曝露於該沉積該第一金屬或金屬合金之操作，且其中具有低銅溶解度的該第一金屬或具有低銅溶解度之金屬合金係選擇性地加以沉積以僅在該含銅互連線上形成一層；及在該密封層上無電沉積具有低銅溶解度之一第二金屬或具有低銅溶解度之金屬合金的一貫孔填充物，其填充該貫孔，包含：提供一清潔操作；執行具有低銅溶解度之該第二金屬或具有低銅溶解度之金屬合金的無電沉積；及提供一酸清潔，以移除金屬污染物；其中，沉積該密封層的步驟包含：在該含銅互連線上無電沉積一層具有低銅溶解度的該第一金屬或具有低銅溶解度之金屬合金，以在該含銅互連線上形成一層，其中該貫孔填充物的無電沉積係使用與用於無電沉積該層的無電沉積槽液相比對銅較具反應性的無電沉積槽液；及潤洗及乾燥該無電沉積的層。
  2. 如申請專利範圍第1項之使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，其中，具有低銅溶解度的該第一金屬或具有低銅溶解度之 金屬合金係鈷、釕、或銥、或其他元素與鈷、釕、或銥之合金的其中一者以上，該其他元素係選自包含W、Mo、Re、P、及B的一群組。
  3. 如申請專利範圍第2項之使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，更包含：在毗鄰貫孔之一溝槽及該貫孔填充物上形成一阻障層；及使用一導電金屬或金屬合金填充該溝槽，該導電金屬或金屬合金包含銅、鈷、釕、鎳、或鎢的其中至少一者。
  4. 如申請專利範圍第1項之使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，更包含：在毗鄰貫孔之一溝槽及該貫孔填充物上形成一阻障層；及使用一導電金屬或金屬合金填充該溝槽，該導電金屬或金屬合金包含銅、鈷、釕、鎳、或鎢的其中至少一者。
  5. 如申請專利範圍第1項之使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，其中，該密封層具有在5Å-100Å之間的厚度。
  6. 一種使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，該金屬或金屬合金對含銅互連線上的銅具有低溶解度，其中該貫孔係具有溝槽及貫孔之一互連線結構的一部分，該方法包含：在該貫孔的底部在含銅互連線正上方，選擇性地沉積具有低銅溶解度之一第一金屬或具有低銅溶解度之金屬合金的一密封層，其中形成該貫孔之該介電層的側壁係曝露於該沉積該第一金屬或金屬合金之操作，且其中具有低銅溶解度的該第一金屬或具有低銅溶解度之金屬合金係選擇性地加以沉積以僅在該含銅互連線上形成一層；及在該密封層上無電沉積具有低銅溶解度之一第二金屬或具有低銅溶解度之金屬合金的一貫孔填充物，其填充該貫孔，包含： 提供一清潔操作；執行具有低銅溶解度之該第二金屬或具有低銅溶解度之金屬合金的無電沉積；及提供一酸清潔，以移除金屬污染物；其中，該選擇性地沉積該密封層的步驟包含：提供一預沉積清潔操作；在該含銅互連線上無電沉積一層具有低銅溶解度的該第一金屬或具有低銅溶解度之金屬合金，以在該含銅互連線上形成一層，其中該貫孔填充物的無電沉積係使用與用於無電沉積該密封層的無電沉積槽液相比較具反應性的無電沉積槽液；提供一後沉積清潔操作；及潤洗及乾燥該無電沉積的層。
  7. 如申請專利範圍第6項之使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，其中，具有低銅溶解度的該第一金屬或具有低銅溶解度之金屬合金係鈷、釕、或銥、或其他元素與鈷、釕、或銥之合金的其中一者以上，該其他元素係選自包含W、Mo、Re、P、及B的一群組。
  8. 如申請專利範圍第7項之使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，更包含：在毗鄰貫孔之一溝槽及該貫孔填充物上形成一阻障層；及使用一導電金屬或金屬合金填充該溝槽，該導電金屬或金屬合金包含銅、鈷、釕、鎳、或鎢的其中至少一者。
  9. 一種使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，該金屬或金屬合金對含銅互連線上的銅具有低溶解度，其中該貫孔係具有溝槽及貫孔之一互連線結構的一部分，該方法包含： 在該含銅互連線上無電沉積一層具有低銅溶解度的一第一金屬或金屬合金，以在該含銅互連線上形成一層；乾燥該無電沉積的層；及在該層上無電沉積具有低銅溶解度之一第二金屬或金屬合金的一貫孔填充物，其填充該貫孔；此步驟包含：執行具有低銅溶解度之該第二金屬或金屬合金的無電沉積，其中該貫孔填充物的無電沉積係使用與用於無電沉積該層的無電沉積槽液相比較具反應性的無電沉積槽液；及提供一酸清潔，以移除金屬污染物。
  10. 如申請專利範圍第9項之使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，其中，具有低銅溶解度的該第一金屬或金屬合金係鈷、釕、或銥、或其他元素與鈷、釕、或銥之合金的其中一者以上，該其他元素係選自包含W、Mo、Re、P、及B的一群組。
  11. 如申請專利範圍第10項之使用金屬或金屬合金填充在一介電層中形成之貫孔的方法，更包含：在毗鄰貫孔之一溝槽及該貫孔填充物上形成一阻障層；及使用一導電金屬或金屬合金填充該溝槽，該導電金屬或金屬合金包含銅、鈷、釕、鎳、或鎢的其中至少一者。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11164780B2 (en) * 2019-06-07 2021-11-02 Applied Materials, Inc. Process integration approach for selective metal via fill
US11101171B2 (en) 2019-08-16 2021-08-24 Micron Technology, Inc. Apparatus comprising structures including contact vias and conductive lines, related methods, and memory devices
WO2022170169A1 (en) 2021-02-08 2022-08-11 Macdermid Enthone Inc. Method and wet chemical compositions for diffusion barrier formation

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060121733A1 (en) * 2004-10-26 2006-06-08 Kilpela Olli V Selective formation of metal layers in an integrated circuit
CN1835206A (zh) * 2005-02-05 2006-09-20 三星电子株式会社 利用保护性通路盖层形成半导体器件的双镶嵌布线的方法
US20060252252A1 (en) * 2005-03-18 2006-11-09 Zhize Zhu Electroless deposition processes and compositions for forming interconnects
CN104051336A (zh) * 2013-03-15 2014-09-17 应用材料公司 用于在半导体装置中产生互连的方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4567066A (en) 1983-08-22 1986-01-28 Enthone, Incorporated Electroless nickel plating of aluminum
US4840820A (en) 1983-08-22 1989-06-20 Enthone, Incorporated Electroless nickel plating of aluminum
US6294836B1 (en) 1998-12-22 2001-09-25 Cvc Products Inc. Semiconductor chip interconnect barrier material and fabrication method
JP2002043315A (ja) 2000-07-26 2002-02-08 Sony Corp 半導体装置およびその製造方法
WO2002047139A2 (en) * 2000-12-04 2002-06-13 Ebara Corporation Methode of forming a copper film on a substrate
WO2003011410A1 (en) * 2001-08-03 2003-02-13 Walker Digital, Llc Method and apparatus for generating directives for personnel
US8241701B2 (en) * 2005-08-31 2012-08-14 Lam Research Corporation Processes and systems for engineering a barrier surface for copper deposition
US7049234B2 (en) 2003-12-22 2006-05-23 Intel Corporation Multiple stage electroless deposition of a metal layer
US7268074B2 (en) 2004-06-14 2007-09-11 Enthone, Inc. Capping of metal interconnects in integrated circuit electronic devices
US20060188659A1 (en) 2005-02-23 2006-08-24 Enthone Inc. Cobalt self-initiated electroless via fill for stacked memory cells
US7273814B2 (en) 2005-03-16 2007-09-25 Tokyo Electron Limited Method for forming a ruthenium metal layer on a patterned substrate
US20060280860A1 (en) 2005-06-09 2006-12-14 Enthone Inc. Cobalt electroless plating in microelectronic devices
US8771804B2 (en) 2005-08-31 2014-07-08 Lam Research Corporation Processes and systems for engineering a copper surface for selective metal deposition
US8258057B2 (en) 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
US8916232B2 (en) 2006-08-30 2014-12-23 Lam Research Corporation Method for barrier interface preparation of copper interconnect
US7829454B2 (en) * 2007-09-11 2010-11-09 Tokyo Electron Limited Method for integrating selective ruthenium deposition into manufacturing of a semiconductior device
US7776740B2 (en) * 2008-01-22 2010-08-17 Tokyo Electron Limited Method for integrating selective low-temperature ruthenium deposition into copper metallization of a semiconductor device
BR112015001113B1 (pt) 2012-07-17 2021-05-18 Coventya, Inc método de formação de um revestimento de níquel autocatalítico preto de um substrato
US9514983B2 (en) * 2012-12-28 2016-12-06 Intel Corporation Cobalt based interconnects and methods of fabrication thereof
US8921167B2 (en) * 2013-01-02 2014-12-30 International Business Machines Corporation Modified via bottom for BEOL via efuse
US9312203B2 (en) 2013-01-02 2016-04-12 Globalfoundries Inc. Dual damascene structure with liner
US8673779B1 (en) * 2013-02-27 2014-03-18 Lam Research Corporation Interconnect with self-formed barrier
US9040421B2 (en) * 2013-05-03 2015-05-26 GlobalFoundries, Inc. Methods for fabricating integrated circuits with improved contact structures
US9236292B2 (en) 2013-12-18 2016-01-12 Intel Corporation Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD)
US9659856B2 (en) * 2014-10-24 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Two step metallization formation
US9583386B2 (en) * 2014-10-25 2017-02-28 Lam Research Corporation Interlevel conductor pre-fill utilizing selective barrier deposition
US10727122B2 (en) * 2014-12-08 2020-07-28 International Business Machines Corporation Self-aligned via interconnect structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060121733A1 (en) * 2004-10-26 2006-06-08 Kilpela Olli V Selective formation of metal layers in an integrated circuit
CN1835206A (zh) * 2005-02-05 2006-09-20 三星电子株式会社 利用保护性通路盖层形成半导体器件的双镶嵌布线的方法
US20060252252A1 (en) * 2005-03-18 2006-11-09 Zhize Zhu Electroless deposition processes and compositions for forming interconnects
CN104051336A (zh) * 2013-03-15 2014-09-17 应用材料公司 用于在半导体装置中产生互连的方法

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