CN107533960B - 制造三维装置的方法以及形成多栅极式晶体管的方法 - Google Patents

制造三维装置的方法以及形成多栅极式晶体管的方法 Download PDF

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CN107533960B
CN107533960B CN201680022679.1A CN201680022679A CN107533960B CN 107533960 B CN107533960 B CN 107533960B CN 201680022679 A CN201680022679 A CN 201680022679A CN 107533960 B CN107533960 B CN 107533960B
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孙世宇
吉田尚美
班杰明·科伦贝亚努
汉斯-乔辛·L·格斯曼
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Abstract

一种形成三维装置的方法以及一种形成多栅极式晶体管的方法。所述形成三维装置的方法可包括:将离子引导至鳍片结构的延伸区的端面,所述鳍片结构自基板平面垂直地延伸且具有平行于所述基板平面的鳍片轴线,其中所述离子具有在垂直于所述基板平面且平行于所述鳍片轴线的平面中延伸的轨迹,其中所述鳍片结构的一部分被栅极结构覆盖,所述栅极结构定义通道区,且其中所述端面不被所述栅极结构覆盖。

Description

制造三维装置的方法以及形成多栅极式晶体管的方法
技术领域
本发明实施例涉及三维装置结构,且更具体而言,涉及用于掺杂三维装置的技术。
背景技术
现今,使用三维晶体管装置来提供比平面晶体管更高的性能。例如鳍式场效晶体管(fin field effect transistor,finFET)装置及水平环栅(horizontal-Gate-All-Around,hGAA)FET等装置是由自基板平面(例如硅晶片的平面)垂直地延伸的鳍片形半导体区形成。此种装置中的相邻鳍片可靠近彼此进行堆积,其中考虑到包括多晶硅层及罩幕层在内的额外层,在处理过程中的某些阶段,鳍片结构高度:鳍片结构间距的比率可接近10∶1。在这些情况下,可能难以对鳍片结构的源极/漏极或源极/漏极延伸区进行植入,这是因为被引导至给定鳍片结构的表面的离子会被一个或多个相邻鳍片遮挡。
有鉴于这些及其他考虑而提供本发明。
发明内容
在一个实施例中,一种形成三维装置的方法可包括:将离子引导至鳍片结构的延伸区的端面,所述鳍片结构自基板平面垂直地延伸且具有平行于所述基板平面的鳍片轴线,其中所述离子具有在垂直于所述基板平面且平行于所述鳍片轴线的平面中延伸的轨迹,其中所述鳍片结构的一部分被栅极结构覆盖,所述栅极结构定义通道区,且其中所述端面不被所述栅极结构覆盖。
在另一实施例中,一种形成三维装置的方法可包括:提供多个鳍片结构,所述鳍片结构自基板平面垂直地延伸,所述鳍片结构相互平行且具有平行于所述基板平面的鳍片轴线;提供栅极结构,所述栅极结构覆盖所述鳍片结构的一部分,其中所述栅极结构定义给定鳍片结构的暴露区;移除所述暴露区的至少一部分,其中所述鳍片结构的暴露区被形成为具有不被所述栅极结构覆盖的端面;以及将离子引导至所述端面,所述离子具有在垂直于所述基板平面且平行于所述鳍片轴线的平面中延伸的轨迹。
在再一实施例中,一种形成多栅极式晶体管中的源极/漏极区的方法可包括:提供多个鳍片结构,所述鳍片结构自基板平面垂直地延伸,所述鳍片结构相互平行且具有平行于所述基板平面的鳍片轴线,其中所述鳍片结构包含至少单晶硅。所述方法可还包括:提供栅极结构,所述栅极结构覆盖所述鳍片结构的一部分,其中所述栅极结构定义给定鳍片结构的暴露区。所述方法还可包括:在执行源极/漏极延伸植入之前,移除所述暴露区的至少一部分,其中所述鳍片结构的延伸区形成为具有不被所述栅极结构覆盖的端面。
附图说明
图1的(a)至(c)说明根据本发明实施例的装置在不同的制造阶段期间的侧视图。
图2显示图1所示装置在图1的(c)所显示阶段期间的端部透视图。
图3的(a)至(c)说明根据本发明其他实施例的另一装置在不同的制造阶段期间的侧视图。
图4显示图3所示装置在图3的(c)所显示的阶段期间的端部透视图。
图5显示根据本发明各种实施例的用于制造装置的示例性制造流程。
图6显示根据本发明再一些实施例的另一示例性制造流程。
具体实施方式
现在将参照其中示出某些实施例的附图更全面地阐述本发明实施例。本发明的主题可实施为许多不同形式,而不应被视为仅限于本文所述实施例。提供这些实施例是为了使本公开内容将透彻及完整,且将向所属领域中的技术人员全面传达所述主题的范围。在所有附图中,相同的编号均指代相同的元件。
本文所述实施例提供用于形成包括多栅极式金属氧化物半导体场效晶体管(metal oxide semiconductor field effect transistor,MOSFET)的三维装置的新颖处理及装置结构。术语“多栅极式晶体管”或“多栅极式MOSFET”是指一种类型的三维装置,在此种类型的三维装置中,晶体管的通道区自基板表面延伸以呈现出多个侧面以供栅极接触。多栅极式MOSFET的实例包括finFET装置或hGAA FET装置、以及垂直通道式FET装置。多栅极式MOSFET的特性是给定的栅极结构形成于半导体通道的各个不同的侧面上,其中所述半导体通道可形成于鳍片结构内。因此,与平面式MOSFET相比,栅极结构可用于自各个侧对通道进行闸控,在平面式MOSFET中,闸控是仅自通道的顶侧进行。各种实施例有利于改善对例如三维场效晶体管的源极/漏极延伸(source/drain extension,SDE)区、源极/漏极(SD)及相邻区等晶体管特征的掺杂。
图1的(a)至(c)说明根据本发明实施例的装置120在不同的制造阶段期间的侧视图。图2显示图1所示装置在图1的(c)所显示阶段期间的端部透视图。如图1的(a)所说明,鳍片结构102安置于基板100上。鳍片结构102在某些实例中可构成晶体材料,例如单晶硅。鳍片结构102自基板100的基板平面(X-Y平面)垂直地延伸。在图1的(a)所示的形成阶段,栅极结构104也安置于鳍片结构102之上。在某些情形中,栅极结构104可为将在后续处理阶段中被替换的虚设栅极(dummy gate)。如在图2中所更清楚地说明,多个鳍片结构102可相互平行地排列且可具有平行于所示笛卡尔座标系(Cartesian coordinate system)中的X轴(及平行于基板平面P)延伸的鳍片轴线。鳍片轴线可平行于所要形成的晶体管装置中源极/漏极区之间的电流流动方向。如在图1的(a)中所进一步显示,侧壁106可沿栅极结构104形成,其中栅极结构104(及侧壁106)以留出暴露区118的方式覆盖鳍片结构102。
在现有的装置制造技术中,源极/漏极区及源极/漏极延伸区可被植入离子,以引入目标程度的掺杂剂在通道的相对各侧上形成源极区及漏极区。通道(图中未示出)可形成于被栅极结构104的至少一部分覆盖的鳍片结构的一部分中。为将掺杂剂引入此种源极/漏极区或源极/漏极延伸区中,现有技术可将离子植入至例如图1的(a)所示的装置结构中,其中离子轨迹位于Y-Z平面内。在此种现有方法中,离子相对于Z轴以低的入射角植入,以撞击位于X-Z平面中的鳍片结构102的侧面122。由于鳍片结构102沿Z方向的高度以及各鳍片结构102沿Y方向的紧密间距,在某些现有技术中,离子相对于Z轴以近似7度或小于7度的角度朝侧面122引导。
根据本发明的各种实施例,一种创新技术提供对前述方法的改良。此种新颖且创新的技术的实例说明于图1的(b)及图1的(c)中。在图1的(b)中,暴露区118的一部分被自鳍片结构102移除。在此实例中,鳍片结构102可被至少蚀刻至基板100。所述实施例在本上下文中不受限制。
当如图1的(b)所示蚀刻鳍片结构102时,形成延伸区124,所述延伸区124呈现出端面126。鳍片结构102的一部分被栅极结构104覆盖,从而定义通道区129。
端面126在此处理阶段形成鳍片结构102的端面,且表示不被栅极结构104或侧壁106覆盖的表面。同样地,在鳍片结构102的相对的端部上,形成第二延伸区(也称为延伸区124)。在鳍片结构102的此相对的端部上,延伸区具有端面127,端面127也不被栅极结构104或侧壁106覆盖。如图所说明,端面126及端面127可平行于Y-Z平面。
现在转至图1的(c),在对暴露区118进行蚀刻而形成延伸区124后,可将离子112引导至延伸区124。具体而言,可将离子引导至端面126及端面127。举例来说,可在一个植入过程中或在多个植入过程中将离子112植入至延伸区124中,以充当源极/漏极延伸(SDE)掺杂植入剂,并可另外充当用于“晕圈(halo)”掺杂的离子。在此实施例中,可沿位于X-Z平面内的轨迹引导离子112,其中X-Z平面垂直于与X-Y平面平行的基板平面P。端面126及端面127可平行于Y-Z平面。因此,离子122的轨迹可位于与端面126的平面及端面127的平面垂直的平面内。离子112可具有也相对于基板平面P的垂线130而形成非零入射角的轨迹,所述非零入射角被示出为入射角θ。如图1的(c)中所说明,离子112可在一个植入过程中以+θ角被引导至端面126并在第二植入过程中以-θ角被引导至端面127。在一个其中离子112是掺杂剂离子的实例中,离子可在经由端面126植入时形成第一源极/漏极延伸且在经由端面127植入时形成第二源极/漏极延伸。这两个源极/漏极延伸可形成两个接面,这两个接面定义沿穿过鳍片结构102的X轴延伸的通道的相对端部。在图1的(a)至(c)所显示的操作之后,可将源极/漏极区重新生长至暴露区118中。应注意,角度-θ与+θ角度可具有相同的大小或不同的大小。
图1的(a)至(c)中所显示的方法的优点是能够以比finFET结构或hGAAFET结构的现有处理中大的入射角θ提供离子112。在现有方法中,例如,源极/漏极延伸植入可进行至图1的(a)中所示阶段的装置结构。最大倾斜角可定义为角度θcrit,其中入射离子112能够到达端面126的底部而不被相邻结构116的顶部阻挡。最大倾斜角可被计算为θcrit=arctan(<相邻结构116与包括侧壁106的栅极结构104之间沿X轴的距离S>/<高度hT,自鳍片结构102的底部至栅极结构104的顶部的总栅极高度>),或者更简单地说,(S/hT)。图1的(c)所示的此距离S表示端面126与相邻结构116之间沿X轴的距离。应注意,在图1的(a)至(c)所示的方法中,相邻结构116与位于栅极结构104下方的鳍片结构102位于同一鳍片串中,且因此为相同的极性。因此,当向延伸区124中执行离子注入时,相邻结构116不具有罩幕(例如光阻)。相比较而言,对于其中源极/漏极延伸植入发生至鳍片结构102的侧面122的现有方法,现在在Y-Z平面中倾斜地入射的离子112须穿过相邻的鳍片结构102(参照图2)。经常,相邻的鳍片结构102具有彼此相反的极性,因此当相邻鳍片被植入时,第一鳍片会受到罩幕(图中未示出)保护。此罩幕的厚度须通过加至上述θcrit公式的分母中而被考虑在内,从而使其中离子在Y-Z平面中倾斜且被植入鳍片结构102的侧面122中的现有植入方法的θcrit变小。在一个具体实例中,对于7nm技术节点,离子112可相对于方向130而以10度至12度的入射角、且尤其是12度的入射角被引导至端面126。相比之下,对于相同的技术节点,当根据现有技术在鳍片结构的侧面引导离子时离子的最大角度是7度。
相比较而言,对于给定的倾斜角,使用在平面Y-Z中倾斜且入射至鳍片结构102的侧面122中的现有方法植入的离子也会植入暴露区118中的鳍片结构102的顶面132。顶面132的入射角由倾斜角θ表示;至于鳍片结构102的侧面122,入射角可被表达为90-θ。此种差异使得植入至顶面132中的有效剂量比植入至鳍片结构102的侧面122的有效剂量大得多,从而导致在植入期间及在鳍片顶部区处的后续热处理期间掺杂剂体积浓度高得多且掺杂剂向通道内的横向穿透更大。相比之下,无论离子沿端面126的高度h在何处撞击,以在X-Z平面中具有倾斜的方式将离子112引导至端面126均提供相同的入射角,从而得到更佳的接面平面度。
图3的(a)至(c)说明根据本发明其他实施例的装置220在不同的制造阶段期间的侧视图。图4显示图3所示装置在图3的(c)所显示阶段期间的端部透视图。如图3的(a)中所说明,鳍片结构200安置于基板100上。鳍片结构200可在某些实例中构成多个不同的半导体层,例如至少三个层。在某些情形中,至少一个层可包含第一半导体材料,且至少一个层可包含第二半导体材料。在一个实例中,第一半导体层202可与第二半导体层204交错。在一个实例中,第一半导体层202可为单晶硅,且第二半导体层204可为单晶硅:锗。鳍片结构200可用作通过相对于相应的层(层204或层202)而选择性地蚀刻层202或层204来形成水平环栅装置结构(hGAA FEG结构)的基础,如所属领域中所已知。在其他方面,鳍片结构200的处理可如上文参照图1及图2所述。因此,延伸区224的端面226及端面227可被以比其中离子朝位于Y-Z平面内的鳍片结构200的侧面引导的现有技术所能实现的入射角θ大的入射角θ来植入离子112。
在图1至图3的实施例中,与将离子引导至鳍片结构的侧壁中的现有技术的方法相比,将离子引导至鳍片结构的端面中的能力可提供更均匀的掺杂。已进行了模拟。使用图1至图3所大体说明的方法(其中离子位于X-Z平面中)及其中将离子引导至鳍片侧壁中(其中离子位于Y-Z平面中)的传统源极/漏极延伸离子注入制程对鳍片结构执行了源极/漏极延伸植入。结果表明,与传统方法相比,由本发明实施例的技术形成的源极/漏极延伸区之间的接面更均匀。另外,与传统方法相比,根据本发明实施例的装置内的有效通道长度(Leff)的变化较小。此可部分地归因于离子直接植入至端面126或端面127中,其中这些端面平行(在Y-Z平面中)于将由所述源极/漏极延伸植入所生成的目标接面。通过此种方式,所植入的离子可均匀地分布于端面126及端面127上,且可相对于端面126及端面127以更均匀的深度植入。
图5显示根据本发明各种实施例的用于制造装置的示例性制造流程350。例如,示例性制造流程350可代表用于制造例如hGAA晶体管的操作的一部分。在第一操作290中,进行多晶硅沉积后可进行化学机械研磨(chemical-mechanical polishing,CMP)。在操作292中,可对所沉积的多晶硅应用微影,以定义栅极图案。在操作294中,可执行蚀刻以定义栅极结构。在图5所示的后续操作中,传统顺序可由以下表示:操作300,进行源极/漏极延伸间隔壁沉积及蚀刻;操作302,进行源极/漏极延伸植入/晕圈植入;操作304,进行磊晶间隔壁沉积及蚀刻;操作306,进行凹槽蚀刻;以及操作308,进行凸起源极/漏极磊晶沉积。此种传统顺序可能需要操作302,以在鳍片结构的侧壁处以相对较低的角度(例如7度)引导离子,如上文所述。接着,在操作306的凹槽蚀刻期间,可蚀刻掉鳍片的暴露区,以允许在操作308中生长凸起的源极/漏极。根据本发明的实施例,可移动操作302以使新的操作顺序为:操作300,操作304,操作306,操作302,及操作308。另外,操作302可能需要以相对较大的角度(例如12度)朝鳍片结构的端面引导离子,如上文所述。
图6显示根据本发明其他实施例的另一示例性制造流程400。在方块402中,提供自基板平面垂直地延伸的多个鳍片结构,其中所述鳍片型结构相互平行且具有鳍片轴线。在不同的实施例中,鳍片结构可由单晶硅或由多个不同的半导体层形成。在一个实例中,鳍片结构的第一半导体层可与第二半导体层交错。在一个实例中,第一半导体层可为单晶硅,且第二半导体层可为单晶硅:锗合金。
在方块404中,提供覆盖鳍片结构的一部分的栅极结构,其中栅极结构定义给定鳍片结构的暴露区。
在方块406中,移除暴露区的一部分,其中形成延伸区,所述延伸区具有不被栅极结构覆盖的端面。
在方块408中,将离子引导至延伸区,其中离子具有在垂直于基板平面、垂直于端面的平面、且平行于鳍片轴线的平面中延伸的轨迹。
本发明实施例所提供的优点包括:与现有方法相比,能够将离子相对于被植入的鳍片表面以较大的入射角引导至鳍片结构中以进行源极/漏极延伸掺杂。例如,由于可沿其中各相邻结构具有相同极性的给定鳍片串执行植入,因而在所植入的同一鳍片串上与所述鳍片结构相邻的结构上不存在光阻。此使得与传统方法所采用的较小的入射角(例如7度)相比,离子能够更均匀地穿透至鳍片表面中。另一优点是能够将掺杂剂以更均匀的方式引导至鳍片结构中,这是因为掺杂剂可植入至代表鳍片结构横截面的整个端面中,从而使离子均匀地“照射”此横截面。如此一来,与传统方法相比,本发明的实施例可产生更平的接面。
本发明的范围不受本文所述具体实施例限制。实际上,通过阅读以上说明及附图,除本文中所述实施例以外的本发明其他各种实施例及对本发明进行的润饰将对所属领域中的普通技术人员显而易见。因此,此种其他实施例及润饰旨在落于本发明的范围内。此外,本文中已在用于特定目的的特定环境中的特定实施方式的上下文中阐述了本发明。所属领域中的普通技术人员将认识到其适用性并非仅限于此,且本发明可有利地实作于用于任意数目的目的的任意数目的环境中。因此,必须虑及本文所述本发明的全部广度及精神来解释以上所述权利要求。

Claims (14)

1.一种形成三维装置的方法,其特征在于,包括:
将离子引导至鳍片结构的延伸区的端面,所述鳍片结构自基板平面垂直地延伸且具有平行于所述基板平面的鳍片轴线,
其中所述离子具有在垂直于所述基板平面且平行于所述鳍片轴线的平面中延伸的轨迹,
其中所述鳍片结构的一部分被栅极结构覆盖,所述栅极结构定义通道区,
其中在引导所述离子期间,所述端面不被所述栅极结构覆盖且不延伸超过所述栅极结构,且其中所述离子均匀地分布于所述端面上。
2.根据权利要求1所述的形成三维装置的方法,其特征在于,所述鳍片结构包含单晶硅。
3.根据权利要求1所述的形成三维装置的方法,其特征在于,所述鳍片结构包括至少三个层,其中至少一个层包含硅且至少一个层包含硅:锗合金。
4.根据权利要求1所述的形成三维装置的方法,其特征在于,所述轨迹相对于所述基板平面的垂线形成10度至12度的入射角。
5.根据权利要求1所述的形成三维装置的方法,其特征在于,所述离子被提供作为源极/漏极延伸植入剂。
6.根据权利要求1所述的形成三维装置的方法,其特征在于,还包括:在将所述离子引导至所述端面之后,在所述延伸区上形成凸起的源极/漏极。
7.根据权利要求1所述的形成三维装置的方法,其特征在于,所述栅极结构定义所述鳍片结构的暴露区,所述方法还包括移除所述暴露区的一部分,其中形成所述鳍片结构的所述延伸区。
8.一种形成三维装置的方法,其特征在于,包括:
提供多个鳍片结构,所述鳍片结构自基板平面垂直地延伸,所述鳍片结构相互平行且具有平行于所述基板平面的鳍片轴线;
提供栅极结构,所述栅极结构覆盖所述鳍片结构的一部分,其中所述栅极结构定义给定鳍片结构的暴露区;
移除所述暴露区的至少一部分,其中所述鳍片结构的暴露区被形成为具有不被所述栅极结构覆盖的端面,所述端面不延伸超过所述栅极结构;以及
在移除所述暴露区的所述至少一部分之后,将离子引导至所述端面,所述离子具有在垂直于所述基板平面且平行于所述鳍片轴线的平面中延伸的轨迹,其中所述离子均匀地分布于所述端面上。
9.根据权利要求8所述的形成三维装置的方法,其特征在于,所述多个鳍片结构包含单晶硅。
10.根据权利要求8所述的形成三维装置的方法,其特征在于,所述多个鳍片结构包括至少三个层,其中至少一个层包含硅且至少一个层包含硅:锗合金,其中所述鳍片结构构成水平环栅装置结构的一部分。
11.根据权利要求8所述的形成三维装置的方法,其特征在于,所述轨迹相对于所述基板平面的垂线形成10度至12度的入射角。
12.根据权利要求8所述的形成三维装置的方法,其特征在于,所述三维装置包括多个鳍片串,其中给定的鳍片串包括给定的鳍片结构以及与所述鳍片结构的所述端面相隔距离S的相邻结构,其中所述栅极结构是由高度hT定义,且其中以由arctan(S/hT)定义的入射角引导所述离子。
13.根据权利要求8所述的形成三维装置的方法,其特征在于,所述多个鳍片结构构成鳍式场效晶体管装置的部分或水平环栅装置的部分。
14.一种形成多栅极式晶体管的方法,其特征在于,包括:
提供多个鳍片结构,所述鳍片结构自基板平面垂直地延伸,所述鳍片结构相互平行且具有平行于所述基板平面的鳍片轴线,其中所述鳍片结构包含至少单晶硅;
提供栅极结构,所述栅极结构覆盖所述鳍片结构的一部分,其中所述栅极结构定义给定鳍片结构的暴露区;
移除所述暴露区的至少一部分,以形成所述鳍片结构的延伸区,
其中所述鳍片结构的所述延伸区具有不被所述栅极结构覆盖的端面,所述端面不延伸超过所述栅极结构;以及
在移除所述暴露区的所述至少一部分之后,执行源极/漏极延伸植入,所述源极/漏极延伸植入包括:将掺杂剂离子引导至所述端面,所述掺杂剂离子具有在垂直于所述基板平面且平行于所述鳍片轴线的平面中延伸的轨迹,其中所述轨迹相对于所述基板平面的垂线形成非零入射角,其中所述掺杂剂离子在所述鳍片结构内形成源极/漏极延伸,且其中所述掺杂剂离子均匀地分布于所述端面上。
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Publication number Priority date Publication date Assignee Title
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CN103903985A (zh) * 2012-12-27 2014-07-02 台湾积体电路制造股份有限公司 用于形成具有自对准源极/漏极的FinFET的方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6894326B2 (en) * 2003-06-25 2005-05-17 International Business Machines Corporation High-density finFET integration scheme
US6794256B1 (en) * 2003-08-04 2004-09-21 Advanced Micro Devices Inc. Method for asymmetric spacer formation
US7098477B2 (en) * 2004-04-23 2006-08-29 International Business Machines Corporation Structure and method of manufacturing a finFET device having stacked fins
JP2006012898A (ja) * 2004-06-22 2006-01-12 Toshiba Corp 半導体装置及びその製造方法
US20070298551A1 (en) * 2006-02-10 2007-12-27 Ecole Polytechnique Federale De Lausanne (Epfl) Fabrication of silicon nano wires and gate-all-around MOS devices
US7629603B2 (en) * 2006-06-09 2009-12-08 Intel Corporation Strain-inducing semiconductor regions
EP1892750B1 (en) * 2006-08-23 2012-11-28 Imec Method for doping a fin-based semiconductor device
JP4473889B2 (ja) * 2007-04-26 2010-06-02 株式会社東芝 半導体装置
US7667271B2 (en) 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
US7902000B2 (en) 2008-06-04 2011-03-08 International Business Machines Corporation MugFET with stub source and drain regions
US8222154B2 (en) * 2009-02-10 2012-07-17 International Business Machines Corporation Fin and finFET formation by angled ion implantation
JP2011071235A (ja) * 2009-09-24 2011-04-07 Toshiba Corp 半導体装置及びその製造方法
JP2012049286A (ja) * 2010-08-26 2012-03-08 Sen Corp 半導体装置の製造方法
US8367498B2 (en) * 2010-10-18 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US8871584B2 (en) * 2011-07-27 2014-10-28 Advanced Ion Beam Technology, Inc. Replacement source/drain finFET fabrication
US8685825B2 (en) * 2011-07-27 2014-04-01 Advanced Ion Beam Technology, Inc. Replacement source/drain finFET fabrication
CN103021854B (zh) 2011-09-28 2015-09-16 中国科学院微电子研究所 制作鳍式场效应晶体管的方法以及由此形成的半导体结构
KR101647324B1 (ko) * 2011-09-30 2016-08-10 인텔 코포레이션 비평면 트랜지스터 핀 제조
US9093556B2 (en) * 2012-08-21 2015-07-28 Stmicroelectronics, Inc. Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods
US8748940B1 (en) * 2012-12-17 2014-06-10 Intel Corporation Semiconductor devices with germanium-rich active layers and doped transition layers
KR20150015187A (ko) 2013-07-31 2015-02-10 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9673277B2 (en) 2014-10-20 2017-06-06 Applied Materials, Inc. Methods and apparatus for forming horizontal gate all around device structures

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103238208A (zh) * 2010-12-01 2013-08-07 英特尔公司 硅和硅锗纳米线结构
CN103903985A (zh) * 2012-12-27 2014-07-02 台湾积体电路制造股份有限公司 用于形成具有自对准源极/漏极的FinFET的方法

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