CN107527943A - 功率半导体装置 - Google Patents

功率半导体装置 Download PDF

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CN107527943A
CN107527943A CN201710469418.0A CN201710469418A CN107527943A CN 107527943 A CN107527943 A CN 107527943A CN 201710469418 A CN201710469418 A CN 201710469418A CN 107527943 A CN107527943 A CN 107527943A
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doped region
substrate
region
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doped
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CN107527943B (zh
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金莹俊
禹赫
金台烨
赵汉信
朴泰泳
李珠焕
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Hyundai Mobis Co Ltd
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Hyundai Autron Co Ltd
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Abstract

本公开涉及功率半导体装置。本发明提供了一种半导体装置，其包括：衬底，包括有源区域和边缘区域并且包含掺杂有具有第一导电类型的杂质的半导体；绝缘膜，设置在衬底的边缘区域上；场板图案，设置在绝缘膜上；以及具有第二导电类型的至少一个第一掺杂区域，被埋入衬底的边缘区域中并且在具有平行于衬底的上表面的矢量分量的方向上延伸。

Description

功率半导体装置
相关申请的交叉引用
本申请要求于2016年6月21日在韩国知识产权局提交的韩国专利申请第10-2016-0077605号的优先权和权益，其全部内容通过引证结合于此。
技术领域
本发明涉及功率半导体装置及其制造方法，更具体地，涉及一种绝缘栅双极晶体管(IGBT)装置及其制造方法。
背景技术
绝缘栅双极晶体管(IGBT)通过金属氧化物半导体(MOS)技术和双极物理学的功能的集成而被开发出来。其特点是具有低饱和电压和快速切换功能。其应用范围扩展到无法用晶闸管、双极晶体管、MOSFET等所实现的应用。这也是下一代功率半导体装置，该装置基本上用于广泛应用于电压范围300V以上的高效率的高速电力系统中。自20世纪70年代的功率MOSFET的发展以来，MOSFET已在需要快速切换功能的领域中用作开关装置，而双极晶体管、晶闸管、GTO等已用于在中到高电压中需要大量电流传导的领域中。20世纪80年代初开发的IGBT在输出特性方面具有比双极晶体管更好的电流能力，并且在输入特性方面具有像MOSFET这样的栅极驱动特性，因此，能够以约100KHz的高速切换。因此，IGBT用于从工业到家用电子的广泛应用中，因为这不仅用于装置替代MOSFET、双极晶体管和晶闸管，而且用于创建新的应用系统。
韩国专利申请公开第20140057630号(于2014年5月13日公开，题目为“IGBT及其制造方法(IGBT and manufacturing method thereof)”)是相关的现有技术。
发明内容
本发明的目的是提供一种能够降低电阻并改善短路和击穿电压特性的功率半导体装置及其制造方法。然而，这些问题是说明性的，因此本发明的范围不限于此。
根据本发明一个方面，提供了一种功率半导体装置，用于解决上述问题。功率半导体装置包括：衬底，其包括有源区域(active region)和边缘区域(edge region)并且包含掺杂有具有第一导电类型的杂质的半导体；绝缘膜，其设置在所述衬底的边缘区域上；场板图案(field plate pattern)，其设置在绝缘膜上；以及具有第二导电类型的至少一个第一掺杂区域，被埋入衬底的边缘区域中并且在具有平行于衬底的上表面的矢量分量(vectorcomponent)的方向上延伸。
在功率半导体装置中，具有第二导电类型的第一掺杂区域可以在平行于衬底的上表面的方向上延伸。
功率半导体装置还可以包括：至少一个第二掺杂区域，其在衬底中具有第二导电类型并且具有从衬底的上表面向下延伸的形状，其中，具有第二导电类型的第一掺杂区域可以具有从第二掺杂区域横向突出的形状。
在功率半导体装置中，该第一掺杂区域可以连接到该第二掺杂区域的下端并且横向突出。
在功率半导体装置中，该第一掺杂区域可以设置在该第二掺杂区域的下方并与该第二掺杂区域间隔开。
在功率半导体装置中，具有第二导电类型的至少一个第二掺杂区域可以包括彼此间隔开布置的具有第二导电类型的多个第二掺杂区域，并且具有第二导电类型的至少一个第一掺杂区域可以包括彼此间隔开布置的具有第二导电类型的并且均具有从所述第二掺杂区域横向突出的形状的多个第一掺杂区域。
在功率半导体装置中，多个第二掺杂区域中的一个与第二掺杂区域中的直接相邻的一个之间的间距会随着所述第二掺杂区域被设置为远离所述有源区域而变大。
在功率半导体装置中，在垂直于所述衬底的上表面的方向上的电压分布(voltagedistribution)可以具有电压反向部分(voltage reversal section)，该电压反向部分在平行于衬底的上表面的方向上穿透第一掺杂区域的第一表面与在平行于衬底的上表面的方向上穿透第二掺杂区域并且被设置在第一表面上方使得在第一表面上生成最低电压的第二表面之间。
在功率半导体装置中，通过形成电压反向部分，在包含掺杂有具有第一导电类型的杂质的半导体的衬底与绝缘膜之间的接触面处，在从第二表面到第一表面的方向上可以生成电场。
根据如上所述的本发明的实施例，该功率半导体装置能够防止由于半导体界面处的电荷变化导致的高温反向电压可靠性测试中的特性劣化。当然，本发明的范围不限于这些效果。
附图说明
图1是示出根据本发明的实施例的功率半导体装置的结构的剖面图；
图2是图1中所示的第一掺杂区域和第二掺杂区域的结构的放大图；
图3是示出根据本发明的实施例的在功率半导体装置中沿着穿透第一掺杂区域和第二掺杂区域的方向在与衬底的上表面垂直的方向的电压分布的示图；以及
图4是示出根据本发明的另一实施例的功率半导体装置的结构的剖面图。
<附图标记说明>
10：衬底
18：第二掺杂区域
19：第一掺杂区域
20：主体区域
22：源极区域
28a、28b、28c：栅电极图案
30：层间绝缘膜
36b：场板图案
具体实施方式
在下文中，将参考附图详细描述本发明的实施例。然而，应当理解，本发明不限于下面描述的实施例，而是可以以各种其他形式体现。以下实施例旨在给出本公开的更完整的描述，并且被提供，以便向本领域技术人员充分地传达本公开的范围。此外，为了便于说明，至少一些部件的尺寸可以夸大或缩小。在附图中相同的附图标记表示相同的元件。
在本说明书中，第一导电类型和第二导电类型可以具有相反的导电类型，并且可以分别是n型和p型中的一个。例如，第一导电类型可以是n型并且第二导电类型可以是p型，在附图中示意性地示出这些导电类型。然而，本发明的技术构思不限于此。例如，第一导电类型可以是p型并且第二导电类型可以是n型。
图1是示出根据本发明的实施例的功率半导体装置的结构的剖面图。
参考图1，根据本发明的实施例的功率半导体装置包括衬底10，该衬底包括有源区域A和边缘区域B和C并且包含掺杂有具有第一导电类型的杂质的半导体。
衬底10可以被理解为包括半导体晶片(semiconductor wafer)和外延生长在晶片上的外延层(semiconductor wafer)。半导体晶片可以包括例如轻掺杂有具有第一导电类型的杂质的硅晶片。说明性地，硅晶片中的n型杂质的掺杂浓度可以是例如约1013/cm3至约1016/cm3。考虑到n型杂质的掺杂浓度，衬底100可以被称为N衬底。然而，衬底100的材料、掺杂浓度等不限于此，并且可以变化。
有源区域A包括存在多个有源电池(active cell)的区域，因此，沿垂直方向发生电流导通。在有源区域A中，设置通过在形成在衬底10中的沟槽的内壁上塞满栅极绝缘膜并且用栅电极材料填充沟槽而实施的栅电极28a和28b，；形成在栅电极28a和28b之间的具有第二导电类型的主体区域(body region)20和具有第一导电类型的源极区域22；以及形成在栅电极28a和28b的一侧上的具有第二导电类型的浮动区域14。此外，可以提供形成在衬底10的上表面上的层间绝缘膜30和穿透层间绝缘膜30并接触衬底的表面的第一接触插塞34a。
在层间绝缘膜30上设置具有平坦的上表面的第一金属膜图案36a。第一金属膜图案36a可以接触第一接触插塞34a。第一金属膜图案36a可以具有覆盖有源区域A的上部的大部分的形状。第一金属膜图案36a可以设置为用于引线接合的膜。此外，第一金属膜图案36a可以用作发射电极。
视场光阑区域(field stop region)38可以设置在衬底10的与上表面相反的下表面上。视场光阑区域38可以是掺杂有具有第一导电类型的杂质的区域。例如，视场光阑区域38中的n型杂质的掺杂浓度可以为约1014/cm3至约1018/cm3。考虑到视场光阑区域38中的n型杂质的掺杂浓度，视场光阑区域38可以被称为N0层。集电极区域40可以设置在视场光阑区域38的下方。集电极区域40可以是掺杂有具有第二导电类型的杂质的区域。第二金属膜42可以设置在集电极区域40的下方。第二金属膜42可以设置为集电极。
边缘区域B和C设置成与有源区域A相邻。边缘区域B和C与有源区域A之间的相互位置关系可以变化。例如，边缘区域B和C可以形成为围绕有源区域A的至少一部分。
在边缘区域B和C中，作为与第一金属膜图案36a不同的第二金属膜图案的其中场板图案36b形成在绝缘膜30上的区域可以被称为外围区域B。场板图案36b可以抑制边缘周围的电场浓度并且场板图案36b可以很宽以增加抑制效果。
通过设置场板图案36b，即使结终端延伸区域(junction termination extensionregion)16的宽度w1减小仍可以抑制电场浓度。此外，场板图案36b可以设置为与形成在有源区域A中的整个栅电极28a和28b电连接的栅极总线。场板图案36b可以沿着有源区域A的外围形成。例如，场板图案36b可以形成为闭环的环形，但是形状不限于此。
外围区域B可以设置有设置在形成在衬底10中的沟槽中的连接部分28c。连接部分28c可以连接一个第一栅电极28a和与该一个第一栅电极28a相邻的一个第二栅电极28b。可以设置包括第一栅电极28a、第二栅电极28b和连接部分28c的多个栅电极图案，并且可以重复布置栅电极图案，同时以规则的距离彼此间隔开。当在平面图中看时，栅电极图案可以具有环形。由于连接部分28c具有圆形形状，所以可以抑制连接部分28c中的电场浓度。
结终端延伸(JTE)区域16可以设置在与连接部分28c接触的衬底10上。结终端延伸区域16可以掺杂具有与浮动阱区域(floating well region)14的导电类型相同的导电类型的杂质。结终端延伸区域16可掺杂有具有第二导电类型的高浓度杂质。当在平面图中看时，结终端延伸区域16可以具有围绕有源区域A的外部的环形。
在边缘区域B和C中，所形成的被埋入在衬底10中并且在具有平行于衬底10的上表面的矢量分量的方向上延伸的具有第二导电类型的至少一个第一掺杂区域19的区域可以称为边缘终端区域C。边缘终端区域C是用于支持高击穿电压的区域。
具有第二导电类型的第一掺杂区域19在预定方向上延伸，并且预定方向具有平行于衬底10的上表面的矢量分量。例如，第一掺杂区域19可以在平行于衬底10的方向上延伸。当然，在其他实施例中，第一掺杂区域19可以在与衬底10的上表面形成任意的第一角度(但不是90o)的方向上延伸。
在边缘终端区域C中，根据本发明的实施例的功率半导体装置可以包括在衬底10中具有第二导电类型的至少一个第二掺杂区域18，该第二掺杂区域具有从该衬底10的上表面向下延伸的形状。当在平面图中观察时，第二掺杂区域18可以具有围绕有源区域A的环形。第二掺杂区域18可以掺杂有具有第二导电类型的高浓度杂质。此外，第二掺杂区域18、浮动阱区域14和结终端延伸区域16可以具有相同的杂质浓度和结深度。
上文描述的具有第二导电类型的第一掺杂区域19可以具有从第二掺杂区域18横向突出的形状。在图1中所示的第一掺杂区域19可以连接到第二掺杂区域18的下端并且横向突出。
具有第二导电类型的至少一个第二掺杂区域18可以包括彼此隔开设置的具有第二导电类型的多个第二掺杂区域18，并且具有第二导电类型的至少一个第一掺杂区域18可以包括彼此间隔开设置的具有第二导电类型的多个第一掺杂区域19，其中的每一个具有从第二掺杂区域18横向突出的形状。
在此处，多个第二掺杂区域18中的一个与第二掺杂区域18中的直接相邻的一个之间的间距可以增加，因为其被放置得更远离有源区域A，以便减小装置的边缘周围的电场浓度。第二掺杂区域18a、18b、18c、18d、18e和18f之间的间距d1、d2、d3、d4和d5中的每一个可以参考最接近有源区域A的第二掺杂区域18a和18b之间的间隔依次增大。
可以在边缘终端区域C中的层间绝缘膜30上设置与每个接触插塞34c接触的第三金属膜图案36c。第三金属膜图案36c可以具有连接到至少一个第二掺杂区域18的形状。在平面图中，第三金属膜图案36c可以具有环形。第三金属膜图案36c可以是虚拟图案(dummypattern)，并且实际上可能不作为操作电路进行操作。然而，通过设置第三金属膜图案36c，可以进一步减小电场浓度。
图2是图1所示的第一掺杂区域和第二掺杂区域的结构的放大图，并且图3是示出根据本发明的实施例的在功率半导体装置中沿着穿透第一掺杂区域和第二掺杂区域的方向在与衬底的上表面垂直的方向的电压分布的示图。
参考图1至图3，沿着垂直于衬底10的边缘终端区域C中的上表面的方向的电压分布可以具有电压反向部分，该电压反向部分在与衬底10的上表面平行的方向上穿透第一掺杂区域19的第一表面D与在与衬底10的上表面平行的方向上穿透第二掺杂区域18并且被设置在第一表面D之上使得可以在第一表面D上生成最低电压的第二表面C之间。通过形成电压反向部分，可以在包含掺杂有具有第一导电类型的杂质的半导体的衬底10与绝缘膜30之间的接触面处在从第二表面C到第一表面D的方向上生成电场。
作为本发明的比较例，可以假设功率半导体装置不包括上述第一掺杂区域19。在本发明的比较例中，终端结使用场板图案来提高水平电场效率，但是在场板图案下在从衬底(即，硅)到绝缘膜(即，氧化物)的方向上发生电压差，生成了从氧化硅界面朝向氧化物的垂直电场，并且在可靠性测试过程中在朝向氧化物的方向沿着该电场移动孔，以破坏表面上氢处理的悬挂键，导致界面处硅中的电荷变化，因此导致BV(击穿电压)变化的问题。
另一方面，在根据本发明的实施例的功率半导体装置中，通过引入上述第一掺杂区域19，在第一表面D和第二表面C之间形成电压反向部分，并且可以在氧化硅界面处生成在从第二表面C到第一表面D的方向的电场。因此，通过抑制由孔在界面处的碰撞引起的界面电荷的变化，可以抑制高温反向电压可靠性测试期间由于硅中的悬挂键电荷的波动引起的BV劣化。
图4是示出根据本发明的另一实施例的功率半导体装置的结构的剖面图。
参考图4，第一掺杂区域19可以设置在第二掺杂区域18的下方并与其间隔开。在此处，还在第一表面D与第二表面C之间生成电压反向部分，并且可以在氧化硅界面处生成在从第一表面D到第二表面C的方向的电场。因此，通过抑制由孔在界面处的碰撞引起的界面电荷的变化，可以抑制高温反向电压可靠性测试期间由于硅中的悬挂键电荷的波动引起的BV劣化。
可以参考图1至图3的描述来描述其余部件。
根据本发明的上述实施例，通过在终端结的氧化硅界面处使用结的电位来生成垂直(即，从上到下)的反向电压，使得可以抑制由于界面处硅中的电荷变化导致的在高温反向电压可靠性测试中的特性的劣化。
虽然已经参考示例性实施例描述了本发明，但是应当理解，本发明不限于所公开的示例性实施例，而是与此相反，旨在覆盖包括在所附权利要求的精神和范围内的各种修改和等同布置。因此，本发明的真实范围应由所附权利要求的技术构思确定。

Claims (9)

1.一种功率半导体装置，包括：
衬底，包括有源区域和边缘区域并且包含掺杂有具有第一导电类型的杂质的半导体；
绝缘膜，设置在所述衬底的所述边缘区域上；
场板图案，设置在所述绝缘膜上；以及
具有第二导电类型的至少一个第一掺杂区域，被埋入在所述衬底的所述边缘区域中并且在具有平行于所述衬底的上表面的矢量分量的方向上延伸。
2.根据权利要求1所述的装置，
其中，具有第二导电类型的所述第一掺杂区域在平行于所述衬底的上表面的方向上延伸。
3.根据权利要求1所述的装置，还包括：
至少一个第二掺杂区域，在所述衬底中具有第二导电类型并且具有从所述衬底的上表面向下延伸的形状，
其中，具有第二导电类型的所述第一掺杂区域具有从所述第二掺杂区域横向突出的形状。
4.根据权利要求3所述的装置，
其中，所述第一掺杂区域连接到所述第二掺杂区域的下端并且横向突出。
5.根据权利要求3所述的装置，
其中，所述第一掺杂区域设置在所述第二掺杂区域的下方并且与所述第二掺杂区域间隔开。
6.根据权利要求3至5中任一项所述的装置，
其中，具有第二导电类型的至少一个所述第二掺杂区域包括彼此间隔布置的具有第二导电类型的多个第二掺杂区域，并且
其中，具有第二导电类型的至少一个所述第一掺杂区域包括彼此间隔布置的具有第二导电类型的并且均具有从所述第二掺杂区域横向突出的形状的多个第一掺杂区域。
7.根据权利要求6所述的装置，
其中，所述多个第二掺杂区域中的一个与所述第二掺杂区域中的直接相邻的一个之间的间距随着所述第二掺杂区域被设置为远离所述有源区域而变大。
8.根据权利要求1至5中任一项所述的装置，
其中，在垂直于所述衬底的上表面的方向上的电压分布具有电压反向部分，所述电压反向部分在平行于所述衬底的上表面的方向上穿透所述第一掺杂区域的第一表面与在平行于所述衬底的上表面的方向上穿透所述第二掺杂区域并且被设置在所述第一表面的上方使得在所述第一表面上生成最低电压的第二表面之间。
9.根据权利要求8所述的装置，
其中，通过形成所述电压反向部分，在包含掺杂有具有第一导电类型的杂质的所述半导体的所述衬底与所述绝缘膜之间的接触面处，在从所述第二表面到所述第一表面的方向上生成电场。
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DE102017210255A1 (de) 2017-12-21

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