CN107482057A - 多重外延层的共射共基晶体管 - Google Patents

多重外延层的共射共基晶体管 Download PDF

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CN107482057A
CN107482057A CN201710516502.3A CN201710516502A CN107482057A CN 107482057 A CN107482057 A CN 107482057A CN 201710516502 A CN201710516502 A CN 201710516502A CN 107482057 A CN107482057 A CN 107482057A
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doped layer
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transistor
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CN107482057B (zh
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李斌
彭俊益
王江
苏住裕
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Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
Xiamen Sanan Integrated Circuit Co Ltd
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Abstract

本发明公开了一种多重外延层的共射共基化合物半导体晶体管，包括衬底以及于所述衬底上由下至上依次层叠的第一n型掺杂层、第一p型掺杂层、第二n型掺杂层、第三n型掺杂层、第二p型掺杂层和第四n型掺杂层，由下至上所述各掺杂层的长度依次递减以呈阶梯式排布，且所述各掺杂层裸露的台面上分别设有金属端子，其中第二n型掺杂层和第三n型掺杂层的金属端子电性连接。本发明通过台面堆栈式垂直外延结构实现共射共基结构，结合了底部共发射极器件的击穿电压和顶级共基极器件的击穿电压，大大提高了电压使用范围；相对于传统的水平放置式，可以实现更大的面积效率和成本效益。

Description

多重外延层的共射共基晶体管
技术领域
本发明涉及半导体技术，特别是涉及一种多重外延层的共射共基晶体管。
背景技术
对于化合物半导体器件来说，一般晶体管的外延结构包括于衬底上依次生长的一层第一n型掺杂(作为集电极)、一层p型掺杂(作为基极)和一层第二n型掺杂(作为发射极)。随着共射共基结构被广泛地用于提高模拟或射频电路的双极型晶体管击穿电压或电源电压，通常共射共基结构的执行是两个晶体管横向布局，分别如上述结构形成于衬底上，且衬底于两晶体管之间设置绝缘层，一个晶体管的集电极与另一个晶体管的发射极通过金属连线进行电性连接以实现串联。随着电话通讯，信息化产品等不断发展，集成电路设计朝着轻、薄、短、小的趋势，这种结构一方面占用较多的面积，不利于器件的小型化；另一方面布线多，两晶体管间的连线为复杂的绕线连接，也很难实现器件的薄、小结构。
发明内容
本发明的目的在于克服现有技术的不足，提供了一种多重外延层的共射共基晶体管及其制作方法，可以实现更大的面积效率和成本效益。
本发明的技术方案为：
一种多重外延层的化合物半导体共射共基晶体管，包括衬底以及于所述衬底上由下至上依次层叠的第一n型掺杂层、第一p型掺杂层、第二n型掺杂层、第三n型掺杂层、第二p型掺杂层和第四n型掺杂层，由下至上所述各掺杂层的长度依次递减以呈阶梯式排布，且所述各掺杂层裸露的台面上分别设有金属端子，其中第二n型掺杂层和第三n型掺杂层的金属端子电性连接。
优选的，所述第一n型掺杂层、第一p型掺杂层、第二n型掺杂层依次作为第一晶体管的集电极、基极和发射极，所述第三n型掺杂层、第二p型掺杂层和第四n型掺杂层依次作为第二晶体管的集电极、基极和发射极。
优选的，所述化合物半导体是GaAs、AlGaAs、InGaP或InP。
优选的，所述第一n型掺杂层的掺杂浓度范围为1×1018～5×1018cm-3，第一p型掺杂层的掺杂浓度范围为5×1018～1×1019cm-3，第二n型掺杂层的掺杂浓度范围为1×1016～1×1018cm-3。
优选的，所述第三n型掺杂层的掺杂浓度范围为1×1018～5×1018cm-3、第二p型掺杂层的掺杂浓度范围为5×1018～1×1019cm-3，第四n型掺杂层的掺杂浓度范围为1×1018～5×1018cm-3。
优选的，还包括一蚀刻停止层，所述蚀刻停止层设于所述第二n型掺杂层和第三n型掺杂层之间。
优选的，所述蚀刻停止层的材料为InGaP。
本发明具有以下有益效果：
1.通过台面堆栈式垂直外延结构实现共射共基结构，结合了底部共发射极器件的击穿电压和顶级共基极器件的击穿电压，大大提高了电压使用范围；相对于传统的水平放置式，可以实现更大的面积效率和成本效益。
2.两晶体管的集电极和发射极之间的串联通过单层金属连线即可实现，无需复杂的走线，简化了布线，进一步减少占用面积。
3.两个晶体管可以分别对各掺杂层的厚度、掺杂浓度以及掺杂元素等进行优化，可设计强，以满足更多需求。
附图说明
图1是实施例1的结构示意图；
图2是实施例1的放大电路图；
图3是实施例2的结构示意图。
具体实施方式
以下结合附图及实施例对本发明作进一步详细说明。本发明的各附图仅为示意以更容易了解本发明，其具体比例可依照设计需求进行调整。文中所描述的图形中相对元件的上下关系，在本领域技术人员应能理解是指构件的相对位置而言，因此皆可以翻转而呈现相同的构件，此皆应同属本说明书所揭露的范围。
实施例1
参考图1，一种多重外延层的共射共基晶体管，包括由垂直外延结构形成的串联的两个化合物半导体晶体管，具体，包括衬底1以及于所述衬底1上由下至上依次层叠的第一n型掺杂层2、第一p型掺杂层3、第二n型掺杂层4、第三n型掺杂层5、第二p型掺杂层6和第四n型掺杂层7，由下至上所述各掺杂层的长度依次递减以呈阶梯式排布并形成台面，且所述各掺杂层裸露的台面上分别设金属端子21、31、41、51、61和71，其中第二n型掺杂层4和第三n型掺杂层5的金属端子通过金属连线8进行电性连接。所述第一n型掺杂层2、第一p型掺杂层3、第二n型掺杂层4依次作为第一晶体管的集电极、基极和发射极，所述第三n型掺杂层5、第二p型掺杂层6和第四n型掺杂层7依次作为第二晶体管的集电极、基极和发射极。第一晶体管的发射极和第二晶体管的集电极电性连接，形成两晶体管的串联结构。
具体，第一晶体管和第二晶体管可以分别是GaAs、AlGaAs、InGaP或InP的HBT。其中所述第一n型掺杂层的掺杂浓度范围为1×1018～5×1018cm-3，第一p型掺杂层的掺杂浓度范围为5×1018～1×1019cm-3，第二n型掺杂层的掺杂浓度范围为1×1016～1×1018cm-3。所述第三n型掺杂层的掺杂浓度范围为1×1018～5×1018cm-3、第二p型掺杂层的掺杂浓度范围为5×1018～1×1019cm-3，第四n型掺杂层的掺杂浓度范围为1×1018～5×1018cm-3。在具体设置时，两个晶体管相同功能层的掺杂元素、掺杂浓度及厚度等可以相同，也可以根据需要进行分别优化，以达到较佳效果。此外，在特殊情况下，例如第二n型掺杂层和第三n型掺杂层的掺杂浓度均为1×1018时，一个单一的生长层也可以实现，或者这两个掺杂层允许同时优化，以适用于某些应用。
上述多重外延层的共射共基晶体管的制作方法，是在化合物半导体衬底上通过MOCVD(金属有机化合物化学气相沉积)依次沉积各外延层(E/B/C)，通过半导体制程步骤蚀刻出发射极、集电极和基极以形成台阶型结构，然后在各个外延层的台面上沉积金属以制作金属端子。具体，沉积的金属选自钛、金、铂、镍、钛钨的一种或其组合。
在制作实现第二n型掺杂层4和第三n型掺杂层5电性连接的金属连线8时，由于两层上下设置，在常规的第一金属连线制程中，对金属端子41和51所在区域开窗并沉积金属即可实现。而传统横向设置的两个晶体管，由于具有横向和纵向的距离差，需要做两层金属的跨接才可实现。通过本发明的设置，单层金属走线连接即可实现，大大的简化了布线，进一步减少占用面积。同样的，金属连线8沉积的金属选自钛、金、铂、镍、钛钨的一种或其组合。需要说明的是，图中的金属连线8仅为其连接关系的示意，并不表示其实际结构，其实际结构通过半导体的金属制程实现。
参考图2，本实施例的共射共基结构结构从整体可以看做是具有发射极，集电极和两个基极的四端子器件，结合了底部共发射极器件的击穿电压和顶级共基极器件的击穿电压，大大提高了电压使用范围，具有高击穿电压，优异的RF和功率性能，可以广泛应用于提高模拟或射频电路的双极型晶体管击穿电压或电源电压。
实施例2
参考图3，一种多重外延层的共射共基晶体管，包括由垂直外延结构形成的串联的两个化合物半导体晶体管，具体，包括衬底1以及于所述衬底1上由下至上依次层叠的第一n型掺杂层2、第一p型掺杂层3、第二n型掺杂层4、蚀刻停止层9、第三n型掺杂层5、第二p型掺杂层6和第四n型掺杂层7，由下至上所述各掺杂层的长度依次递减以呈阶梯式排布并形成台面，且所述各掺杂层裸露的台面上分别设金属端子21、31、41、51、61和71，其中第二n型掺杂层4和第三n型掺杂层5的金属端子通过金属连线8进行电性连接。所述第一n型掺杂层2、第一p型掺杂层3、第二n型掺杂层4依次作为第一晶体管的集电极、基极和发射极，所述第三n型掺杂层5、第二p型掺杂层6和第四n型掺杂层7依次作为第二晶体管的集电极、基极和发射极。第一晶体管的发射极和第二晶体管的集电极电性连接，形成两晶体管的串联结构。
本实施例中，通过增加蚀刻停止层9于第二n型掺杂层4和第三n型掺杂层5之间，可以进一步提高后续工艺在蚀刻的可控性。例如，所述晶体管是GaAs晶体管，第二n型掺杂层4和第三n型掺杂层5分别是n型掺杂的GaAs，所述蚀刻停止层9的材料选自InGaP。
上述实施例仅用来进一步说明本发明的一种多重外延层的共射共基晶体管，但本发明并不局限于实施例，凡是依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均落入本发明技术方案的保护范围内。

Claims (7)

1.一种多重外延层的共射共基晶体管，其特征在于：所述共射共基晶体管是化合物半导体晶体管，包括衬底以及于所述衬底上由下至上依次层叠的第一n型掺杂层、第一p型掺杂层、第二n型掺杂层、第三n型掺杂层、第二p型掺杂层和第四n型掺杂层，由下至上所述各掺杂层的长度依次递减以呈阶梯式排布，且所述各掺杂层裸露的台面上分别设有金属端子，其中第二n型掺杂层和第三n型掺杂层的金属端子电性连接。
2.根据权利要求1所述的多重外延层的共射共基晶体管，其特征在于：所述第一n型掺杂层、第一p型掺杂层、第二n型掺杂层依次作为第一晶体管的集电极、基极和发射极，所述第三n型掺杂层、第二p型掺杂层和第四n型掺杂层依次作为第二晶体管的集电极、基极和发射极。
3.根据权利要求1所述的多重外延层的共射共基晶体管，其特征在于：所述化合物半导体是GaAs、AlGaAs、InGaP或InP。
4.根据权利要求1所述的多重外延层的共射共基晶体管，其特征在于：所述第一n型掺杂层的掺杂浓度范围为1×1018～5×1018cm-3，第一p型掺杂层的掺杂浓度范围为5×1018～1×1019cm-3，第二n型掺杂层的掺杂浓度范围为1×1016～1×1018cm-3。
5.根据权利要求1或4所述的多重外延层的共射共基晶体管，其特征在于：所述第三n型掺杂层的掺杂浓度范围为1×1018～5×1018cm-3，第二p型掺杂层的掺杂浓度范围为5×1018～1×1019cm-3，第四n型掺杂层的掺杂浓度范围为1×1018～5×1018cm-3。
6.根据权利要求1所述的多重外延层的共射共基晶体管，其特征在于：还包括一蚀刻停止层，所述蚀刻停止层设于所述第二n型掺杂层和第三n型掺杂层之间。
7.根据权利要求6所述的多重外延层的共射共基晶体管，其特征在于：所述共射共基晶体管是GaAs晶体管，所述蚀刻停止层的材料为InGaP。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108110002A (zh) * 2017-12-18 2018-06-01 西安理工大学 一种互补型SiC双极集成晶体管及其制作方法
WO2019001144A1 (zh) * 2017-06-29 2019-01-03 厦门市三安集成电路有限公司 多重外延层的共射共基晶体管

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750025A (en) * 1981-12-04 1988-06-07 American Telephone And Telegraph Company, At&T Bell Laboratories Depletion stop transistor
CN1738048A (zh) * 2004-08-10 2006-02-22 Atmel德国有限公司 共射共基放大器,其电路以及制造这种放大器布置的方法
CN1965398A (zh) * 2004-07-01 2007-05-16 日本电信电话株式会社 异质结构双极型晶体管
CN101855726A (zh) * 2007-11-09 2010-10-06 克里公司 具有台面结构及包含台面台阶的缓冲层的功率半导体器件

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7098487B2 (en) * 2002-12-27 2006-08-29 General Electric Company Gallium nitride crystal and method of making same
DE102004044835B4 (de) * 2004-09-14 2008-12-11 Atmel Germany Gmbh Integrierte Halbleiter-Kaskodenschaltung für Hochfrequenzanwendungen
DE102004053393B4 (de) * 2004-11-05 2007-01-11 Atmel Germany Gmbh Verfahren zur Herstellung einer vertikal integrierten Kaskodenstruktur und vertikal integrierte Kaskodenstruktur
DE102005009725A1 (de) * 2005-03-03 2006-09-07 Atmel Germany Gmbh Verfahren zur Integration von zwei Bipolartransistoren in einen Halbleiterkörper, Halbleiteranordnung in einem Halbleiterkörper und Kaskodenschaltung
CN107482057B (zh) * 2017-06-29 2019-04-09 厦门市三安集成电路有限公司 多重外延层的共射共基晶体管

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750025A (en) * 1981-12-04 1988-06-07 American Telephone And Telegraph Company, At&T Bell Laboratories Depletion stop transistor
CN1965398A (zh) * 2004-07-01 2007-05-16 日本电信电话株式会社 异质结构双极型晶体管
CN1738048A (zh) * 2004-08-10 2006-02-22 Atmel德国有限公司 共射共基放大器,其电路以及制造这种放大器布置的方法
CN101855726A (zh) * 2007-11-09 2010-10-06 克里公司 具有台面结构及包含台面台阶的缓冲层的功率半导体器件

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019001144A1 (zh) * 2017-06-29 2019-01-03 厦门市三安集成电路有限公司 多重外延层的共射共基晶体管
CN108110002A (zh) * 2017-12-18 2018-06-01 西安理工大学 一种互补型SiC双极集成晶体管及其制作方法
CN108110002B (zh) * 2017-12-18 2020-06-26 西安理工大学 一种互补型SiC双极集成晶体管及其制作方法

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