CN107424999A - Circuit with linear finfet structure - Google Patents

Circuit with linear finfet structure Download PDF

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Publication number
CN107424999A
CN107424999A CN201611023356.2A CN201611023356A CN107424999A CN 107424999 A CN107424999 A CN 107424999A CN 201611023356 A CN201611023356 A CN 201611023356A CN 107424999 A CN107424999 A CN 107424999A
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China
Prior art keywords
transistor
field effect
diffusion
fin
layout
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CN201611023356.2A
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Chinese (zh)
Inventor
S.T.贝克
M.C.斯梅林
D.甘地
J.马利
C.朗贝尔
J.R.匡特
D.福克斯
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Tela Innovations Inc
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Tela Innovations Inc
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Publication of CN107424999A publication Critical patent/CN107424999A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The first transistor has the source region and drain region in the first diffusion fin.The first diffusion fin protrudes from the surface of substrate.The first diffusion fin longitudinally extends to the second end from the first end of the described first diffusion fin in a first direction.Second transistor has the source region and drain region in the second diffusion fin.The second diffusion fin protrudes from the surface of the substrate.The second diffusion fin longitudinally extends to the second end from the first end of the described second diffusion fin in a first direction.The second diffusion fin is oriented to be spaced apart by the described first diffusion fin and with the described first diffusion fin.The first end of the second diffusion fin or second end are positioned in said first direction between the first end of the described first diffusion fin and second end.

Description

Circuit with linear finfet structure
It is on January 13rd, 2013 applying date that the application, which is, Application No. 201380013824.6（PCT/US2013/ 021345）And the divisional application of entitled " circuit with linear finfet structure " application.
Background technology
Known optical lithographic printing is in 193nm optical wavelength and 1.35 numerical apertures（NA）It is reached under immersion system The limit of ability.The minimum straight line resolution capabilities of this equipment are near in the case of approximate 80nm feature to feature spacing Like 40nm.The given structure type that feature less than about 80nm may be directed in given chip level to feature pitch requirements will Seek multiple patterning steps.In addition, as lithographic printing is promoted towards its resolution limit, line end resolution ratio becomes more to choose War property.In semiconductor device layout, the typical metal line spacing in 32nm critical dimensions is approximately 100nm.In order to reach The cost benefit of feature scaling, what 0.7 to 0.75 zoom factor was intended to.To reach about the 0.75 of 22nm critical dimensions Zoom factor ask that about 75nm metal wire spacing, this is less than present single exposing lithographic print system and technology Ability.Exactly the present invention occurs in this case.
The content of the invention
In one embodiment, semiconductor devices includes：Substrate, the first transistor and second transistor.Described first is brilliant Body pipe has the source region and drain region in the first diffusion fin.The first diffusion fin is configured to from the lining The surface at bottom protrudes.The first diffusion fin is configured in a first direction longitudinally from the of the described first diffusion fin One end extends to the second end of the first diffusion fin.The second transistor has the source area in the second diffusion fin Domain and drain region.The second diffusion fin is configured to from the surface of substrate protrusion.The second diffusion fin quilt It is configured to longitudinally extend to the second diffusion fin from the first end of the described second diffusion fin in said first direction The second end.The second diffusion fin is oriented to by the described first diffusion fin and between the described first diffusion fin Separate.In addition, the first end of the second diffusion fin or second end are oriented in said first direction Between the first end of the described first diffusion fin and second end.
In one embodiment, the method for disclosing manufacture semiconductor devices.Methods described includes providing substrate.The side Method also includes：The first transistor is formed over the substrate, to cause the first transistor to have in the first diffusion fin Source region and drain region, and with cause it is described first diffusion fin be formed with from the surface of the substrate protrude, And to cause the first diffusion fin to be formed with a first direction longitudinally from the first of the described first diffusion fin End extends to the second end of the first diffusion fin.Methods described also includes：Second transistor is formed over the substrate, with So that the second transistor has the source region and drain region in the second diffusion fin, and to cause described second Diffusion fin is formed to be protruded from the surface of the substrate, and to cause the second diffusion fin to be formed with described The second end of the second diffusion fin longitudinally is extended to from the first end of the described second diffusion fin on first direction, and To cause the second diffusion fin to be formed on the opening position by the described first diffusion fin and be spread with described first Fin is spaced apart.In addition, the first transistor and the second transistor are formed so that the second diffusion fin First end or the second end are formed in said first direction between the first end of the described first diffusion fin and the second end Opening position.
In one embodiment, data storage device is with the layout for being used to reproduce semiconductor devices being stored thereon Computer-executable program instructions.The data storage device includes：For limiting the first crystal that be formed on substrate The computer program instructions of pipe, to cause the first transistor to be defined as with the source region in the first diffusion fin And drain region, and to cause the first diffusion fin to be defined as from the surface of substrate protrusion, and to cause The first diffusion fin is defined as longitudinally extending to institute from the first end of the described first diffusion fin in a first direction State the second end of the first diffusion fin.The data storage device also includes being used to limit the second crystalline substance that be formed on substrate The computer program instructions of body pipe, to cause the second transistor to be defined as with the source area in the second diffusion fin Domain and drain region, and to cause the second diffusion fin to be defined as from the surface of substrate protrusion, and so that The second diffusion fin is obtained to be defined as：Longitudinally extended in a first direction from the first end of the described second diffusion fin Second end of the second diffusion fin, and to cause the second diffusion fin to be defined as being positioned to be close to described first Diffusion fin and be spaced apart with the described first diffusion fin, and with cause the second diffusion fin be defined as making its One end or its second end are positioned in said first direction between the first end of the described first diffusion fin and the second end.
Brief description of the drawings
Figure 1A and Figure 1B shows the example layout view of finfet field effect transistor according to some embodiments of the invention.
Fig. 1 C show the wherein diffusion fin of the finfet field effect transistor of Figure 1A/1B according to some embodiments of the invention 102 in vertical cross-section A-A more be Pyramid deformation.
Fig. 1 D show according to some embodiments of the invention with the multiple finfet field effect transistors being formed thereon The simplification vertical cross-section of substrate.
Fig. 1 E show that wherein inner fins spacing Ps1 according to some embodiments of the invention is substantially equal between outside fin The diagram of spacing of fin relation away from Ps2.
Fig. 1 F show wherein rational denominator according to some embodiments of the invention（y）Spacing of fin for 2 Fig. 1 E is closed It is the deformation of diagram.
Fig. 1 G show wherein rational denominator according to some embodiments of the invention（y）Spacing of fin for 3 Fig. 1 E is closed It is the deformation of diagram.
Fig. 1 H show wherein inner fins spacing Ps1 according to some embodiments of the invention and outside fin spacing Ps2 not The form more typically changed of same Fig. 1 E spacing of fin relational view.
Fig. 2A shows the exemplary cell for being associated with finfet field effect transistor layout according to some embodiments of the invention.
Fig. 2 B show according to some embodiments of the invention with the two of Fig. 2 D inputs with it is non-（NAND）Circuit corresponding to configuration Figure.
Fig. 2 C show two inputs or non-with Fig. 2 E according to some embodiments of the invention（NOR）Circuit corresponding to configuration Figure.
Fig. 2 D show according to some embodiments of the invention wherein by n-type diffusion material formed diffusion fin 201A and by P-type diffusion material forms diffusion fin 201B Fig. 2A layout.
Fig. 2 E show according to some embodiments of the invention wherein by p-type diffusion material formed diffusion fin 201A and by N-type diffusion material forms diffusion fin 201B Fig. 2A layout.
Fig. 2 F show that wherein gate electrode structure according to some embodiments of the invention makes it respectively hold substantially in unit The deformation of the layout for the Fig. 2A being aligned on top and the bottom of unit.
Fig. 2 G show that wherein contact according to some embodiments of the invention is formed with the bottom at the top of unit and unit Portion is in the deformation of the layout for the Fig. 2A for extending to horizontal local interlinkage portion structure under electrical guide rail from met1 interconnection structures.
Fig. 2 H show Fig. 2A's for wherein using two different diffusion spacings of fin according to some embodiments of the invention The deformation of unit.
Fig. 2 I show being wherein at the top and bottom of unit under electrical guide rail according to some embodiments of the invention Diffusion fin and horizontal local interlinkage portion structure be extended to be used as electrical guide rail met1 interconnection structures whole width The deformation of Fig. 2A of degree layout.
The wherein met1 electrical guide rails that Fig. 3 shows according to some embodiments of the invention be connected to vertical local interlinkage portion with So that met1 electrical guide rails are used as the deformation of Fig. 2A of locally supplied power source layout.
Fig. 4 show according to some embodiments of the invention the met1 interconnection knots that two-dimensionally change are used wherein in unit The deformation of the layout for Fig. 2A that structure route for unit inside.
Fig. 5 shows that wherein met1 electrical guide rails according to some embodiments of the invention are connected to vertical local interlinkage portion simultaneously And the layout for the Fig. 2A being route wherein in unit using the met1 interconnections structure two-dimensionally changed for unit inside Deformation.
Fig. 6 show according to some embodiments of the invention wherein in unit together with the met1 interconnection knots two-dimensionally changed Structure is used together layout fixed, minimum widith, sharing Fig. 2A that local met1 power supplys route for unit inside Deformation.
Fig. 7 show according to some embodiments of the invention have carry unit in hardwired shared locally supplied power source and Fig. 2A of the met1 interconnection structures two-dimensionally changed in global power and the unit for being route inside unit layout Deformation.
The wherein input pin that Fig. 8 A show according to some embodiments of the invention is placed on each diffusion wing of same type Between piece congestion and some of cloth for spreading fin and being used as the example criteria unit of interconnection conductor are route to relax Office.
Fig. 8 B show Fig. 8 A's for wherein using two kinds of different gate electrode spacing according to some embodiments of the invention Deformation.
Fig. 8 C show the circuit diagram of the layout of Fig. 8 A according to some embodiments of the invention.
Fig. 9 A show that wherein diffusion fin according to some embodiments of the invention is used as the example mark of interconnection conductor Quasi- cell layout.
Fig. 9 B show Fig. 9 A of the transistor with three groups of identified cross-coupleds according to some embodiments of the invention Layout.
Fig. 9 C show the circuit diagram of the layout of Fig. 9 A according to some embodiments of the invention.
Figure 10 show according to some embodiments of the invention have be positioned substantially at diffusion fin on grid electricity The example criteria cell layout of pole contact.
Figure 11 shows the exemplary unit layout of realization diffusion fin according to some embodiments of the invention.
Figure 12 A/B show the layout of Figure 11 with minimum widith met1 electrical guide rails according to some embodiments of the invention Deformation.
Figure 13 A/B show according to some embodiments of the invention do not have from local interlinkage portion and gate electrode structure Each arrives the deformation of Figure 12 A/B of met1 contact layout.
Figure 14 A/B show according to some embodiments of the invention include electrical guide rail have with same widths and The deformation of Figure 11 of the minimum widith met1 electrical guide rails of all met1 structures in identical spacing layout.
Figure 15 A/B show according to some embodiments of the invention be filled to be met1 routing infrastructures so that each（y）Position Put the deformation of the layout of Figure 14 A/B with met1 structures.
Figure 16 A/B show according to some embodiments of the invention there is the grid electricity being placed between each p-type diffusion fin The deformation of Figure 11 of pole form touch layout.
Figure 17 A/B show the exemplary unit layout of realization diffusion fin according to some embodiments of the invention.
The wherein contact that Figure 18 A/B show according to some embodiments of the invention is connected to horizontal local interlinkage portion and wherein Horizontal local interlinkage portion is directly connected to the deformation of Figure 17 A/B in vertical local interlinkage portion layout.
Figure 19 A/B show that the wherein not shared electrical guide rail for local interlinkage portion according to some embodiments of the invention does not connect Touch and the deformation of Figure 17 A/B in shared local interlinkage portion layout is not present wherein under electrical guide rail.
Figure 20 A/B show that wherein diffusion fin according to some embodiments of the invention offsets diffusion wing relative to elementary boundary The deformation of Figure 19 A/B of the spacing of piece half layout.
Figure 21 A/B show that the minimum widith electrical guide rail with diffusion fin according to some embodiments of the invention hangs down with negative The deformation of the straight overlapping Figure 20 A/B in local interlinkage portion layout.
Figure 22 A/B show according to some embodiments of the invention have minimum widith electrical guide rail, under electrical guide rail Not shared local interlinkage portion or the cloth for spreading fin and Figure 17 A/B with the greater room between p- fins and n- fins The deformation of office.
Figure 23 A/B show the deformation of the layout of Figure 17 A/B according to some embodiments of the invention.
Figure 24 A/B show the deformation of the layout of Figure 23 A/B according to some embodiments of the invention.
Figure 25 A/B show the layout for Figure 23 A/B that wherein unit according to some embodiments of the invention doubles in height Deformation.
Figure 26 A/B show the exemplary unit layout of realization diffusion fin according to some embodiments of the invention.
Figure 27 A/B show the deformation of the layout of Figure 26 A/B according to some embodiments of the invention.
Figure 28 A/B show the exemplary unit layout of realization diffusion fin according to some embodiments of the invention.
Figure 29 A/B show according to some embodiments of the invention wherein n-type transistor two gate electrode structures it Between there is no the deformation of Figure 28 A/B layout existing for local interlinkage portion structure.
Figure 30 A/B show the exemplary unit layout of realization diffusion fin according to some embodiments of the invention.
Figure 31 A show according to some embodiments of the invention there is the grid electricity placed in the middle substantially between each diffusion fin Pole and the example sdff cell layouts in local interconnection line end gap.
Figure 31 B show according to some embodiments of the invention have substantially occupied between each diffusion fin that circle is delineated In local interlinkage portion line end gap Figure 31 A example sdff cell layouts.
Figure 31 C show according to some embodiments of the invention have wherein that respectively diffusion fin end overlaps each other in the x direction Two adjacent gate electrodes structures between region annotation Figure 31 A and Figure 31 B example sdff cell layouts.
Wherein all contact layer structures that Figure 32 shows according to some embodiments of the invention be placed on each diffusion fin it Between example layout.
Figure 33 and Figure 34 shows that wherein all contact layer structures according to some embodiments of the invention are placed on diffusion wing Example layout on piece.
Figure 35 A/B to Figure 47 A/B show all internal nodes of requirement according to some embodiments of the invention have p-type with The cross-coupling transistors configuration of the transmission grid having in two logical paths of connection between n-type.
Figure 35 C show Figure 35 A/B's to Figure 47 A/B according to some embodiments of the invention and Figure 63 A/B to Figure 67 A/B The circuit diagram of layout.
Figure 48 A/B to Figure 57 A/B show according to some embodiments of the invention have in the logic with larger transistor The cross-coupling transistors configuration of transmission grid in path and the tri-state gates in other paths.
Figure 48 C show the circuit diagram of the layout of Figure 48 A/B to Figure 58 A/B according to some embodiments of the invention.
Figure 58 A/B to Figure 59 A/B show according to some embodiments of the invention have in the logic with more small crystals pipe The cross-coupling transistors configuration of transmission grid in path and the tri-state gates in other paths.
Figure 59 C show the circuit diagram of the layout of Figure 59 A/B according to some embodiments of the invention.
Figure 60 A/B to Figure 62 A/B show the tri-state grid having in two logical paths according to some embodiments of the invention The cross-coupling transistors configuration of pole.
Figure 60 C show Figure 60 A/B's to Figure 62 A/B according to some embodiments of the invention and Figure 68 A/B to Figure 69 A/B The circuit diagram of layout.
Figure 63 A/B to Figure 67 A/B show all internal nodes of requirement according to some embodiments of the invention have p-type with The cross-coupling transistors configuration of the transmission grid having in two logical paths of connection between n-type.
Figure 68 A/B to Figure 69 A/B show the tri-state grid having in two logical paths according to some embodiments of the invention The cross-coupling transistors configuration of pole.
Figure 70 A show the grid limited in limited grid level layout architecture according to some embodiments of the invention Electrode track 70-1A to 70-1E example.
Figure 70 B show many exemplary grid hierarchy characteristics having defined in it according to some embodiments of the invention 7001-7008 Figure 70 A exemplary limited grid level layout architecture.
Figure 71 A/B to Figure 77 A/B show utilization according to some embodiments of the invention based on tri-state and transmit both Many individual example SDFF circuit layouts of the cross-coupled circuit structure of grid.
Figure 71 C show the circuit diagram of the layout of Figure 71 A/B to Figure 77 A/B according to some embodiments of the invention.
Figure 72 C show the circuit diagram of the layout of Figure 72 A/B to Figure 76 A/B according to some embodiments of the invention.
Embodiment
In the following description, a large amount of details are illustrated to provide the thorough understanding of the present invention.However, for ability It is evident that the present invention can be put into practice in the case of these no some or all of details for field technique personnel. In other examples, known processing operation is not described in detail, so as not to can unnecessarily obscure the present invention.Additionally, should Understand, the various circuits and/or spatial layout feature described in the given figure proposed at this can be with being proposed at this Other each figures in described other circuits and/or spatial layout feature combination and be utilized.
" finfet " is by vertical silicon island（That is fin）The transistor of structure.Finfet field effect transistor can also be by Refer to as tri-gate transistor.Term " finfet " transistor as used in this is referred to including upward from substrate below Any transistor configuration of prominent diffusion structure.Figure 1A and Figure 1B shows finfet according to some embodiments of the invention The example layout view of transistor 100.Finfet field effect transistor 100 is built by diffusion fin 102 and grid electrode layer 104. Diffusion fin 102 vertically upward protrudes from substrate 105, as shown in Figure 1B.Gate oxide level 106 is deployed in diffusion fin Between 102 and grid electrode layer 104.Diffusion fin 102 can be doped to form p-type transistor or n-type transistor.Covering The part for spreading the grid electrode layer 104 of fin 102 forms the gate electrode of finfet field effect transistor 100.Therefore, fin field The gate electrode of effect transistor 100 may reside on three sides of diffusion fin 102 or more side, thus from three sides or more Side provides the control of finfet field effect transistor raceway groove, with providing crystal pipe trench from side such as in non-finfet field effect transistor The control in road is opposite.In addition, in certain embodiments, finfet field effect transistor is formed " to turn around（wrap-around）” Transistor, wherein, gate oxide level 106 and grid electrode layer 104 also extend under diffusion fin 102.
It should be understood that the example finfet field effect transistor 100 described in Figure 1A and Figure 1B is to provide in an illustrative manner And do not indicate that mode that finfet field effect transistor wherein as referenced in this can be designed and/or be manufactured appoint What is limited.Specifically, in certain embodiments, fin is spread（Such as 102）It can be formed as including among other things But it is not restricted to Si（Silicon）、SiGe（SiGe）、Ge（Germanium）、InP（Indium phosphorus）、CNT（CNT）、SiNT（Nano-tube）Or it Any combination of different materials layer.Gate oxide level 106 can be formed by many different types of dielectric materials. For example, in certain embodiments, gate oxide level 106 can be formed as the hafnium oxide layer in silicon dioxide layer.Other In embodiment, gate oxide level 106 can be formed by one or more of other dielectric materials.In some embodiments In, grid electrode layer 104 can be formed by any amount of conductive material.For example, in certain embodiments, gate electrode Layer 104 can be formed the TiN covered by polysilicon（Titanium nitride）Or TaN（Tantalum nitride）Film.It is, however, to be understood that In other embodiments, grid electrode layer 104 can be formed by other materials.
In addition, though Figure 1B example diffusion fin 102 is shown as having relative to lining in vertical cross-section A-A The rectangular configuration of the substantially vertical protrusion at bottom 105, it is to be understood that the expansion on semiconductor chip " as manufactured " under state Dissipate the rectangular configuration that fin 102 can have or can not protruded substantially vertically relative to substrate 105.For example, at some In embodiment, in vertical cross-section A-A, the diffusion fin 102 in its " as manufactured " state can have More similar triangle or pyramidal shape.Fig. 1 C show to spread the wing that fin 102 is more taper in vertical cross-section A-A The deformation of gate fin-fet 100.As depicted in Figure 1 C, in certain embodiments, upwardly extended from substrate 105 Each side of diffusion fin 102 can upwardly extend by with the angulation of substrate 105 from substrate, so as to be not orthogonal to substrate 105. It is in addition, it will be appreciated that non-perpendicular as between each side of substrate 105 and the diffusion fin 102 upwardly extended from substrate 105 Relation can be result that is being designed or being manufacture.
Additionally, in certain embodiments, the vertical prominent distance of the diffusion fin 102 on substrate 105 is across semiconductor The region of chip will be substantially equal.However, in other embodiments, some diffusion fins 102 can be designed or make Make as there are multiple different vertical prominent distances on substrate 105 across one or more regions of semiconductor chip.Cause Channel area for finfet field effect transistor 100 is the function that diffusion fin 102 on substrate 105 vertically protrudes distance, So such deformation that the diffusion fin 102 on substrate 105 vertically protrudes distance can be used for adjusting selected fin Field-effect transistor 100 relative to other finfet field effect transistors on semiconductor chip driving intensity.In an example In, the structure of fin 102 can be spread by selective etch during manufacture/overetch to provide the height of diffusion fin 102 Selectivity change.
Fig. 1 D show according to some embodiments of the invention there are many individual finfet field effect transistors for being formed thereon The simplification vertical cross-section of 100 substrate 105.During manufacture finfet field effect transistor 100, a series of cores 107 are formed To promote to form the side spaced walls 109 of each being used in core 107.It is following to promote that side spaced walls 109 are used as mask features Finfet field effect transistor 100 formation.It should be appreciated that core 107, side spaced walls 109 and finfet field effect transistor 100 with Parallel mode is longitudinally extended, i.e., into the page shown in Fig. 1 D.It should be appreciated that core 107 and side spaced walls 109 are finally gone Remove, it is final as in manufactured semiconductor chip/device so as to be not present in.Each finfet field effect transistor 100 is for that This relative spacing is the size of core 107 and side spaced walls 109 and the function at interval.
Fig. 1 D show the core 107 such as with width Wb and spacing Pb.In addition, Fig. 1 D show such as side interval with width Ws Wall 109.Finfet field effect transistor 100 can then be characterized as spacing of fin Ps1, Ps2 with alternating pairs, wherein, Ps1 Be given core 107 each side spaced walls 109 between average centerline to centreline space away from（Ps1 is mentioned as inner fins Spacing）, and wherein Ps2 is average centerline between each adjacent side spaced walls 109 for the core 107 being positioned adjacent to center Line spacing（Ps2 is mentioned as outside fin spacing）.Assuming that the width Wb of core 107, the spacing Pb of core 107 and the width of side spaced walls 109 Uniformity in each of Ws, then inner fins spacing Ps1 be equal to the width Wb of core 107 and the width Ws of side spaced walls 109 it With.Also, outside fin spacing Ps2 subtracts the width Wb of core 107 and the width Ws sums of side spaced walls 109 equal to the spacing Pb of core 107. Therefore, inner fins spacing Ps1 and outside fin spacing Ps2 both will with the spacing Pb of core 107, the width Wb of core 107 and/or Each in the width Ws of side spaced walls 109 changes and changed.It will thus be appreciated that the reference for giving " spacing of fin " Refer to being averaged for given spacing of fin, i.e. spacing of fin PS_ave is equal to inner fins spacing Ps1 and outside fin spacing Ps2 Be averaged, wherein, each in inner fins spacing Ps1 and outside fin spacing Ps2 itself is average.
Fig. 1 E show that wherein inner fins spacing Ps1 according to some embodiments of the invention is substantially equal between outside fin The diagram of spacing of fin relation away from Ps2.Cell height Hc is equal to average spacing of fin and is multiplied by rational, that is, is multiplied by integer x and y Ratio, wherein, x is the molecule of rational, and y is the denominator of rational.Inner fins spacing Ps1 and outside fin spacing wherein In the case of Fig. 1 E equal Ps2, average spacing of fin is equal to each in Ps1 and Ps2.Therefore, cell height Hc is equal to Inner fins spacing Ps1 or outside fin spacing Ps2 are multiplied by rational.It should be appreciated that the denominator of rational（y）Instruction is when many Individual unit is on cell height Hc direction（I.e. on the direction vertical with the longitudinal direction of fin）It is positioned in an abutting manner When obtain fin to the repetition at elementary boundary interval required by many individual units.In addition, when the molecule of rational（x）It is reasonable Several denominators（y）When dividing exactly, top unit border and base unit border can internally spacing of fin Ps1 and/or outside wings Piece spacing Ps2 in alignment with（Indicate）There is identical fin to elementary boundary interval during elementary boundary.
Fig. 1 F show the denominator of wherein rational according to some embodiments of the invention（y）For 2 Fig. 1 E spacing of fin The deformation of relational view.Therefore, in figure 1f, fin repeats each two cell height Hc to elementary boundary interval.In addition, In Fig. 1 F example, the molecule of rational（x）Not by the denominator of rational（y）Divide exactly.Therefore, when inner fins spacing Ps1 and/or outside fin spacing Ps2 in alignment with（Indicate）During elementary boundary, top fin to elementary boundary interval and bottom Fin to elementary boundary interval will be different.
Fig. 1 G show the denominator of wherein rational according to some embodiments of the invention（y）For 3 Fig. 1 E spacing of fin The deformation of relational view.Therefore, in figure 1g, fin repeats every three cell height Hc to elementary boundary interval.In addition, In Fig. 1 G example, the molecule of rational（x）Not by the denominator of rational（y）Divide exactly.Therefore, when inner fins spacing Ps1 and/or outside fin spacing Ps2 in alignment with（Indicate）During elementary boundary, top fin to elementary boundary interval and bottom Fin to elementary boundary interval will be different.It will be appreciated that can be any desired in cell height Hc direction to obtain On fin to elementary boundary interval repetition rate and/or any desired fin to elementary boundary interval specification needed for mode To limit the rational.
Fig. 1 H show wherein inner fins spacing Ps1 according to some embodiments of the invention and outside fin spacing Ps2 not The form more typically changed of same Fig. 1 E spacing of fin relational view.In this example, outside fin spacing Ps2 is more than inside Spacing of fin Ps1.It should be appreciated that cell height Hc, which is equal to average spacing of fin Ps_ave, is multiplied by rational（x/y）, wherein, x and Y is integer.In addition, it will be appreciated that fin to the elementary boundary interval on integer y indicating member height Hc direction repeats frequency Rate.In addition, it will be appreciated that work as rational（x/y）When being reduced to integer value（I.e. when x can be divided exactly by y）, top fin to list First boundary interval and bottom fin to elementary boundary interval can be equal to each other.If rational（x/y）It is not reduced to integer Value, then the different fin phases of order member can be defined in cell library（phasing）Change, wherein, each fin phase change It is corresponding to elementary boundary spaced relationship from the different possibility fins for giving unit.In addition, the possibility for giving unit Fin phase change quantity by equal to the rational of its mathematically most brief form（x/y）Denominator（y）.
As discussed above, Fig. 1 H are shown between the different diffusion fins of two kinds of use according to some embodiments of the invention Away from Ps1 and Ps2.More specifically, in Fig. 1 H, the expansion that each another pair is positioned adjacent to is placed according to smaller spacing Ps1 Dissipate fin structure.In certain embodiments, bigger diffusion spacing of fin Ps2 is about 80 nanometers（nm）, and smaller expansion It is about 60nm to dissipate spacing of fin Ps1.It will be appreciated, however, that in other embodiments, smaller diffusion spacing of fin Ps1 can To be any size, and bigger diffusion spacing of fin Ps2 can be any size.It should be appreciated that some embodiments can be with More than two diffusion spacing of fin is utilized in given unit or block.Also, some embodiments can be in given unit or block It is interior to utilize single diffusion spacing of fin.In addition, it will be appreciated that can with（It is multiple）Spread spacing of fin and retouched at this Any layer of the similar manner stated to form semiconductor devices or part thereof.For example, the local interlinkage portion layer of semiconductor devices or More high-level interconnection layer or part thereof can include with（It is multiple）Spread spacing of fin and it is described herein similar Mode is one or more（It is multiple）The interconnection conductive structure formed in corresponding spacing.
It is attributed to gate oxide limitation and/or source/drain leakage scaling problem, transistor is scaled at 45 nanometers（nm） Slow down under critical dimension.Finfet field effect transistor is subtracted by controlling the raceway groove of finfet field effect transistor from three sides These light problems.The increased electric field of institute in the raceway groove of finfet field effect transistor improves I-on（ON state driving current）With I- off（Leakage current under thresholding）Between relation.Finfet crystal can be used under 22nm critical dimensions and its Pipe.However, being attributed to their vertical protrusion, finfet field effect transistor may have limited put in various circuit layouts Put.For example, in addition to other limited aspects, it is understood that there may be required finfet to finfet minimum interval and/ Or required finfet is to finfet minimum spacing.Herein for utilizing fin in a manner of supplement layout scaling The cell layout of field-effect transistor discloses embodiment.
Unit as referenced in this represents the abstract of logic function, and encapsulate lower level level integrated circuit layout with In realizing logic function.It should be appreciated that given logic function can be represented by multiple element deformations, wherein element deformation can be with By feature sizes, performance and technological compensa tion technology（PCT）Handle to distinguish.For example, multiple lists for giving logic function Member deformation can be by power consumption, signal timing, current leakage, chip area, OPC（Optical proximity correction）、RET（Groove increases Strong technology）Etc. distinguishing.It is also understood that each unit description includes being used for core as required by the logic function for realizing unit Each level of the piece in the associated vertical row of chip（Or layer）In unit layout.More specifically, unit description bag Include the layout of the unit in each level of the chip for extending upward through specific interconnected portion level from substrate level.
Fig. 2A shows the exemplary cell for being associated with finfet field effect transistor layout according to some embodiments of the invention. Cell layout includes diffusion level, in diffusion level, many diffusion fin 201A/201B is limited, for subsequently forming Finfet field effect transistor and associated connection.In certain embodiments, under layout state as drawn, wing is spread Piece 201A/201B is linear shape.Diffusion fin 201A/201B is oriented parallel to each other to cause their length the One direction（x）Upper extension, and with cause their width with first direction（x）Vertical second direction（y）Upper extension.
In certain embodiments, it is all as shown in Figure 2 A, according to such as in second direction（y）Upper measured fixation longitudinal center Line places diffusion fin 201A/201B to longitudinal centre line spacing 203.In this embodiment, spread fin 201A/201B's Spacing 203 can with such as in second direction（y）Upper measured cell height is relevant, can be with to spread spacing of fin 203 It is continuous across elementary boundary.In fig. 2, cell abutment edge represents the list abreast advanced with diffusion fin 201A/201B First border.In certain embodiments, the diffusion for multiple adjacent units will be placed according to common global diffusion spacing of fin Fin, thus promote the chip level manufacture of the diffusion fin in multiple units.
It should be appreciated that other embodiments can be in given unit or among unit set using between multiple diffusion fins Away from.For example, Fig. 2 H show according to some embodiments of the invention wherein using two different spacings of fin 203 and 205 that spread The deformation of Fig. 2A unit.It should be appreciated that in certain embodiments, diffusion fin 201A/201B can be according to one or more Individual longitudinal centre line is placed to longitudinal centre line spacing, or can with longitudinal centre line to longitudinal centre line interval not by The mode of limit is placed.In addition, in certain embodiments, diffusion fin 201A/201B can be placed according to determining deviation, and And it can be vacancy that some spaced positions are placed on diffusion fin.Additionally, in certain embodiments, can be in unit Given diffusion spacing of fin opening position to be spaced apart, it is end-to-end in a manner of place diffusion fin.
In each figure proposed at this, fin is each spread, for example, the diffusion fin 201A/201B in Fig. 2A is n Type diffusion material or p-type diffusion material.In addition, depending on specific unit is realized, the material type for spreading fin can be with Exchange, to obtain different cellular logic functions.Therefore, mark " Class1 _ diffusion " and " type 2_ diffusions " is used in each figure In, to show the different materials type for spreading fin.For example, if Class1 _ diffusion material were n-type material, type 2_ Diffusion material is p-type material, and vice versa.
Cell layout also includes the gate electrode structure 207 of many individual linear shapes.The gate electrode structure of linear shape 207 on direction substantially vertical with diffusion fin 201A/201B（I.e. in second direction（y）On）Extension.When being manufactured, The gate electrode structure 207 of linear shape is bent to form finfet field effect transistor on diffusion fin 201A/201B Gate electrode.It should be appreciated that appropriate gate oxide material is disposed（That is positioning/deposition）In diffusion fin 201A/201B With between the gate electrode structure 207 that is formed above.
In certain embodiments, according to such as between each longitudinal centre line for the gate electrode structure 207 being positioned adjacent to In a first direction（x）Measured fixed railing die opening 209 is gone up to place the gate electrode structure 207 of linear shape.At some In embodiment, grid spacing 209 with as in a first direction（x）Upper measured cell width is relevant, make it that grid spacing can With across elementary boundary but continuous.Therefore, in certain embodiments, can be used for according to public global grid spacing to place The gate electrode structure 207 of multiple adjacent units, thus promote the gate electrode structure 207 of linear shape in multiple units Chip level manufactures.
It should be appreciated that some given in the grid spaced position in unit can be occupied by gate electrode structure 207, and Other grid spaced positions in given unit are left vacancy.In addition, it will be appreciated that can be in given unit along any grid Multiple gate electrode structures 207 are placed in a manner of spaced apart, end-to-end in pole electrode spacing position.It is also understood that at some In embodiment, gate electrode structure 207 can place according to one or more grid spacing, or can be between grid Placed away from unrestricted mode.
Cell layout can also include the local interlinkage portion structure of many horizontal linear shapes（lih）211 and/or many The local interlinkage portion structure of individual veritcal linearity shape（liv）213.Vertical local interlinkage portion structure 213 is oriented and grid electricity Pole structure 207 is parallel.Horizontal local interlinkage portion structure 211 is oriented parallel with diffusion fin 201A/201B.In some implementations In example, the placement of vertical local interlinkage portion structure 213 be defined as according to the half of grid spacing come with gate electrode structure 207 Placement phase out-phase.Therefore, in this embodiment, when neighbouring gate electrode structure 207 is positioned in grid spacing, each Vertical local interlinkage portion structure 213 is placed in the middle between its each adjacent gate electrode structure 207.Therefore, in this embodiment, it is adjacent The vertical local interlinkage portion structure 213 that ground is placed will cause center to center interval to be equal between local grid spacing or global grid Away from, wherein, local grid spacing is applied in given unit, and across multiple unit application overall situation grid spacing.
In certain embodiments, the placement of horizontal local interlinkage portion structure 211 is defined as according to diffusion spacing of fin Half carrys out the placement out-phase with spreading fin 201A/201B.Therefore, in this embodiment, as neighbouring diffusion fin 201A/ When 201B is positioned in diffusion spacing of fin, horizontal local interlinkage portion structure 211 can be in its each neighbouring diffusion fin 201A/ It is placed in the middle between 201B.Therefore, in this embodiment, center will be caused extremely by being adjacent to the horizontal local interlinkage portion structure 211 of placement Middle heart septum is equal to local diffusion spacing of fin or global diffusion spacing of fin, wherein, apply local diffusion in given unit Spacing of fin, and across the global diffusion spacing of fin of multiple unit applications.
In certain embodiments, cell layout also includes the metal 1 of many individual linear shapes（met1）Interconnection structure 215.Met1 interconnections structure 215 is oriented parallel with diffusion fin 201A/201B and hung down with gate electrode structure 207 Directly.In certain embodiments, the placement of met1 interconnections structure 215 be defined as according to diffusion spacing of fin half come with expansion Dissipate fin 201A/201B placement out-phase.Therefore, in this embodiment, although in higher chip level, expand when it is neighbouring When scattered fin is positioned in diffusion spacing of fin, each met1 interconnections structure 215 is placed in the middle between its each neighbouring diffusion fin. Therefore, in this embodiment, being adjacent to the met1 interconnections structure 215 of placement will cause center to center interval to be equal to local expand Spacing of fin or global diffusion spacing of fin are dissipated, wherein local diffusion spacing of fin is applied in given unit, and across multiple The global diffusion spacing of fin of unit application.In certain embodiments, the spacing of met1 interconnections structure 215 and therefore expanding trajectory Spacing is arranged on the single exposure lithographic printing limit（Such as 80nm and 1.35 NA for 193nm wavelength lights）.In the implementation In example, double exposing lithographic printings are not required（Repeatedly pattern）To manufacture met1 interconnections structure 215.It should be appreciated that its Its embodiment can be vertical and parallel with gate electrode structure 207 with diffusion fin 201A/201B using being oriented Met1 interconnections structure 215.
Cell layout also includes many and is defined as each met1 interconnections structure 215 being connected to each local interlinkage Multiple contacts 217 of portion's structure 211/213 and gate electrode structure 207, are thus provided as needed for the logic function for realizing unit Each finfet field effect transistor between electrical connectivity.In certain embodiments, contact 217 is defined to meet single exposure The lithographic printing limit.For example, in certain embodiments, the spatial layout feature that contact 217 is connected to is sufficiently separated, to make it possible to Enough carry out the single exposure manufacture of contact 217.For example, met1 interconnections structure 215 is defined so that：They will accommodate contact The neighbouring line end of met1 interconnections structure 215 that 217 line end contacts 217 with also to accommodate is separated sufficiently to so that each contact Space between 217 is close fully big, enables to carry out the single exposure lithographic printing of contact 217.In some embodiments In, neighbouring contact 217 separates 1.5 times of at least grid spacing each other.It will be appreciated that can be by being sufficiently separated met1 interconnection The relative line end of portion's structure 215 eliminates the expense of line end cutting and associated increased double exposing lithographics printings.Should Work as understanding, depending on the selection made in being handled in manufacture, in certain embodiments, contact separation and line end point on metal level From can be independent of one another.
In certain embodiments, cell layout also includes the metal 2 of many individual linear shapes（met2）Interconnection structure 219.Met2 interconnections structure 219 is oriented parallel with gate electrode 207 and vertical with diffusion fin 201A/201B. Met2 interconnections structure 219 can physically pass through the structure of via 1 as needed for the logic function for realizing unit（v1）221 It is connected to met1 interconnections structure 215.Although Fig. 2A exemplary unit show with 207 vertical longitudinal direction side of gate electrode structure The met1 interconnections structure 219 of formula extension and by it is parallel with gate electrode structure 207 it is longitudinal in a manner of the met2 interconnections that extend Structure 219, it is to be understood that, in other embodiments, met1 interconnections structure 219 and met2 interconnections structure 219 can be by It is defined to upwardly extend surely relative to any of gate electrode structure 207.Determined it should be appreciated that other embodiments can utilize To for it is vertical with gate electrode 207 and with the parallel met2 interconnections structures 219 oriented of diffusion fin 201A/201B.
Fig. 2A unit represents the input gate electrode with substantial registration（That is, in direction（y）On be aligned altogether（co- align）Three gate electrode structures 207 placed in the middle）Multi input gate.Depending on diffusion material type is for Class1 With the distribution of the diffusion fin of type 2, Fig. 2A unit can have different logic functions.For example, Fig. 2 D are shown wherein by n Type diffusion material forms diffusion fin 201A and diffusion fin 201B Fig. 2A layout is formed by p-type diffusion material.Fig. 2 D Layout be two inputs with it is non-（NAND）The layout of door.Fig. 2 B show the two inputs circuit diagram corresponding with non-configuration with Fig. 2 D. Fig. 2 E show to form diffusion fin 201A with p-type diffusion material and diffusion fin 201B Fig. 2A are formed by n-type diffusion material Layout.Fig. 2 E layout is two inputs or non-（NOR）The layout of door.Fig. 2 C show to input with the two of Fig. 2 E or non-configuration is corresponding Circuit diagram.In Fig. 2 B to Fig. 2 E, each in P1 and P2 identifies corresponding p-type transistor（Such as PMOS transistor）, Each in N1 and N2 identifies corresponding n-type transistor（Such as nmos pass transistor）, each mark in A and B is corresponding Input node, and Q mark output marks.It should be appreciated that for p-type transistor, n-type transistor, input node and output section The similar marker of point is also used at this in other figures.
Based on foregoing, it will be appreciated that the material type of fin can be spread by exchanging to change given cell layout Logic function.Therefore, for each cell layout proposed at this, it will be appreciated that n-type material and p can be depended on Section bar material represents multiple logic functions for spreading the distribution of fin.
Fig. 3 to Fig. 7 and Figure 11 to Figure 29 shows the deformation of the layout of Fig. 2A according to some embodiments of the invention.Cause This, depending on n-type material and p-type material are for Class1 _ diffusion and the distribution of type 2_ diffusion diffusion fins, Fig. 3 to Fig. 7 with And each in the units described into Figure 29 of Figure 11 represents two input nand gates or two input nor gates.Fig. 2A to Fig. 7 And each in the cell layout shown in Figure 11 to Figure 29 has following feature：
● multi input gate, wherein, its all input electrode substantial registration,
● local diffusion fin layer power supply,
● global more high-level interconnection power supply,
● horizontal interconnection, for gate electrode to be connected into vertical local interlinkage portion, and by contact placement Bigger flexibility be possibly realized to help to improve the manufacturability of contact layer.
It will be appreciated that each in layout in Fig. 2A to Fig. 7 and Figure 11 to Figure 29 shows identity logic function Difference is realized.Fig. 2A layout shows following feature：
● gate electrode, inputted for two or more, wherein gate electrode substantial registration,
● gate electrode end line space, between each diffusion fin of identical diffusion types,
● gate electrode contact, between each diffusion fin of identical diffusion types,
● Class1 _ diffusion and type 2_ diffusion diffusion fins, for locally supplied power source, i.e. the local interlinkage portion to unit, wherein Met1 is used for more high-level interconnection（It is global）Both power supply, wherein locally supplied power source and global power are common by adjacent unit Enjoy,
● the unit that supplies an electric current in local level of diffusion fin of Class1 _ diffusion and type 2_ diffusions and can be by Predetermined space is connected to more high-level interconnection（Such as met1）, to support multi-chip electric power strategy,
● use level local interlinkage portion is used for the connection of gate electrode,
● the substantially horizontal local interlinkage portion for vertical local interlinkage portion layer being connected to grid electrode layer can be used for deviateing The position of gate electrode contact, thus it is used for increasing the flexibility in contact mask pattern, this can relax potential lithographic plate print Brush problem.
Fig. 2 F show wherein gate electrode structure according to some embodiments of the invention so that it is respectively held substantially as oval It is aligned on the top of unit as indicated by 250 and is aligned as indicated by ellipse 251 on the bottom of unit Fig. 2A layout deformation.
The wherein contact that Fig. 2 G show according to some embodiments of the invention be formed in as indicated by circle 260 The bottom that unit is at the top of unit is under electrical guide rail from met1 interconnection structures and extends to horizontal local interlinkage portion Structure and as circle 261 is indicated at the bottom of unit under electrical guide rail from the extension of met1 interconnections structure To the deformation of Fig. 2A of horizontal local interlinkage portion structure layout.
As mentioned previously, Fig. 2 H show according to some embodiments of the invention wherein use two different diffusions The deformation of Fig. 2A of spacing of fin 203 and 205 unit.
It should be appreciated that the expansion under electrical guide rail is at the top and bottom of unit in this each layout described Dissipate fin and horizontal local interlinkage portion structure in the horizontal direction（x）On continuously extend, be positioned in a row simultaneously so as to service And possibly multiple units in an adjacent row.In order to illustrate this point, Fig. 2 I show according to some embodiments of the invention its In diffusion fin under electrical guide rail is at the top and bottom of unit and horizontal local interlinkage portion structure is extended to and is used as For the deformation of Fig. 2A of the met1 interconnection structures 215A/215B of electrical guide rail whole width layout.It should be appreciated that in electricity Diffusion fin and horizontal local interlinkage portion structure under power guide rail 215A/215B is together with electrical guide rail 215A/215B itself one Rise（x）Continuously extend on direction, as indicated by arrow 270.
The wherein met1 electrical guide rails that Fig. 3 shows according to some embodiments of the invention be connected to vertical local interlinkage portion so that Met1 electrical guide rails be used as locally supplied power source Fig. 2A layout deformation.It should be appreciated that met1 electrical guide rails are based on unit Storehouse requires and can be variable width.As in the case of Fig. 2A layout, Fig. 3 layout is used with substantially right The multi input gate of accurate input electrode.
Fig. 4 show according to some embodiments of the invention the met1 interconnection knots that two-dimensionally change are used wherein in unit The deformation of the layout for Fig. 2A that structure route for unit inside.As in the case of Fig. 2A layout, Fig. 4 layout makes With the input electrode with substantial registration and shared locally supplied power source and the multi input gate of global power.In some realities Apply in example, curving in met1（Two-dimentional change i.e. on met1 direction）Appear in fixed-grid.In some embodiments In, the met1 fixed-grids can include be positioned in it is each diffusion fin between and with it is each diffusion fin it is parallel and extend and The horizontal grid line being positioned in spacing identical with diffusion fin.In addition, in certain embodiments, the met1 fixed-grids can With including vertically extending and being positioned so as to vertical gate ruling placed in the middle in vertical local interlinkage portion with diffusion fin.
The wherein met1 electrical guide rails that Fig. 5 shows according to some embodiments of the invention be connected to vertical local interlinkage portion so that Met1 electrical guide rails be used as locally supplied power source and wherein in unit using the met1 interconnections structure that two-dimensionally changes with Deformation for Fig. 2A of route layout inside unit.As in the case of Fig. 2A layout, Fig. 5 layout uses tool There is the multi input gate of the input electrode of substantial registration.
Fig. 6 show according to some embodiments of the invention wherein in unit together with the met1 interconnection knots two-dimensionally changed Structure is used together the change of the layout for Fig. 2A that fixed, minimum widith shared local met1 power supplys route for unit inside Shape.As in the case of Fig. 2A layout, Fig. 6 layout is patrolled using the multi input of the input electrode with substantial registration Collect door.
Fig. 7 show according to some embodiments of the invention have carry unit in hardwired shared locally supplied power source and Global power and the cloth for Fig. 2A of the met1 interconnection structures two-dimensionally changed in unit of route inside unit The deformation of office.As in the case of Fig. 2A layout, Fig. 7 layout uses the more of the input electrode with substantial registration Input logic gate.
Fig. 8 A show that wherein input pin according to some embodiments of the invention is placed on same type of each diffusion wing Between piece congestion and some of layouts for spreading fin and being used as the example criteria unit of interconnection conductor are route to relax.Figure 8C shows the circuit diagram of the layout for Fig. 8 A for including input pin 8a, 8b, 8c and 8d.Flat normal unit（I.e. non-fin Field effect cell）Typically have and be located at opposite types（I.e. n-type is for p-type）Each diffusion characteristic between or diffusion characteristic with it is adjacent Input pin between nearly electrical guide rail, the higher concentration degree of input pin is thus created in the partial zones of flat unit. As being shown Fig. 8 A, it is defeated to place some by using diffusion fin and between each diffusion fin of identical diffusion types Enter pin, input pin can be spread out in a more uniform manner in bigger area, and the route thus relaxed for unit is gathered around Plug.In addition, as being shown Fig. 8 A, by being selectively removed some gate electrode structures, as shown in region 8001, diffusion Fin layer may be used as substantially horizontal routing layer, to be connected to the transistor being not adjacent to or local interlinkage portion.For example, in area In domain 8001, diffusion fin 8003 is used as horizontal route conductors.
Fig. 8 B show the figure for wherein using two different gate electrode spacing p1 and p2 according to some embodiments of the invention 8A deformation.More specifically, in the fig. 8b, the grid being positioned adjacent to of each another pair is placed according to smaller spacing p2 Electrode structure.In certain embodiments, bigger gate electrode spacing p1 is about 80 nanometers（nm）, and smaller grid electricity Die opening p2 is about 60nm.It should be appreciated that some embodiments can utilize more than two grid in given unit or block Electrode structure spacing.Also, some embodiments can utilize single gate electrode structure spacing in given unit or block.Separately Outside, it will be appreciated that can with（It is multiple）Gate electrode spacing similar manner described herein forms semiconductor device Any layer of part or part thereof.For example, local interlinkage portion layer or more high-level interconnection layer of semiconductor devices or part thereof can With including with（It is multiple）Gate electrode spacing similar manner described herein is one or more（It is multiple）It is right Answer the interconnection conductive structure formed in spacing.
Additionally, in the different layers of semiconductor devices（Also known as level）In conductive structure or part thereof can be positioned In corresponding spacing arrangement, the relation defined in it is present between the conductive structure spacing arrangement of different layers.For example, In certain embodiments, the diffusion fin in fin layer is spread according to the expansion that can include one or more diffusion spacings of fin Dissipate spacing of fin arrangement and be positioned, and metal 1（met1）Met1 interconnections structure in layer according to can including one or More met1 spacing met1 spacing arrangement and be positioned, wherein, spread spacing of fin in it is one or more by having Manage number（x/y）And it is one or more relevant with met1 spacing, wherein, x and y are integer values.In certain embodiments, expand The relation between spacing of fin and met1 spacing of dissipating by from（1/4）Expand to（4/1）In the range of rational limit.
In addition, in certain embodiments, vertical local interlinkage portion structure（liv）Can be according to being substantially equal to gate electrode The vertical local interlinkage portion spacing of spacing and be positioned.In certain embodiments, gate electrode is smaller than 100 nanometers.In addition, In a manner of similar to discussed above for met1 spaced relationships on diffusion spacing of fin, in certain embodiments, Diffusion spacing of fin arrangement can pass through rational（x/y）It is relevant with horizontal local interlinkage portion spacing arrangement, wherein, x and y are whole Numerical value.That is, one or more diffusion spacings of fin can pass through rational（x/y）With one or more horizontal offices Portion's interconnection spacing is relevant.
Fig. 9 A show that wherein diffusion fin according to some embodiments of the invention is used as the example criteria of interconnection conductor Cell layout.Fig. 9 C show the circuit diagram of Fig. 9 A layout.Fig. 9 A example criteria cell layout is included in single track （Such as in gate electrode track 9001）Multiple gate electrode line ends.Fig. 9 B show there is three identified cross-coupleds Transistor set Fig. 9 A layout.The transistor set of the first cross-coupled is identified by paired line cc1a and cc1b.By Paired line cc2a and cc2b identifies the transistor set of the second cross-coupled.Handed over by paired line cc3a and cc3b mark the 3rd Pitch the transistor set of coupling.
Figure 10 show according to some embodiments of the invention have be positioned substantially at diffusion fin on rather than each Spread the example criteria cell layout of the gate electrode contact between fin.Figure 10 example criteria cell layout also illustrates variable The met1 local power structures of width.In Figure 10 example criteria cell layout, contact layer vertically it is each diffusion fin it It is aligned above rather than between them.The technology can cause in the case of no illusory portion's diffusion fin in each diffusion fin Shared on joining edge between structure is possibly realized, there is provided layout more efficiently.It should be appreciated that illusory portion's diffusion wing Piece is the diffusion fin for not forming transistor.Additionally, it should understand, skill of substantially aligned vertically contact layer on diffusion fin Art can change met1 interconnections structure and spread the perpendicular alignmnet relation between fin.
Figure 11 shows the exemplary unit layout of realization diffusion fin according to some embodiments of the invention.In Figure 11 example In layout, grid electrode layer includes following feature：
● substantially linear gate electrode structure,
● the gate electrode structure of three or more linear shapes on grid electrode layer, two therein are illusory portions （dummy）（The gate electrode hierarchical structure of the gate electrode of transistor is not formed）,
● three or more gate electrode structures on grid electrode layer, it has identical vertical dimension（Length）, i.e., In the longitudinal direction with spreading fin（X directions）Identical length on vertical y directions,
● the gate electrode structure on grid electrode layer, substantially with of substantially equal longitudinal centre line between longitudinal centre line Away from and be spaced evenly,
● shared illusory portion's gate electrode structure with the adjacent cells on the left side and/or the right, and
● the illusory portion's gate electrode structure being cut under met1 electrical guide rails.
In Figure 11 example layout, diffusion fin includes following feature：
● the diffusion fin that the spacing according to being substantially identical essentially homogeneously is spaced, diffusion fin may be at grid On, in certain embodiments, diffusion spacing of fin is less than 90nm,
● for one or more diffusion fins of each in p-type and n-type, Figure 11 shows two diffusion fins of n-type Fin is spread with two of p-type, but other embodiments can include any amount of any type of diffusion fin,
● the p-type diffusion fin and n-type diffusion fin, the p-type that other embodiments can have varying number of identical quantity spread Fin spreads fin for n-type
● one or more diffusion fins omitted under electrical guide rail,
● one in the multiple diffusion fins omitted between p-type area section and n-type area section, and
● it is substantially identical width and each diffusion fin of length.
In Figure 11 example layout, local interlinkage portion includes following feature：
● gate electrode and diffusion fin source/drain junction are in different conductor layers, and these different conductor layers It is isolated from each other,
● the substantially linear conductor layer parallel with grid for source drain connection；In certain embodiments, with grid In the identical spacing of pole layer；And in certain embodiments, the linear conductor layer can be offset by the spacing of grid half.
● local interlinkage portion and the plus lap of diffusion fin.
In Figure 11 example layout, more high-level met1 interconnections layer includes following feature：
● p-type spreads the contact gate conductors between fin and n-type diffusion fin,
● the contact of rasterizing in the two directions,
● local interlinkage portion and grid conductor are connected to metal level above by contact,
● substantially linear metal；Metal in spacing；In the case where vertically offseting half spacing with spreading spacing of fin Metal in identical spacing,
● output node pin and input node pin on same layer,
● the wide electrical guide rail on each shared top edge and bottom margin；Electrical guide rail is connected to by adjacent The left side and the right,
● output node and input node in highest metal level；It is positioned between p-type diffusion fin and n-type diffusion fin Contact, and
● the electrical guide rail to the local interlinkage portion shared with the adjacent unit on top and bottom contacts.
Figure 12 A/B show the layout of Figure 11 with minimum widith met1 electrical guide rails according to some embodiments of the invention Deformation.Figure 12 B show to be laid out with Figure 12 A identicals, wherein in order to clear and the form to be merged describes layout.Figure 12A/B example layout also has all met1 for the same widths in identical spacing for including electrical guide rail.In addition, scheming In 12/B layout, met1 is positioned in and diffusion spacing of fin identical（y）Direction opening position.
Figure 13 A/B show according to some embodiments of the invention without from every in local interlinkage portion and gate electrode structure The deformation of one Figure 12 A/B to met1 contact layout.Figure 13 B show to be laid out with Figure 13 A identicals, wherein in order to clear And the form to be merged is laid out to describe.In this embodiment, met1 is formed with electric directly with local interlinkage portion and grid Pole structure connection.In addition, in other embodiments, local interlinkage portion structure, gate electrode structure or local interlinkage portion and grid Both pole electrode structures can be directly connected to met1.
Figure 14 A/B show according to some embodiments of the invention include electrical guide rail have with same widths and The deformation of Figure 11 of the minimum widith met1 electrical guide rails of all met1 structures in identical spacing layout.Figure 14 B show with Figure 14 A identicals are laid out, wherein in order to clear and the form to be merged describes layout.
Figure 15 A/B show according to some embodiments of the invention be filled to be met1 routing infrastructures so that each（y）Position Put the deformation of the layout of Figure 14 A/B with met1 structures.Figure 15 B show to be laid out with Figure 15 A identicals, wherein in order to clear and It is laid out with the form being merged to describe.
Figure 16 A/B show according to some embodiments of the invention there is the grid electricity being placed between each p-type diffusion fin The deformation of Figure 11 of pole form touch layout.Figure 16 B show to be laid out with Figure 16 A identicals, wherein in order to clear and to be closed And form come describe layout.Figure 16 A/B example layout, which also illustrates, to be positioned under met1 electrical guide rails and is connected to VSS/VDD diffusion fin.In addition, diffusion fin VDD/VSS structures be with above and/or following unit is shared.In order to It is easy to illustrate, contact layer not shown in Figure 16 A/B layout.
Figure 17 A/B show the exemplary unit layout of realization diffusion fin according to some embodiments of the invention.Figure 17 B are shown Be laid out with Figure 17 A identicals, wherein in order to clear and the form to be merged describes layout.In Figure 17 A/B example layout In, grid electrode layer includes following feature：
● substantially linear gate electrode structure,
● three or more linear structures on grid electrode layer, therein at least two be illusory portion,
● illusory portion's structure on grid electrode layer is identical vertical dimension（Length）, i.e., in the longitudinal direction with spreading fin （X directions）Equal length on vertical y directions,
● the structure on grid electrode layer for being substantially spaced evenly and/or being opened by equally spacing in the x direction,
● shared illusory portion's structure with the adjacent cells on the left side and/or the right,
● the illusory portion's structure for being plotted as single line and being cut then under electrical guide rail and in the place of needs And gate electrode structure；The gate electrode structure cutting drawn in separating layer；The cutting being shown as in Figure 17 A/B In the case of final result grid electrode layer,
● three or more sections of gate electrode, two in further types of p-type transistor and n-type transistor are controlled,
● in multiple gate electrode structures of identical x position, each is connected to different networks；And it is connected to two Individual different input network.
In Figure 17 A/B example layout, diffusion fin includes following feature：
● the diffusion fin being essentially homogeneously spaced according to the spacing being substantially identical, diffusion fin can be in grid On, in certain embodiments, diffusion spacing of fin is less than 90nm,
● for one or more diffusion fins of each in p-type and n-type,
● the p-type diffusion fin and n-type diffusion fin of identical quantity,
● the shared diffusion fin under electrical guide rail,
● diffusion fin can be omitted or can not be omitted between p-type area section and n-type area section；Figure 17 A/B show own The fin of appearance,
● the width and each diffusion fin of length being substantially identical, there is diffusion fin width measured in y-direction Measured diffusion finned length in the x direction,
● it is plotted as the diffusion fin of continuous lines；The cutting mask of separation, it is plotted as they being separated into each section；Figure 17A/B shows diffusion fin section after releasing；It should be appreciated that in certain embodiments, can be in diffusion fin level Drawn in layout or diffusion fin line end can be formed using cutting mask.
In Figure 17 A/B example layout, local interlinkage portion includes following feature：
● gate electrode and diffusion fin source/drain junction are in different conductor layers；These different conductor layers can be with It is merged during manufacture,
● the substantially linear conductor layer parallel with grid, connected for source drain；In certain embodiments, with grid In layer identical spacing；And in certain embodiments, the linear conductor layer can be offset by the spacing of grid half.
● local interlinkage portion and diffusion fin just, zero or under lap,
● local interlinkage portion is directly connected to diffusion fin source/drain and gate electrode structure,
● the shared local interlinkage portion under electrical guide rail；In certain embodiments, it is convenient to omit under electrical guide rail Local interlinkage portion.
In Figure 17 A/B example layout, more high-level met1 interconnections layer includes following feature：
● the gate electrode structure contact between each diffusion fin,
● one of x directions and y directions or on both rasterizing contact,
● contact by local interlinkage portion and grid conductor be connected on metal level,
● metal sites can be fixed on one of x directions and y directions or both on,
● output node pin and input node pin on same layer,
● the wide electrical guide rail on top and bottom is shared；Electrical guide rail is connected to the left side and the right by adjacent；Extremely Local interlinkage portion electrical guide rail contact be it is shared,
● metal, which can have, to be curved.In certain embodiments, curving in metal interconnection can be in adjacent each diffusion fin Between it is placed in the middle.In addition, in certain embodiments, the perpendicular segment of the metal interconnection extended in y-direction can be with vertical office Portion's interconnection alignment, so as to extend in y-direction along vertical local interlinkage portion and above.
The wherein contact that Figure 18 A/B show according to some embodiments of the invention is connected to horizontal local interlinkage portion and wherein Horizontal local interlinkage portion is directly connected to the deformation of Figure 17 A/B in vertical local interlinkage portion layout.Figure 18 B are shown and Figure 18 A Identical is laid out, wherein in order to clear and the form to be merged describes layout.In Figure 18 A/B layout, expansion is not shown Dissipate the cutting on fin, gate electrode and local interconnection layer.
Figure 19 A/B show that the electrical guide rail do not shared wherein to local interlinkage portion according to some embodiments of the invention contacts And there is no the deformation of Figure 17 A/B in shared local interlinkage portion layout under electrical guide rail wherein.Figure 19 B show and schemed 19A identicals are laid out, wherein, for clarity, being laid out with the form being merged to describe.
Figure 20 A/B show wherein diffusion fin according to some embodiments of the invention relative to elementary boundary by diffusion fin Half spacing is come the deformation of Figure 19 A/B layout that offsets.Figure 20 B show to be laid out with Figure 20 A identicals, wherein in order to clear and with The form being merged is laid out to describe.Figure 20 A/B layout also includes and met1 positions identical diffusion fin position.In addition, The not shared diffusion fin on the top and bottom of unit.Figure 20 A/B also illustrate the top for being positioned at gate electrode and spreading fin Contact in portion.Figure 20 A/B also illustrate that different diffusion fin/local interlinkage portions is overlapping.It should be appreciated that in Figure 20 A/B spy In fixed layout, although horizontal local interlinkage portion lih and vertical local interlinkage portion liv are shown as weighing each other in region 2001 It is folded, but horizontal local interlinkage portion lih and vertical local interlinkage portion liv in region 2001 each other not in contact with.This is right below Also set up in region 2001 in Figure 21 A/B.It should again be understood, however, that in some other layouts, can cause horizontal local Interconnection lih and vertical local interlinkage portion liv are in contact with each other in their opening positions intersected with each other.
Figure 21 A/B show that the minimum widith electrical guide rail with diffusion fin according to some embodiments of the invention hangs down with negative The deformation of the straight overlapping Figure 20 A/B in local interlinkage portion layout.Figure 21 B show to be laid out with Figure 21 A identicals, wherein in order to clear And the form to be merged is laid out to describe.
Figure 22 A/B show according to some embodiments of the invention have minimum widith electrical guide rail without in electrical guide rail Under shared local interlinkage portion or diffusion fin and Figure 17 A/B with larger space between p- fins and n- fins The deformation of layout.Figure 22 B show to be laid out with Figure 22 A identicals, wherein, for clarity, being laid out with the form being merged to describe.
Figure 23 A/B show the deformation of the layout of Figure 17 A/B according to some embodiments of the invention.Figure 23 B are shown and Figure 23 A Identical is laid out, wherein in order to clear and the form to be merged describes layout.Figure 23 A/B layout has following spy Sign：
● unidirectional metal interconnection structure, i.e. the metal interconnection structure of linear shape,
● the shared local interlinkage portion of nothing or fin under electrical guide rail,
● an input pin on highest metal level and another input pin and efferent duct on following metal level Pin,
● the gate electrode contact isolated with local interlinkage portion.
In addition, Figure 23 A/B show the diffusion fin before diffusion fin is cut on left hand edge and right hand edge.
Figure 24 A/B show the deformation of the layout of Figure 23 A/B according to some embodiments of the invention.Figure 24 B are shown and Figure 24 A Identical is laid out, wherein in order to clear and the form to be merged describes layout.Figure 24 A/B layout has following spy Sign：
● less than the diffusion spacing of fin of metal spacing；The diffusion spacing of fin of the half of metal spacing,
● gate electrode and the cutting of local interconnection shown between each diffusion fin；The realization of replacement, which can have, is spreading Cutting on fin cutting；This quantity for spreading fin that will be reduced in one or more transistors,
● an input pin on highest metal level, and another input pin and efferent duct on following metal level Pin,
● more than the interval between the p-type diffusion fin and n-type diffusion fin of minimum value；Expand in p-type diffusion fin section with n-type One or more diffusion fins omitted between fin section are dissipated,
● the gate electrode contact placed on diffusion fin,
● the local interlinkage portion contact placed on diffusion fin, and
● vertical met2 has different skews in the x direction in unit.
Figure 25 A/B show the layout for Figure 23 A/B that wherein unit according to some embodiments of the invention doubles in height Deformation.Figure 25 B show to be laid out with Figure 25 A identicals, wherein in order to clear and the form to be merged describes layout.Figure 25A/B layout includes total twice of the diffusion fin in Figure 23 A/B layout.Show to expand in Figure 25 A/B layout Dissipate fin cutting.
Figure 26 A/B show the exemplary unit layout of realization diffusion fin according to some embodiments of the invention.Figure 26 B are shown Be laid out with Figure 26 A identicals, wherein in order to clear and the form to be merged describes layout.In Figure 26 A/B example layout In, grid electrode layer includes following feature：
● substantially linear gate electrode structure,
● three or more linear structures on grid electrode layer, therein at least two be illusory portion,
● illusory portion's structure on grid electrode layer is identical size,
● be substantially evenly spaced in the x direction and/or grid electrode layer that equally spacing is opened on structure,
● shared illusory portion's structure with the adjacent cells on the left side and/or the right,
● cut illusory portion's structure under electrical guide rail,
● single gate electrode structure controls two or more p-type transistors and n-type transistor, with later manufacture processing in It is separated, to form two or more unique gate electrodes that such as gate electrode structure 2601 and 2603 is described,
● such as by being connected to the gate electrode structure 2601 of input network 2605 and being connected to the grid of input network 2607 What electrode structure 2603 was described is connected to two or more different networks, is connected to two or more difference input nets The gate electrode in identical x position of network, and
● two or more illusory portion's sections in identical x position.
In Figure 26 A/B example layout, diffusion fin includes following feature：
● according to the diffusion fin being essentially homogeneously spaced of of substantially equal spacing, diffusion fin can be on grid, In some embodiments, diffusion spacing of fin is less than 90nm,
● for one or more diffusion fins of each in p-type and n-type,
● the p-type diffusion fin and n-type diffusion fin of identical quantity,
● one or more diffusion fins omitted under electrical guide rail,
● the diffusion fin not being omitted between p-type area section and n-type area section,
● width and each diffusion fin of length are substantially identical, and
● the p-type diffusion fin being positioned between each n-type diffusion fin, vice versa.
In Figure 26 A/B example layout, local interlinkage portion includes following feature：
● gate electrode and diffusion fin source/drain junction are in different conductor layers；These different conductor layers are each other Isolation,
● the substantially linear conductor layer parallel with grid for source drain connection；In certain embodiments, with grid In the layer identical spacing of pole；And in certain embodiments, the linear conductor layer can be offset by the spacing of grid half,
● local interlinkage portion and the plus lap of diffusion fin.
In Figure 26 A/B example layout, more high-level met1 interconnections layer includes following feature：
● the gate electrode structure contact between each diffusion fin,
● one of x directions and y directions or on both rasterizing contact,
● local interlinkage portion and grid conductor are connected to metal level above by contact,
● the conductor of the substantially linear shape on output node,
● output node pin and input node pin on the different layers,
● the electrical guide rail in centre, the relative electrical guide rail at top and bottom；The top electrical guide rail shared and Bottom electrical guide rail；All electrical guide rails are connected to the left side and the right by adjacent, and
● the output node in highest metal level.
Figure 27 A/B show the deformation of the layout of Figure 26 A/B according to some embodiments of the invention.Figure 27 B are shown and Figure 27 A Identical is laid out, wherein in order to clear and the form to be merged describes layout.Figure 27 A/B layout includes following spy Sign：
● grid conductor is plotted as with incised layer（Such as include the incised layer of cutting profile 2701）,
● two grid conductor sections at identical x position, heterogeneous networks are each all connected to, are each all connected to input Network, each control utilizes p-type transistor and n-type transistor constructed by multiple fins, such as He of grid conductor 2703 2705,
● an input pin on highest metal level, another input pin and output pin on following metal level.
Figure 28 A/B show the exemplary unit layout of realization diffusion fin according to some embodiments of the invention.Figure 28 B are shown Be laid out with Figure 28 A identicals, wherein in order to clear and the form to be merged describes layout.In Figure 28 A/B example layout In, grid electrode layer includes following feature：
● substantially linear gate electrode structure,
● three or more linear structures on grid electrode layer, therein at least two be illusory portion,
● three or more gate electrode structures are identical sizes,
● substantially it is evenly spaced in the x direction and/or the structure on grid electrode layer that equally spacing is opened,
● shared illusory portion's structure with the adjacent cells on the left side and/or the right,
● cut illusory portion's structure under electrical guide rail,
It should be appreciated that specific implementation embodiment is depended on, including any figure proposed at this of Figure 28 A/B example layout can Fin is spread with the type 2 for spreading fin with the Class1 for being defined to p-type diffusion fin and be defined to n-type diffusion fin, or The type 2 that can have the Class1 diffusion fin for being defined to n-type diffusion fin and be defined to p-type diffusion fin spreads fin. In Figure 28 A/B example layout, diffusion fin includes following feature：
● according to the diffusion fin being essentially homogeneously spaced for the spacing being substantially identical, diffusion fin can be in grid On, in certain embodiments, diffusion spacing of fin is less than 90nm,
● for one or more diffusion fins of each in p-type and n-type,
● the p-type diffusion fin and n-type diffusion fin of varying number,
● one or more diffusion fins omitted under electrical guide rail,
● one or more diffusion fins omitted between p-type area section and n-type area section,
● it is substantially identical width and each diffusion fin of length.
In Figure 28 A/B example layout, local interlinkage portion includes following feature：
● gate electrode is connected directly from conductor layer with diffusion fin source/drain,
● the substantially linear conductor layer parallel with grid for source drain connection；In certain embodiments, with grid In the layer identical spacing of pole；And in certain embodiments, the linear conductor layer can be offset by the spacing of grid half,
● local interlinkage portion and diffusion fin and zero or under lap of gate electrode structure,
● local interlinkage portion can be built with two steps, first, vertical local interlinkage portion structure, after with horizontal local interlinkage Portion's structure；Each establishment in each step is linear, the set of unidirectional local interlinkage portion structure, and
● alternatively, the local interlinkage portion layer of two separation --- a vertical local interlinkage portion layer and a horizontal part are mutual Company's portion's layer.
In Figure 28 A/B example layout, more high-level met1 interconnections layer includes following feature：
● diffusion fin can be positioned at below electrical guide rail
● one of x directions and y directions or on both rasterizing contact,
● all local interlinkage portions are connected to metal level above by contact, and
● contact can be placed on Anywhere.
Figure 29 A/B show according to some embodiments of the invention wherein n-type transistor two gate electrode structures it Between there is no the deformation of Figure 28 A/B layout existing for local interlinkage portion structure.Figure 29 B show to be laid out with Figure 29 A identicals, wherein In order to clear, the form to be merged is laid out to describe.
Figure 30 A/B show the exemplary unit layout of realization diffusion fin according to some embodiments of the invention.Figure 30 B are shown Be laid out with Figure 30 A identicals, wherein in order to clear and the form to be merged describes layout.In Figure 30 A/B example layout In, grid electrode layer includes following feature：
● substantially linear gate electrode structure,
● three or more linear structures on grid electrode layer, therein at least two be illusory portion,
● three or more gate electrode structures are identical sizes,
● substantially it is evenly spaced in the x direction and/or the structure on grid electrode layer that equally spacing is opened,
● shared illusory portion's structure with the adjacent cells on the left side and/or the right,
● cut illusory portion's structure under electrical guide rail,
In Figure 30 A/B example layout, diffusion fin includes following feature：
● according to the diffusion fin being essentially homogeneously spaced for being substantially identical spacing, diffusion fin can be on grid, In certain embodiments, diffusion spacing of fin is less than 90nm,
● for one or more diffusion fins of each in p-type and n-type,
● the p-type diffusion fin and n-type diffusion fin of identical quantity,
● one or more diffusion fins omitted under electrical guide rail,
● one or more diffusion fins omitted between p-type area section and n-type area section,
● it is substantially identical width and each diffusion fin of length.
In Figure 30 A/B example layout, local interlinkage portion includes following feature：
● gate electrode is connected directly from conductor layer with diffusion fin source/drain,
● the substantially linear conductor layer parallel with grid for source drain connection；In certain embodiments, with grid In the layer identical spacing of pole；And in certain embodiments, the linear conductor layer can be offset by the spacing of grid half,
● local interlinkage portion and diffusion fin and zero or under lap of gate electrode structure,
● local interlinkage portion can be built with two steps, first, vertical local interlinkage portion structure, after with horizontal local interlinkage Portion's structure；Each establishment in each step is linear, the set of unidirectional local interlinkage portion structure, and
● in certain embodiments, vertical local interlinkage portion structure and horizontal local interlinkage portion structure can be formed to hand over each other Pitch and connect, be consequently formed the local interlinkage portion structure two-dimensionally changed（There is the local interlinkage portion structure curved）,
● alternatively, the local interlinkage portion layer of two separation --- a vertical local interlinkage portion layer and a horizontal part are mutual Company's portion's layer.
In Figure 30 A/B example layout, more high-level met1 interconnections layer includes following feature：
● diffusion fin can be positioned at below electrical guide rail
● one of x directions and y directions or on both rasterizing contact,
● met1 interconnections structure is positioned according to gate electrode structure identical spacing,
● all local interlinkage portions are connected to metal level above by contact, and
● contact can be placed on Anywhere.
Figure 31 A show according to some embodiments of the invention there is the grid electricity placed in the middle substantially between each diffusion fin Pole and the example sdff cell layouts in local interconnection line end gap.In Figure 31 A, gate electrode line end gap is hooked with circle Draw.Figure 31 B show the figure with local interlinkage portion line end gap placed in the middle substantially between each diffusion fin that circle is delineated 31A example sdff cell layouts.Based on Figure 31 A to Figure 31 B, it will be appreciated that can with generation unit storehouse framework, wherein, own Gate electrode and perpendicular interconnection portion line end gap are substantially placed in the middle between each diffusion fin.Figure 31 C are shown according to the present invention one The area having between two adjacent gate electrodes structures that wherein respectively diffusion fin end overlaps each other in the x direction of a little embodiments Figure 31 A and Figure 31 B of the annotation in domain 3105 example sdff cell layouts.
Figure 32 to Figure 34 shows three examples of the part of standard cell circuit layout according to some embodiments of the invention. Figure 32 shows the example layout that wherein all contact layer structures are placed between each diffusion fin.Figure 33 and Figure 34 shows wherein institute There is the example layout that contact layer structure is placed on diffusion fin.In Figure 32 example, gate electrode in some instances Line end gap is substantially placed in the middle on diffusion fin, as circle 3201 marks, and in some instances, grid electricity Polar curve splaying is substantially placed in the middle between each diffusion fin, as circle 3203 marks.By using in diffusion fin On place the unit structures of all contact layer structures, all gate electrode line end gaps can substantially each diffusion fin it Between it is placed in the middle, as the circle 3301 in Figure 33 and Figure 34 is marked.A benefit in this is gate electrode line end gap Entirely on constant spacing.From the viewpoint of manufacture, gate electrode line end gap is placed in the middle on each diffusion fin or each It is inessential between two parties between diffusion fin.However, it is vital that each gate electrode line end gap, which does not mix, such as exist In Figure 32 example like that.So that gate electrode line end gap will all be caused in identical spacing it is more cheap, more reliable or this Gate electrode manufacture processing both with both.
Figure 35 A to Figure 69 A show that displaying wherein can realize cross-coupling transistors using finfet field effect transistor The various cell layouts of the example of the different modes of configuration.In two inputoutput multiplexer circuits（MUX2）In the case of Figure 35 A are shown Cross-coupled to Figure 69 A is laid out.Figure 35 C show Figure 35 A/B to Figure 47 A/B and figure according to some embodiments of the invention The circuit diagram of 63A/B to Figure 67 A/B layout.Figure 48 C show that Figure 48 A/B according to some embodiments of the invention extremely scheme The circuit diagram of 58A/B layout.Figure 59 C show that the circuit of the layout of Figure 59 A/B according to some embodiments of the invention shows It is intended to.Figure 60 C show the cloth of Figure 60 A/B to Figure 62 A/B and Figure 68 A/B to Figure 69 A/B according to some embodiments of the invention The circuit diagram of office.Figure 71 C show that the circuit of the layout of Figure 71 A/B and Figure 77 A/B according to some embodiments of the invention shows It is intended to.Figure 72 C show the circuit diagram of the layout of Figure 72 A/B to Figure 76 A/B according to some embodiments of the invention.On the left side Transistor on edge and right hand edge is added to cross-coupled, to reach MUX2 features.For with cross-coupled circuit For other functions, these can be different.Figure 35 B to Figure 69 B are shown respectively to be laid out with Figure 35 A to Figure 69 A identicals, its In in order to clear and the form to be merged describes layout, and electricity is wherein identified based on the circuit diagram of cell layout The node on road.In addition, the transistor for identifying cross-coupled in Figure 35 A to Figure 69 A with cc2 by line cc1 connects.
Figure 35 A/B to Figure 47 A/B and Figure 63 A/B to Figure 67 A/B show to require that all internal nodes have in p-type and n The cross-coupling transistors configuration of the transmission grid having in two logical paths of connection between type.Figure 48 A/B extremely scheme 57A/B is shown with the transmission grid in the logical path with bigger transistor and the tri-state gates in other paths Cross-coupling transistors configuration.Tri-state gates do not require the connection between the p-type diffusion on internal node and n-type diffusion.
Figure 58 A/B to Figure 59 A/B show with the more logical path of small crystals pipe transmission grid and The cross-coupling transistors configuration of tri-state gates in other paths.Tri-state gates do not require p-type diffusion and n on internal node Connection between type diffusion.
Figure 60 A/B to Figure 62 A/B and Figure 68 A/B to Figure 69 A/B show there is tri-state gates in two logical paths Cross-coupling transistors configuration.
Figure 63 A/B to Figure 69 A/B show the list of many individual p-type diffusion fins with the quantity for being equal to n-type diffusion fin Member layout.Some in other Figure 35 A/B to Figure 62 A/B show that the p-type of the quantity not equal to n-type diffusion fin spreads fin The cell layout of quantity.
Figure 40 A/B show to utilize the cell layout of the more tight spacing between horizontal/vertical local interlinkage portion structure.Figure 37A/B, Figure 45 A/B and Figure 49 A/B show cell layout's example using the greater distance between each diffusion fin.Figure 63 A/B Cell layout's example using the more tight spacing between each diffusion fin is shown to Figure 69 A/B.Figure 43 A/B and Figure 44 A/B show Go out and utilize the cell layout's example for spreading fin as wiring.
Figure 35 A/B to Figure 41 A/B, Figure 48 A/B to Figure 65 A/B and Figure 68 A/B to Figure 69 A/B are shown in no splitting bar The cell layout's example realized in the case of pole using intensive gate electrode structure.Figure 42 A/B to Figure 47 A/B and Figure 66 A/B The cell layout's example for showing to utilize the splitting grid with less wiring and bigger transistor size to realize to Figure 67 A/B.
Figure 35 A/B to Figure 69 A/B show unit cloth of the displaying for many individual various wirings examples of various cell layouts Office's example.Figure 35 A/B to Figure 69 A/B show that displaying includes the complete filling of grid electrode layer of the extension of gate electrode end cap Using and illusory portion's structure in grid electrode layer in the conceived case the cell layout's example used.Figure 35 A/B Some into the cell layout shown in Figure 69 A/B show not cut at the top and bottom during manufacture is handled in unit In the case of（I.e. before mask operation is cut）Illusory portion's gate electrode Rotating fields example.Some in cell layout （Such as Figure 53 A/B to Figure 55 A/B and Figure 66 A/B）The exemplary unit for showing wherein to omit electrical bus is laid out.
Figure 35 A/B to Figure 69 A/B these cross-coupling transistors configuration is included in the group on each layer and in each layer Formed structure is closed, and many cell layouts feature above-mentioned can be employed independently of one another.It should be appreciated that Figure 35 A/B to Figure 69 A/B cell layout shows to configure by using the cross-coupling transistors of finfet and completed Content example, and never represent it is all include possibility cell layouts configuration set.Figure 35 A/B's to Figure 69 A/B Any feature shown in various cell layout's examples can be combined to generate additional cell layout.
The technology that optical resolution is not enough to solve line pattern for which will be divided directly using some form of spacing. Spacing division can be self aligned, pass through multiple step of exposure using spaced walls, or with accessible resolution ratio.Example Such as, for ArF excimer lasers scanner that the water logging using final lens and a part of wafer to be exposed does not have and Speech, optical resolution are restricted to ~ 40nm.This is with the wavelength for 193nm and the 0.28 of 1.35 effective numerical aperture K1 values are corresponding.Divided for diffusion fin layer and grid electrode layer and using spacing（Such as spaced walls double patternings, intervals Wall four patternings, multiexposure, multiple exposure optical lithography-etching-optical lithography-etchings etc..）The other layers formed For, even if being directed to conductive structure（It is directed to line）Utilize proportional spacing（Longitudinal centre line is to longitudinal centre line spacing）To complete Layout, so manufactured conductive structure may also be attributed to processing variation（It is multiple such as on chip（Such as two, four Deng ...）Spacing terminates）And slightly deviate from target and terminate.
Using autoregistration spaced walls method or multiple Lithography exposures, spacing division can be employed repeatedly, such as two Secondary spacing divides, the spacing division of 4 times.It has been reported that the spacing division of 4 times is used to reach about 11nm line/sky Between.One limitation of spacing division is that resulting line pattern may have slightly different spacing in pattern.For 2 times For spacing division, it means that the group of two lines will have a spacing, and the groups of next two lines may have slightly different Spacing, the groups of next two lines will have with first group of identical spacing etc..The result of chip on being completed will be meaning Figure is in the line that will terminate in uniform, fixed spacing but in two or four or other multiple spacing.For between autoregistration For next door, initial cored wire pattern will be plotted in fixed, uniform spacing.For multiexposure, multiple exposure, exposure every time will With the line being plotted in uniformly fixed spacing.Between the introduced non-homogeneous spacing of spacing division processing may be at finally Away from 10% or smaller magnitude on.For example, for 50nm final goal spacing, the spacing of the group of each two lines Possible difference is less than 5nm.
Limited grid level layout architecture
It can be realized in limited grid level layout architecture and be associated with finfet field effect transistor as discussed above Various circuit layouts.For grid level, many parallel dummy lines are defined as extending across layout.These are parallel Dummy line be mentioned as gate electrode track because they are used for the gate electrode that various transistors are indicated in layout Place.In certain embodiments, the parallel virtual line of gate electrode track is formed by equal to specified gate electrode spacing Perpendicular separation therebetween is limited.Therefore, placement of the gate electrode section on gate electrode track and specified grid electricity Die opening is corresponding.In another embodiment, gate electrode track can be by more than or equal to specified gate electrode spacing Variable spacing and be spaced apart.
Figure 70 A show the grid limited in limited grid level layout architecture according to some embodiments of the invention Electrode track 70-1A to 70-1E example.Gate electrode rail is formed across the parallel virtual line that the grid hierarchical layout of chip extends Road 70-1A is to 70-1E, wherein perpendicular separation therebetween is equal to specified gate electrode spacing 70-3.
In limited grid level layout architecture, grid hierarchy characteristic be laid out raceway groove on given gate electrode track and It is defined, so as to extend between the adjacent each gate electrode track of given gate electrode track.For example, respectively about grid Electrode track 70-1A to 70-1E is laid out raceway groove 70-5A to 70-5E to limit grid hierarchy characteristic.It should be appreciated that each grid Electrode track has corresponding grid hierarchy characteristic layout raceway groove.In addition, for adjacent with the edge of predetermined arrangement space（Such as It is adjacent with elementary boundary）And for the gate electrode track positioned, corresponding grid hierarchy characteristic layout raceway groove extension just looks like Dummy gate electrode track outside predetermined arrangement space be present, as grid hierarchy characteristic layout raceway groove 70-5A and 70-5E scheme Solution is such.It is also understood that each grid hierarchy characteristic layout raceway groove is defined as along its corresponding gate electrode track Whole length and extend.Therefore, each grid hierarchy characteristic layout raceway groove is defined as in the core associated by grid hierarchical layout Across grid hierarchical layout in the part of piece and extend.
In limited grid level layout architecture, it is defined with the grid hierarchy characteristic of given gate electrode track association It is laid out with the grid hierarchy characteristic of given gate electrode track association in raceway groove.The grid hierarchy characteristic adjoined can include limit Determine transistor（Finfet field effect transistor i.e. disclosed herein）Gate electrode part and do not limit the grid of transistor Both parts of pole electrode.Therefore, the grid hierarchy characteristic adjoined can be in diffusion zone（Spread fin）With it is following Extend on both dielectric regions of chip level.
In certain embodiments, form each of the grid hierarchy characteristic of the gate electrode of transistor and be partly positioned as base It is placed in the middle on given gate electrode track on this.In addition, in this embodiment, the grid layer of the gate electrode of transistor is not formed The part of level feature can be positioned in be laid out in raceway groove with the grid hierarchy characteristic of given gate electrode track association.Therefore, As long as the gate electrode portion of given grid hierarchy characteristic is in gate electrode corresponding with given grid hierarchy characteristic layout raceway groove It is placed in the middle on track, as long as and given grid hierarchy characteristic obedience and other grid levels in neighboring gates hierarchical layout raceway groove The relevant design rule space requirement of feature, given grid hierarchy characteristic can are substantially limited to given grid hierarchy characteristic From anywhere in being laid out in raceway groove.Additionally, it is laid out with the grid hierarchy characteristic of adjacent gate electrodes track association in raceway groove Forbid being physically contacted between each grid hierarchy characteristic limited.
Figure 70 B show that many exemplary grid levels having defined in it according to some embodiments of the invention are special Levy 7001-7008 Figure 70 A exemplary limited grid level layout architecture.Grid hierarchy characteristic 7001 is limited at and grid In the grid hierarchy characteristic layout raceway groove 70-5A of pole electrode track 70-1A associations.The gate electrode portion of grid hierarchy characteristic 7001 Divide placed in the middle substantially on gate electrode track 70-1A.In addition, the non-gate electrode portion of grid hierarchy characteristic 7001 utilizes phase Adjacent grid hierarchy characteristic is laid out the interior grid hierarchy characteristics 7002 and 7003 limited of raceway groove 70-5B to keep design rule interval It is required that.Similarly, grid hierarchy characteristic 7002-7008 is limited in their corresponding grid hierarchy characteristic layout raceway groove, And cause its gate electrode portion substantially in gate electrode rail corresponding to its corresponding grid hierarchy characteristic layout raceway groove It is placed in the middle on road.Additionally, it should understand, each in grid hierarchy characteristic 7002-7008 utilizes neighboring gates hierarchy characteristic cloth The grid hierarchy characteristic that is limited keeps design rule space requirement in office's raceway groove, and avoids and neighboring gates hierarchy characteristic The physical contact of any another grid hierarchy characteristic limited in layout raceway groove.
Gate electrode with diffusion structure（I.e. on diffusion fin）The corresponding grid hierarchy characteristic of extension Part is corresponding, wherein, corresponding grid hierarchy characteristic is limited in its entirety in grid hierarchy characteristic layout raceway groove.Often Individual grid hierarchy characteristic is not physically contacting with another grid layer for being limited in adjacent grid hierarchy characteristic layout raceway groove It is limited in the case of level feature in its grid hierarchy characteristic layout raceway groove.Example grid hierarchy characteristic such as Figure 70 B is laid out Raceway groove 70-5A to 70-5E is illustrated like that, each grid hierarchy characteristic layout raceway groove and given gate electrode track association, and And with along given gate electrode track and in each relative direction from given gate electrode track to outside layout border Immediate the adjacent gate electrodes track or dummy gate electrode track in portion and outwards the layout areas that vertically extends is corresponding.
Some grid hierarchy characteristics can have limited at any amount of position along its length one or more Multiple contact head parts.Height and the width that the contact head part of given grid hierarchy characteristic is defined as having enough sizes with Accommodate the section of the grid hierarchy characteristic of gate contacting structure.In this example, in the grid electricity with given grid hierarchy characteristic Limit " width " across substrate on the vertical direction of pole orbit, and put down in the gate electrode track with given grid hierarchy characteristic Limited " height " across substrate on capable direction.Depending on the orientation of the grid hierarchy characteristic in unit, grid hierarchy characteristic are wide Degree and height can be corresponding with cell width W and cell height H or not corresponded to.It will be appreciated that when seen from above, grid layer The contact head of level feature can be limited substantially by any topological shape including square and rectangle.In addition, depend on cloth Office requires and circuit design, the given contact head part of grid hierarchy characteristic can connect with and without the grid limited thereon Touch.
The grid level of some embodiments disclosed herein is defined as limited grid level, as discussed above that Sample.The gate electrode of some formation transistor devices in grid hierarchy characteristic.Other in grid hierarchy characteristic can be formed The conductive section extended between two points in grid level.It is in addition, other on integrated circuit in grid hierarchy characteristic Operation can be non-functional.It should be appreciated that regardless of function, each in grid hierarchy characteristic is not connecing physically It is defined as in the case of touching the other grid hierarchy characteristics limited using neighboring gates hierarchy characteristic layout raceway groove in its phase Across grid level extension in the grid hierarchy characteristic layout raceway groove answered.
In certain embodiments, grid hierarchy characteristic, which is defined as offer, can be directed in manufacture and design treatment accurately The controlled topological shape for the limited quantity that ground is predicted and optimized interacts to shape lithographic printing.In this embodiment, grid Pole hierarchy characteristic is defined as avoiding being introduced into can not be with high probability come the unfavorable of the cloth intra-office that calculates to a nicety and mitigate The topological shape of lithographic printing interaction is to shape space relation.It will be appreciated, however, that when corresponding lithographic printing interaction is predictable And when can manage, the change in direction of the grid hierarchy characteristic in its grid hierarchical layout raceway groove is acceptable.
It should be appreciated that regardless of function, each in grid hierarchy characteristic is defined so that：Do not utilizing non-grid In the case of the hierarchy characteristic of pole, along given gate electrode track grid hierarchy characteristic and be not adapted in grid level It is directly connected to another grid hierarchy characteristic limited along different gate electrode tracks.In addition, by can be higher One or more non-grid hierarchy characteristics limited in interconnection level（I.e. by one or more above grid level Interconnection level）Or made and different grid electricity in a manner of the local interlinkage portion feature at grid level or under it Each connection between each grid hierarchy characteristic placed in the different grid hierarchical layout raceway grooves of pole orbit association.
Figure 71 A/B to Figure 77 A/B show that utilization according to some embodiments of the invention is based on tri-state gates and transmission grid Many individual example SDFF circuit layouts of the cross-coupled circuit structure of both.Figure 71 C are shown according to some implementations of the present invention The circuit diagram for Figure 71 A/B and Figure 77 A/B of example.Figure 72 C show according to some embodiments of the invention be used for scheme 73A/B to Figure 76 A/B circuit diagram.Figure 71 B to Figure 77 B are shown respectively to be laid out with Figure 71 A to Figure 77 A identicals, wherein In order to clear, the form to be merged is laid out to describe, and wherein based on the circuit diagram of cell layout come marker circuit Node.Figure 71 A/B to Figure 77 A/B example SDFF circuit layouts include following feature：
1. grid conductor：
A. substantially uniform grid conductor spaced apart.
B. the uniform grid conductor line end gap formed using mask is cut, with big grid conductor line end dwell set Close to avoid local interlinkage portion, or if there is enough spaces to permit not requiring between the bigger grid conductor line end of cutting Gap.
C. it is used as wiring in some instances to reduce the use of metal（More high-level interconnection is reduced to use）One A little grid conductors.
2. spread fin：
A. the diffusion fin being essentially homogeneously spaced.
B. the diffusion fin omitted between p-type and n-type and in the cell edges of top and bottom.
C. diffusion fin width can change to spatial relationship, or can showing with such as Figure 71 A/B to Figure 77 A/B The relation being substantially identical described in example.
3. local interlinkage portion：
A. local interlinkage portion structure can be directly connected to diffusion fin and grid conductor.
B. local interlinkage portion structure can be connected to metal 1 by contact layer（Met1 or M1）.
C. can be manufactured using separate design layer（Manufactured using separation mask layer）Such as figure by way of example Horizontal local interlinkage portion structure and vertical local interlinkage portion structure shown in 76A/B.
D. horizontal local interlinkage portion structure and vertical local interlinkage portion structure can be located on the same layer（I.e. same mask On layer）, as shown in Figure 71 A/B to Figure 75 A/B and Figure 77 A/B example.In addition, during manufacture, can be in two unique steps In rapid or in a single step manufacture level local interlinkage portion structure and vertical local interlinkage portion structure.
E. local interlinkage portion structure can have with diffusion fin and grid conductor just, zero or under lap.
F. vertical local interlinkage portion can be utilized from half spacing of grid conductor skew and in similar to grid conductor Spacing on.
4. contact：
A. contact can be defined as local interlinkage portion structure being connected to metal 1（Met1 or M1）.
B. local interlinkage portion structure can have in contact just, zero or under lap.
C. metal 1（Met1 or M1）Can have in contact just, zero or under lap.
5. metal 2（Met2 or M2）
A. in certain embodiments, the structure of metal 2 can be unidirectional, i.e. linear shape.
B. the structure of metal 2 can be in level（x）It is and/or vertical（y）Side upwardly extends.
Among other things, Figure 71 A/B example SDFF circuit layouts show following feature：
● metal 2 is not used to internal wiring.
● metal 2 is used for electrical guide rail.
● utilize tri-state gates cross-coupling transistors structure and transmission grid cross-coupling transistors structure.
● local interlinkage portion structure is in level（x）Direction and vertical（y）Both directions are upper to be extended.
● some grid conductors are used as wiring, and do not form the gate electrode of transistor.
● grid conductor cutting is provided in various positions and combination.
● grid conductor cutting is uniform in size.
● gate conductor layer is complete filling of, i.e., at least one grid conductor is positioned in unit each available grid and led At body spaced position.
Wherein, Figure 72 A/B example SDFF circuit layouts show following feature：
● the structure of metal 2 is vertical（y）It is used for internal wiring on direction.
● the circuit layout more more dense than Figure 71 A/B example.
● utilize tri-state gates cross-coupling transistors structure and transmission both grid cross-coupling transistors structures.
● gate conductor layer is complete filling of, i.e., at least one grid conductor is positioned in unit each available grid and led At body spaced position.
● show that grid conductor is cut.
● cut in various combinations and/or position using substantially uniform grid conductor, to optimize layout.
Figure 73 A/B example SDFF circuit layouts are shown for vertical（Y directions）Wiring uses 2 layers of grid conductor and metal SDFF circuits form.Figure 74 A/B example SDFF circuit layouts show to orient for internal wiring use level（I.e. in x On direction）The structure of metal 2 SDFF circuits form.Figure 75 A/B example SDFF circuit layouts show to be directed to internal wiring Reuse horizontal orientation（I.e. in the x direction）The structure of metal 2 SDFF circuits alternative forms.Figure 76 A/B example SDFF circuit layouts show the deformation of Figure 72 A/B layout, wherein horizontal local interlinkage portion and vertical local interlinkage portion are used as dividing From conductor, to allow to remove the conductor of interior metal 2.Figure 77 A/B example SDFF circuit layouts show diagram to limit circuit Structure is so that metal 2 uses the part SDFF cloth for minimizing and causing the maximized substitute mode of transistor density Office.
Based on the circuit layout and description provided at this it should be appreciated that in certain embodiments, can utilize following It is one or more in feature：
● the separating distance between each diffusion fin end that is being aligned altogether and being positioned adjacent to（Spread fin cutting distance） The size of gate electrode spacing can be less than,
● vertical local interlinkage portion structure can be at an edge of diffusion fin（The edge of horizontal orientation）It is upper overlapping（Level is fixed To）Spread fin；In the case, for separating vertical local interlinkage portion structure（In mask is cut）Some cuttings Touching or overlapping diffusion fin can be defined as,
● horizontal local interlinkage portion structure can be at an edge of gate electrode structure（The edge of vertical orientation）It is upper overlapping（Hang down Directly orient）Gate electrode structure.
● the size of grid cap（The distance that i.e. gate electrode structure is extended beyond following diffusion fin）Can be with Less than the sizes of one or more diffusion spacings of fin, or the size less than average diffusion spacing of fin,
● the separating distance between each the being aligned altogether and gate electrode structure end that is positioned adjacent to（I.e. gate electrode structure is cut Cut distance）The size of one or more diffusion spacings of fin can be less than or equal to, or less than average diffusion spacing of fin Size,
●（As measured on the direction vertical with diffusion fin）N-type diffusion fin and the p-type being respectively positioned adjacent to spread Longitudinal centre line separating distance between fin can be defined as the integral multiple or flat of one or more diffusion spacings of fin Spread the integral multiple of spacing of fin.
In the exemplary embodiment, semiconductor devices includes substrate, the first transistor and second transistor.The first crystal Pipe is with the source region and drain region in the first diffusion fin.The first diffusion fin is configured to from the substrate Surface protrude.The first diffusion fin is configured to：In a first direction longitudinally from the of the described first diffusion fin One end extends to the second end of the first diffusion fin.The second transistor has the source area in the second diffusion fin Domain and drain region.The second diffusion fin is configured to from the surface of substrate protrusion.The second diffusion wing Piece is configured to：Longitudinally extend to second diffusion from the first end of the described second diffusion fin in said first direction Second end of fin.The second diffusion fin is oriented to spread wing by the described first diffusion fin and with described first Piece is spaced apart.In addition, the first end of the second diffusion fin or second end are positioned at the first direction On described first diffusion fin the first end and second end between.
The first transistor and second transistor above-mentioned can be located at the different opening positions in second direction.Separately Outside, each in the first transistor and second transistor can be the transistor dimensionally gated.
The first transistor above-mentioned includes：The gate electrode structure of first linear shape, it is such as from the substrate On look such and be longitudinally extended in the second direction vertical with the first direction.Second transistor above-mentioned Including：The gate electrode structure of second linear shape, it is hanging down as viewed from the substrate with the first direction It is longitudinally extended in the straight second direction.First diffusion fin first end and the second end in it is at least one can be in institute State the gate electrode structure of gate electrode structure Yu the second linear shape that first linear shape is positioned on first direction Between.Also, it is described second diffusion fin the first end and the second end in it is at least one can be in the first direction On be positioned between the gate electrode structure of first linear shape and the gate electrode structure of the second linear shape.Described The gate electrode structure of one linear shape be oriented to by second linear shape gate electrode structure and with it is described The gate electrode structure of second linear shape is spaced apart.
The semiconductor devices can also include：The local interlinkage portion structure of linear shape, it is in this second direction Extension, and be positioned at the gate electrode structure of first linear shape and the second linear shape gate electrode structure it Between.The local interlinkage portion structure of the linear shape can be substantially in said first direction in first linear shape It is placed in the middle between the gate electrode structure of gate electrode structure and the second linear shape.The local interlinkage portion structure of the linear shape It may be coupled to one or more in the first diffusion fin and the second diffusion fin.
The semiconductor devices can also include：The local interlinkage portion structure of linear shape, it is in said first direction Extension, and be positioned between the first diffusion fin and the second diffusion fin.The local interlinkage portion knot of the linear shape Structure can be substantially placed in the middle between the described first diffusion fin and the second diffusion fin in this second direction.In addition, institute The local interlinkage portion structure for stating linear shape may be coupled in the first gate electrode structure and second grid electrode structure It is one or more.
The local interlinkage portion structure of the linear shape above-mentioned extended in said first direction can be mentioned as The local interlinkage portion structure of first linear shape.The semiconductor devices can also include：The local interlinkage of second linear shape Portion's structure, it extends in this second direction, and is positioned at the gate electrode structure and second of first linear shape Between the gate electrode structure of linear shape.The local interlinkage portion structure of second linear shape can be substantially described It is placed in the middle between the gate electrode structure of first linear shape and the gate electrode structure of the second linear shape on one direction. In addition, the local interlinkage portion structure of second linear shape may be coupled to the first diffusion fin, second diffusion It is one or more in fin.In addition, in certain embodiments, the local interlinkage portion structure of first linear shape can be with It is the first line segments of the non-linear local interlinkage portion structure two-dimensionally changed, the local interlinkage portion of second linear shape Structure can be the second line segments of the non-linear local interlinkage portion structure two-dimensionally changed.In addition, in some examples In, the local interlinkage portion structure of first linear shape and the local interlinkage portion structure of the second linear shape may be coupled to that This.
The semiconductor devices can also include：Contact structures, it is positioned at the first diffusion fin and the second diffusion wing Between piece.In certain embodiments, the contact structures can be substantially in the described first diffusion fin and the second diffusion fin Between it is placed in the middle.In certain embodiments, the contact structures may be coupled to the first gate electrode structure or described second Gate electrode structure.
The semiconductor devices can also include：Contact structures, it is positioned at the first gate electrode structure and second gate Between the electrode structure of pole.In certain embodiments, the contact structures can substantially the first gate electrode structure with It is placed in the middle between second grid electrode structure.In addition, in certain embodiments, the semiconductor devices can be included in described second The conductive interconnection portion structure being positioned on direction between the first diffusion fin and the second diffusion fin, wherein, the contact structures It is connected to conductive interconnection portion structure.In certain embodiments, conductive interconnection portion structure is not to exist for diffusion fin The lowest hierarchical level interconnection structure that the first party upwardly extends.
The semiconductor devices can also include：Conductive interconnection portion structure, is positioned at the first expansion in said first direction Dissipate between fin and the second diffusion fin, wherein, the contact structures are connected to conductive interconnection portion structure.In some implementations In example, conductive interconnection portion structure is more high-level interconnection structure.
The semiconductor devices can also include：One or more interconnection structures, wherein, one or more Some in interconnection structure include one or more interconnection sections extended in said first direction.In some implementations In example, some in one or more the interconnection section extended in said first direction are positioned at described first and expanded Dissipate between fin and the second diffusion fin.In addition, in certain embodiments, extend in said first direction one or Some in more interconnection sections are positioned on the first diffusion fin or the second diffusion fin.In some realities Apply in example, one or more the interconnection section extended in said first direction is according to such as in this second direction Measured second direction interconnection spacing and the corresponding first party for being positioned in one or more interconnection section To between the center line of orientation.
In certain embodiments, the first diffusion fin and the second diffusion fin can be according to such as in the second directions Go up measured diffusion spacing of fin and be positioned in the corresponding first party of the first diffusion fin and the second diffusion fin To between the center line of orientation, wherein, the second direction interconnection spacing is the rational multiple of the diffusion spacing of fin, Wherein, the rational multiple is defined to the ratio of integer value.
In certain embodiments, each in the first diffusion fin and the second diffusion fin is according to described second The first measured diffusion spacing of fin or the second measured in this second direction diffusion spacing of fin on direction and by Center line positioning is pressed, wherein, the first diffusion spacing and the second diffusion spacing one after the other replace in this second direction, its In, the average diffusion spacing of fin is being averaged for the first diffusion spacing of fin and the second diffusion spacing of fin,
Wherein, the second direction interconnection spacing is the rational multiple of the average diffusion spacing of fin, wherein, it is described to have Reason several times number is defined to the ratio of integer value.In certain embodiments, the first diffusion spacing of fin is equal to the described second diffusion Spacing of fin.In certain embodiments, the first diffusion spacing of fin is different from the described second diffusion spacing of fin.
One or more interconnection structures above-mentioned can include local interlinkage portion structure, more high-level interconnection Structure or its combination, wherein, the lowest hierarchical level interconnection structure that it is diffusion fin that local interlinkage portion structure, which is not, wherein, The more high-level interconnection structure be formed at level of the local interlinkage portion structure relative to the substrate it is mutual Company's portion's structure.
In certain embodiments, each in the first diffusion fin and the second diffusion fin is according to such as described the The first measured diffusion spacing of fin or the second measured in this second direction diffusion spacing of fin on two directions and Center line positioning is pressed, wherein, the first diffusion spacing and the second diffusion spacing one after the other replace in this second direction, Wherein, the average diffusion spacing of fin is being averaged for the first diffusion spacing of fin and the second diffusion spacing of fin.In addition, One or more the interconnection section extended in said first direction can be according to such as institute in this second direction Measurement the first interconnection spacing or the second measured in this second direction interconnection spacing and pressed center line positioning , wherein, the first interconnection spacing and the second interconnection spacing one after the other replace in this second direction, wherein, institute It is being averaged for the first interconnection spacing and the second interconnection spacing to state average interconnection spacing.In addition, the average interconnection Portion's spacing is the rational multiple of the average diffusion spacing of fin, wherein, the rational multiple is defined to the ratio of integer value.
In certain embodiments, it is described first diffusion spacing of fin be equal to described second diffusion spacing of fin, described first Interconnection spacing is equal to the second interconnection spacing.In certain embodiments, the first diffusion spacing of fin is different from institute The second diffusion spacing of fin is stated, the first interconnection spacing is different from the second interconnection spacing.In certain embodiments, The first diffusion spacing of fin is equal to the first interconnection spacing, and it is mutual that the second diffusion spacing of fin is equal to described second Company's portion's spacing.
The semiconductor devices can also include：One or more interconnection structures, wherein, one or more Some in interconnection structure include one or more interconnection sections extended in this second direction.In some implementations In example, some in one or more the interconnection section extended in this second direction are positioned in described first Between gate electrode structure and second grid electrode structure.In certain embodiments, what is extended in this second direction is described Some in one or more interconnection sections are positioned in the first gate electrode structure or the second grid electrode On structure.
In certain embodiments, one or more the interconnection section extended in this second direction is according to such as In said first direction measured first direction interconnection spacing and be positioned in one or more interconnection area Between the center line of the corresponding second direction orientation of section.In addition, the first gate electrode structure and second grid electrode knot Structure can according to being positioned in such as gate electrode spacing measured in said first direction first gate electrode knot Between the center line of the corresponding second direction of structure and second grid electrode structure orientation.The first direction interconnection spacing can To be the rational multiple of the gate electrode spacing, wherein, the rational multiple is defined to the ratio of integer value.
One or more interconnection structures above-mentioned can include local interlinkage portion structure, more high-level interconnection Structure or its combination, wherein, the lowest hierarchical level interconnection structure that it is diffusion fin that local interlinkage portion structure, which is not, wherein, The more high-level interconnection structure be formed at level of the local interlinkage portion structure relative to the substrate it is mutual Company's portion's structure.
In certain embodiments, the semiconductor devices can also include more than first individual transistors, be respectively provided with by corresponding The corresponding source region and corresponding drain region that diffusion fin is formed.Each diffusion wing of individual transistor more than described first Piece is configured to：Protruded from the surface of the substrate.Each diffusion fin of individual transistor more than described first is configured to： Longitudinally extend to the second end from the first end of corresponding diffusion fin in said first direction.More than described first brilliant The first end of the diffusion fin of body pipe is substantially aligned with each other in said first direction.
In addition, the semiconductor devices can include：Individual transistor more than second, it is respectively provided with corresponding diffusion fin and is formed Corresponding source region and corresponding drain region.Each diffusion fin of individual transistor more than described second is configured to：From The surface of the substrate protrudes.Each diffusion fin of individual transistor more than described second is configured to：In the first party Longitudinally extend to the second end from the first end of corresponding diffusion fin upwards.The expansion of individual transistor more than described second The first end for dissipating fin is substantially aligned with each other in said first direction.In addition, the institute of individual transistor more than described second State in the first end of diffusion fin it is one or more be positioned in said first direction more than described first it is brilliant Between one or more first ends and the second end in the diffusion fin of body pipe.
In certain embodiments, each in the first end of the diffusion fin of individual transistor more than described second It is positioned one or more institutes in said first direction in the diffusion fin of individual transistor more than described first State between first end and the second end.In certain embodiments, in the diffusion fin of individual transistor more than described second at least One be oriented to by more than described first individual transistors at least one diffusion fin and with more than described first individual transistors It is described it is at least one diffusion fin be spaced apart.In addition, in certain embodiments, individual transistor more than described first can include n The combination of transistor npn npn, p-type transistor or n-type transistor and p-type transistor, individual transistor more than described second can include n-type The combination of transistor, p-type transistor or n-type transistor and p-type transistor.In certain embodiments, individual crystal more than described first Pipe is n-type transistor, and individual transistor is p-type transistor more than described second.
In certain embodiments, more than described first diffusion fin and more than first diffusion fins are located such that its phase The center line substantial registration for the first direction orientation answered such as the first measured in this second direction diffusion spacing of fin The diffusion fin alignment grid alignment of restriction and measured the second diffusion spacing of fin in described second direction are limited Diffusion fin alignment grid.The first diffusion spacing of fin and the second diffusion spacing of fin are appeared in described with alternating sequence In second direction.In addition, in certain embodiments, the diffusion wing of individual transistor more than described first and more than second individual transistors Piece jointly occupies part at least eight successive alignment opening positions of the diffusion fin alignment grid.
In the exemplary embodiment, a kind of method for manufacturing semiconductor devices is disclosed.Methods described includes：Substrate is provided. Methods described also includes：The first transistor is formed over the substrate, spreads wing first so as to which the first transistor has Source region and drain region in piece, the first diffusion fin are formed from the surface of substrate protrusion, and described the One diffusion fin is formed：Longitudinally extend to described first from the first end of the described first diffusion fin in a first direction Spread the second end of fin.Methods described also includes：Second transistor is formed over the substrate, so as to the second transistor With the source region and drain region in the second diffusion fin, the second diffusion fin is formed from the substrate The surface protrudes, and the second diffusion fin is formed：In said first direction longitudinally from the described second diffusion wing The first end of piece extends to the second end of the second diffusion fin, and the second diffusion fin is formed to be expanded by described first Dissipate fin and the opening position being spaced apart with the described first diffusion fin.In addition, form the first transistor and the second crystal Pipe, so as to which the first end of the described second diffusion fin or second end are formed described first in said first direction Spread the opening position between the first end of fin and second end.
It should be appreciated that any circuit layout disclosed herein including finfet field effect transistor can be by tangible Form（Such as in a digital format）Storage is on a computer-readable medium.For example, given circuit layout can be stored in layout In data file, and can be one or more storehouses that may be selected from unit.Layout data file can be formatted as GDS II（Graphic data system）Database file, OASIS（Open works system interchange standard）Database file or any other class The document format data for being suitable for storing and transmitting semiconductor device layout of type.It is in addition, disclosed herein including fin The multi-layer layout of the unit of field-effect transistor can be included in the multi-layer cloth intra-office of bigger semiconductor devices.More most lead The multi-layer layout of body device can also be stored by the form of layout data file for example identified above.
In addition, the present invention described herein may be embodied as the computer-readable code on computer-readable medium.Example Such as, computer-readable code can include the cloth for storing the layout of the unit disclosed herein including finfet field effect transistor Office data file.Computer-readable code can also include being used to be optionally comprised in the finfet field effect transistor disclosed in this One or more layout storehouses and/or the programmed instruction of unit.Based on layout storehouse and/or unit can also be stored in by number format On calculation machine computer-readable recording medium.
As mentioned herein computer-readable medium be can be with any data storage device of data storage, the data are hereafter Reason computer system is read.The example of computer-readable medium includes hard disk driver, network-attached storage part（NAS）, read-only storage Device, random access memory, CD-ROM, CD-R, CD-RW, tape and other optics and non-optical data storage devices part.Institute's coupling The multiple computer-readable mediums being distributed in the network of the computer system connect can be used for storing computer-readable code Corresponding part, be able to store and perform by distributed way in network so as to computer-readable code.
In the exemplary embodiment, a kind of data storage device, there is the cloth for being used to reproduce semiconductor devices stored thereon The computer-executable program instructions of office.The data storage device includes：For limiting to be formed over the substrate the The computer program instructions of one transistor, so as to which the first transistor is defined as：With the source in the first diffusion fin Polar region domain and drain region, the first diffusion fin are defined as：Protruded from the surface of the substrate, the first diffusion wing Piece is defined as：Longitudinally extend to the first diffusion fin from the first end of the described first diffusion fin in a first direction The second end.The data storage device also includes：For limiting the calculating for the second transistor to be formed over the substrate Machine programmed instruction, so as to which the second transistor is defined as：With second diffusion fin in source region and drain region, The second diffusion fin is defined as：Protruded from the surface of the substrate, the second diffusion fin is defined as：First On direction longitudinally from described second diffusion fin first end extend to it is described second diffusion fin the second end, described second Diffusion fin is defined as being positioned to being spaced apart by the described first diffusion fin and with the described first diffusion fin, and described the Two diffusion fins are defined as：So that its first end or its second end are in said first direction positioned at the described first diffusion fin The first end and second end between.
It is also understood that any circuit layout disclosed herein including finfet field effect transistor can be fabricated to half The part of conductor device or chip.Building semiconductor devices（Such as integrated circuit, memory cell etc.）In, perform a series of Manufacturing operation is to limit the feature on semiconductor wafer.Chip includes the form of the multi-level structure limited on a silicon substrate IC-components.At substrate level, the transistor device of fin is formed with diffusion zone and/or spread.In subsequent layer In level, interconnection metallized thread is patterned and is electrically connected to transistor device, to limit desired IC-components.Separately Outside, the conductive layer after patterning is insulated by dielectric material with other conductive layers.
Although describing the present invention on some embodiments, it is to be understood that, those skilled in the art are before reading Its various replacements, addition, displacement and equivalent will be realized when the specification and studying accompanying drawing in face.Therefore, the invention is intended to wrap Include all these replacements, addition, displacement and the equivalent fallen within the spirit and scope of the present invention.

Claims (26)

1. a kind of integrated circuit, including：
First finfet field effect transistor of the first transistor type；
First finfet field effect transistor of second transistor type；
Second finfet field effect transistor of the first transistor type；
Second finfet field effect transistor of second transistor type；
Each and second transistor type in first and second finfet field effect transistors of the first transistor type Each in first and second finfet field effect transistors has accordingly in the gate electrode of parallel direction Longitudinal extending, the The grid of first finfet field effect transistor of one transistor types and the first finfet field effect transistor of second transistor type Pole electrode has it substantially brilliant with the longitudinal centre line of the common gate electrode rail alignment extended in a parallel direction, first The grid of second finfet field effect transistor of body tubing type and the second finfet field effect transistor of second transistor type electricity Pole is positioned on the opposite side of common gate electrode track,
Each part in first and second finfet field effect transistors of the first transistor type is by being electrically connected to public section The corresponding diffusion fin for the first diffusion types selected is formed,
Each part in first and second finfet field effect transistors of second transistor type is by being electrically connected to public section The corresponding diffusion fin for the second diffusion types selected is formed, and the diffusion fin of the first diffusion types is being put down by internal non-diffusing regions Jointly separated with the diffusion fin of the second diffusion types on line direction,
First finfet field effect transistor of the first transistor type and the first finfet crystal of second transistor type The gate electrode of the two is managed to be formed by the first conductive structure, to be electrically connected to each other by the first conductive structure, the first transistor The gate electrode of second finfet field effect transistor of type is formed by the second conductive structure, the second wing of second transistor type The gate electrode of gate fin-fet is formed by the 3rd conductive structure, each in first, second, and third conductive structure It is included in the part extended in internal non-diffusing regions；
First conductive contact structure is connected to the part of the second conductive structure internally extended in non-diffusing regions；And
Second conductive contact structure is connected to the part of the 3rd conductive structure internally extended in non-diffusing regions, and first and Each in two conductive contact structures is defined as gate contact or local interlinkage structure respectively.
2. integrated circuit as claimed in claim 1, wherein at least one end of the second conductive structure and the 3rd conductive structure are extremely Few one end is aligned with the first common point in a parallel direction.
3. integrated circuit as claimed in claim 2, wherein at least part of the first conductive contact structure and the second conductive contact At least part of structure is aligned with the second common point in a parallel direction.
4. integrated circuit as claimed in claim 3, in addition to：
3rd finfet field effect transistor of the first transistor type；
3rd finfet field effect transistor of second transistor type；
4th finfet field effect transistor of the first transistor type；
4th finfet field effect transistor of second transistor type；
Each and second transistor type in third and fourth finfet field effect transistor of the first transistor type Each in third and fourth finfet field effect transistor has accordingly in the gate electrode of parallel direction Longitudinal extending,
Each gate electrode and second transistor type of third and fourth finfet field effect transistor of the first transistor type The third and fourth finfet field effect transistor each gate electrode be formed as corresponding to one of linear shape conductive structure Point, and
Each in first, second, and third conductive structure has linear shape.
5. integrated circuit as claimed in claim 4, in addition to：
Amorphous fluid line shape shape grid hierarchy characteristic, wherein forming the first, second, third and fourth of the first transistor type Finfet field effect transistor and the first, second, third and fourth finfet field effect transistor of second transistor type are at least Each linear shape conductive structure of one gate electrode is positioned according to grid spacing, and the grid spacing is defined as in phase The equal center to center interval measured in a second direction between adjacent grid hierarchy characteristic, the second direction is perpendicular to flat Line direction, and wherein amorphous fluid line shape shape grid hierarchy characteristic is also positioned according to the grid spacing.
6. integrated circuit as claimed in claim 1, wherein second conductive structure passes through single interconnection levels by part The electrical connection of extension and be electrically connected to the 3rd conductive structure.
7. integrated circuit as claimed in claim 6, in addition to：
3rd finfet field effect transistor of the first transistor type；
3rd finfet field effect transistor of second transistor type；
4th finfet field effect transistor of the first transistor type；
4th finfet field effect transistor of second transistor type；
Each and second transistor type in third and fourth finfet field effect transistor of the first transistor type Each in third and fourth finfet field effect transistor has accordingly in the gate electrode of parallel direction Longitudinal extending,
The first, second, third and fourth finfet field effect transistor of the first transistor type and the of second transistor type First, each gate electrode of second, third and the 4th finfet field effect transistor positions according to grid spacing, the grid spacing It is defined as the equal center to center interval measured in a second direction between adjacent gate electrodes, the second direction Perpendicular to parallel direction.
8. integrated circuit as claimed in claim 7, wherein at least part of the first conductive contact structure and the second conductive contact At least part of structure is aligned with common point in a parallel direction.
9. integrated circuit as claimed in claim 8, wherein the part of the electrical connection extended by single interconnection levels is by linear Shape interconnection conductive structures are formed.
10. the third and fourth finfet crystal of integrated circuit as claimed in claim 9, wherein the first transistor type Each gate electrode quilt of third and fourth finfet field effect transistor of each gate electrode and second transistor type of pipe The part of linear shape conductive structure corresponding to being formed as, and each in wherein first, second, and third conductive structure It is linear shape.
11. integrated circuit as claimed in claim 1, in addition to：
Positioning is close to multiple diffusion fins of the first diffusion types and noncrystal tube grid level spaced away is special Sign, and it is close to positioning and noncrystal tube grid level spaced away with multiple diffusion fins of the second diffusion types Feature.
12. integrated circuit as claimed in claim 11, in addition to：
3rd finfet field effect transistor of the first transistor type；
3rd finfet field effect transistor of second transistor type；
4th finfet field effect transistor of the first transistor type；
4th finfet field effect transistor of second transistor type；
Each and second transistor type in third and fourth finfet field effect transistor of the first transistor type Each in third and fourth finfet field effect transistor has accordingly in the gate electrode of parallel direction Longitudinal extending,
Each gate electrode and second transistor type of third and fourth finfet field effect transistor of the first transistor type The third and fourth finfet field effect transistor each gate electrode be formed as corresponding to one of linear shape conductive structure Point, and
Each in first, second, and third conductive structure has linear shape, and
Wherein, the noncrystal tube grid hierarchy characteristic is linear shape.
13. the first and second finfets of integrated circuit as claimed in claim 12, wherein the first transistor type are brilliant Each part in body pipe is formed by the shared diffusion fin of the first diffusion types, and wherein the of second transistor type One and second each part in finfet field effect transistor formed by the shared diffusion fin of the second diffusion types, the first He The shared diffusion fin of second diffusion types is electrically connected to common node.
14. integrated circuit as claimed in claim 13, wherein forming the first, second, third and the of the first transistor type Four finfet field effect transistors and the first, second, third and fourth finfet field effect transistor of second transistor type are extremely Each linear shape conductive structure of a few gate electrode is positioned according to grid spacing, and the grid spacing is defined as The equal center to center interval measured in a second direction between neighboring gates hierarchy characteristic, the second direction perpendicular to Parallel direction, and wherein amorphous fluid line shape shape grid hierarchy characteristic is also positioned according to the grid spacing.
15. integrated circuit as claimed in claim 14, wherein in the first and second finfets of the first transistor type The center to center distance measured in a second direction between the gate electrode of transistor is substantially equal in second transistor class The center to center distance measured in a second direction between the gate electrode of first and second finfet field effect transistors of type.
16. the first and second finfet crystal of integrated circuit as claimed in claim 1, wherein the first transistor type Each part in pipe is formed by the shared diffusion fin of the first diffusion types, and wherein the first of second transistor type Formed with each part in the second finfet field effect transistor by the shared diffusion fin of the second diffusion types, first and The shared diffusion fin of two diffusion types is electrically connected to common node.
17. integrated circuit as claimed in claim 16, in addition to：
Positioning is close to multiple diffusion fins of the first diffusion types and noncrystal tube grid level spaced away is special Sign, and it is close to positioning and noncrystal tube grid level spaced away with multiple diffusion fins of the second diffusion types Feature.
18. integrated circuit as claimed in claim 17, wherein second conductive structure passes through single interconnection layer by part Level extension electrical connection and be electrically connected to the 3rd conductive structure.
19. integrated circuit as claimed in claim 18, in addition to：
3rd finfet field effect transistor of the first transistor type；
3rd finfet field effect transistor of second transistor type；
4th finfet field effect transistor of the first transistor type；
4th finfet field effect transistor of second transistor type；
Each and second transistor type in third and fourth finfet field effect transistor of the first transistor type Each in third and fourth finfet field effect transistor has accordingly in the gate electrode of parallel direction Longitudinal extending,
Each gate electrode and second transistor type of third and fourth finfet field effect transistor of the first transistor type The third and fourth finfet field effect transistor each gate electrode be formed as corresponding to one of linear shape conductive structure Point, and
Each in first, second, and third conductive structure has linear shape；And
Amorphous fluid line shape shape grid hierarchy characteristic.
20. integrated circuit as claimed in claim 19, wherein the part of the electrical connection extended by single interconnection levels is by line Shape shape interconnection conductive structures are formed.
21. integrated circuit as claimed in claim 1, in addition to：
Grid hierarchy characteristic, it forms the gate electrode of the finfet field effect transistor of the first transistor type and expanded second Extend between at least two diffusion fins of scattered type.
22. the first and second finfets of integrated circuit as claimed in claim 21, wherein the first transistor type are brilliant Each part in body pipe is formed by the shared diffusion fin of the first diffusion types, and wherein the of second transistor type One and second each part in finfet field effect transistor formed by the shared diffusion fin of the second diffusion types, the first He The shared diffusion fin of second diffusion types is electrically connected to common node.
23. integrated circuit as claimed in claim 22, wherein in the first and second finfets of the first transistor type The center to center distance measured in a second direction between the gate electrode of transistor is substantially equal in second transistor class The center to center distance measured in a second direction between the gate electrode of first and second finfet field effect transistors of type, The second direction is perpendicular to parallel direction.
24. integrated circuit as claimed in claim 23, in addition to：
3rd finfet field effect transistor of the first transistor type；
3rd finfet field effect transistor of second transistor type；
4th finfet field effect transistor of the first transistor type；
4th finfet field effect transistor of second transistor type；
Each and second transistor type in third and fourth finfet field effect transistor of the first transistor type Each in third and fourth finfet field effect transistor has accordingly in the gate electrode of parallel direction Longitudinal extending,
Each gate electrode and second transistor type of third and fourth finfet field effect transistor of the first transistor type The third and fourth finfet field effect transistor each gate electrode be formed as corresponding to linear shape conductive structure part, And
Each in first, second, and third conductive structure has linear shape.
25. a kind of method for being used to create the layout of integrated circuit, including：
Computer is operated for limiting the layout of the first finfet field effect transistor of the first transistor type；
Computer is operated for limiting the layout of the first finfet field effect transistor of second transistor type；
Computer is operated for limiting the layout of the second finfet field effect transistor of the first transistor type；
Computer is operated for limiting the layout of the second finfet field effect transistor of second transistor type；
Each layout and second transistor class in first and second finfet field effect transistors of the first transistor type Each layout in first and second finfet field effect transistors of type has accordingly in the grid of parallel direction Longitudinal extending Pole electrode lay-out feature, the first finfet field effect transistor of the first transistor type and the first fin of second transistor type The gate electrode spatial layout feature of field-effect transistor has its common gate electrode rail substantially with extending in a parallel direction The longitudinal centre line of road alignment, the second finfet field effect transistor of the first transistor type and the second of second transistor type The gate electrode spatial layout feature of finfet field effect transistor is positioned on the opposite side of common gate electrode track,
Each layout in first and second finfet field effect transistors of the first transistor type is public including being electrically connected to The corresponding diffusion fin layout of first diffusion types of node,
Each layout in first and second finfet field effect transistors of second transistor type is public including being electrically connected to The corresponding diffusion fin layout of second diffusion types of node, the diffusion fin of the first diffusion types are laid out by internal non-diffusing cloth Office region jointly separates with the diffusion fin layout of the second diffusion types in a parallel direction,
First finfet field effect transistor of the first transistor type and the first finfet crystal of second transistor type The part that the gate electrode spatial layout feature of the two is formed the first conductive structure spatial layout feature is managed, with by being led corresponding to first The conductive structure of electric topology layout feature is electrically connected to each other, the grid of the second finfet field effect transistor of the first transistor type Pole electrode lay-out feature is formed the part of the second conductive structure spatial layout feature, the second fin field effect of second transistor type The gate electrode spatial layout feature of transistor is answered to be formed the part of the 3rd conductive structure spatial layout feature, first, second, and third Each in conductive structure spatial layout feature is included in the part extended on internal non-diffusing layout areas；
Computer is operated for limiting the layout of the first conductive contact structure, it is defined as being connected to corresponding to non-internally The part of the conductive structure of the part of the second conductive structure spatial layout feature extended on diffusion zone；And
Computer is operated for limiting the layout of the second conductive contact structure, it is defined as being connected to corresponding to non-internally The part of the conductive structure of the part of the 3rd conductive structure spatial layout feature extended on diffusion zone, the first and second conductive contacts Each in structure is defined as gate contact or local interlinkage structure respectively.
26. a kind of data storage device with layout of the programmed instruction being stored thereon for generation integrated circuit, bag Include：
Programmed instruction for the layout of the first finfet field effect transistor for limiting the first transistor type；
Programmed instruction for the layout of the first finfet field effect transistor for limiting second transistor type；
Programmed instruction for the layout of the second finfet field effect transistor for limiting the first transistor type；
Programmed instruction for the layout of the second finfet field effect transistor for limiting second transistor type；
Each layout and second transistor class in first and second finfet field effect transistors of the first transistor type Each layout in first and second finfet field effect transistors of type has accordingly in the grid of parallel direction Longitudinal extending Pole electrode lay-out feature, the first finfet field effect transistor of the first transistor type and the first fin of second transistor type The gate electrode spatial layout feature of field-effect transistor has its common gate electrode rail substantially with extending in a parallel direction The longitudinal centre line of road alignment, the second finfet field effect transistor of the first transistor type and the second of second transistor type The gate electrode spatial layout feature of finfet field effect transistor is positioned on the opposite side of common gate electrode track,
Each layout in first and second finfet field effect transistors of the first transistor type is public including being electrically connected to The corresponding diffusion fin layout of first diffusion types of node,
Each layout in first and second finfet field effect transistors of second transistor type is public including being electrically connected to The corresponding diffusion fin layout of second diffusion types of node, the diffusion fin of the first diffusion types are laid out by internal non-diffusing cloth Office region jointly separates with the diffusion fin layout of the second diffusion types in a parallel direction,
First finfet field effect transistor of the first transistor type and the first finfet crystal of second transistor type The part that the gate electrode spatial layout feature of the two is formed the first conductive structure spatial layout feature is managed, with by being led corresponding to first The conductive structure of electric topology layout feature is electrically connected to each other, the grid of the second finfet field effect transistor of the first transistor type Pole electrode lay-out feature is formed the part of the second conductive structure spatial layout feature, the second fin field effect of second transistor type The gate electrode spatial layout feature of transistor is answered to be formed the part of the 3rd conductive structure spatial layout feature, first, second, and third Each in conductive structure spatial layout feature is included in the part extended on internal non-diffusing layout areas；
For the programmed instruction for the layout for limiting the first conductive contact structure, first conductive contact structure is defined as being connected to Corresponding to the part of the conductive structure of the part of the second conductive structure spatial layout feature internally extended in non-diffusing regions；And
For the programmed instruction for the layout for limiting the second conductive contact structure, second conductive contact structure is defined as being connected to Corresponding to the part of the conductive structure of the part of the 3rd conductive structure spatial layout feature internally extended in non-diffusing regions, first Gate contact or local interlinkage structure are defined as respectively with each in the second conductive contact structure.
CN201611023356.2A 2012-01-13 2013-01-13 Circuit with linear finfet structure Pending CN107424999A (en)

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