AU2013207719A1 - Circuits with linear finfet structures - Google Patents

Circuits with linear finfet structures Download PDF

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Publication number
AU2013207719A1
AU2013207719A1 AU2013207719A AU2013207719A AU2013207719A1 AU 2013207719 A1 AU2013207719 A1 AU 2013207719A1 AU 2013207719 A AU2013207719 A AU 2013207719A AU 2013207719 A AU2013207719 A AU 2013207719A AU 2013207719 A1 AU2013207719 A1 AU 2013207719A1
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Prior art keywords
diffusion
diffusion fin
pitch
fin
semiconductor device
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AU2013207719A
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AU2013207719B2 (en
Inventor
Scott T. Becker
Daryl Fox
Dhrumil Gandhi
Carole Lambert
Jim Mali
Jonathan R. Quandt
Michael C. Smayling
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Tela Innovations Inc
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Tela Innovations Inc
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Priority to AU2016202229A priority Critical patent/AU2016202229B2/en
Priority to AU2018200549A priority patent/AU2018200549B2/en
Priority to AU2020201521A priority patent/AU2020201521A1/en
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Abstract

A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.

Description

WO 2013/106799 PCT/US2013/021345 1 Circuits with Linear Finfet Structures by inventors Scott T. Becker, Michael C. Smayling, Dhrumil Gandhi, Jim Mali, Carole Lambert, Jonathan R. Quandt, Daryl Fox 5 Background 100011 It is known that optical lithography has reached the end of its capability at the 193 nm light wavelength and 1.35 numerical aperture (NA) immersion system. The minimum straight line resolution capability of this equipment is approximately 40 nm with an approximate 80 nm feature-to-feature pitch. A feature-to-feature pitch requirement lower than about 80 nm would 10 require multiple patterning steps for a given structure type within a given chip level. Also, line end resolution becomes more challenging as lithography is pushed toward its resolution limits. In semiconductor device layout, a typical metal line pitch at the 32 nm critical dimension is approximately 100 nm. In order to achieve the cost benefit of feature scaling, a scaling factor of 0.7 to 0.75 is desirable. The scaling factor of about 0.75 to reach the 22 nm critical 15 dimension would require a metal line pitch of about 75 nm, which is below the capability of current single exposure lithography systems and technology. It is within this context that the present invention arises. Summary [00021 In one embodiment, a semiconductor device includes a substrate, a first transistor, and a 20 second transistor. The first transistor has a source region and a drain region within a first diffusion fin. The first diffusion fin is structured to project from a surface of the substrate. The first diffusion fin is structured to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The second transistor has a source region and a drain region within a second diffusion fin. The second diffusion fin is structured 25 to project from the surface of the substrate. The second diffusion fin is structured to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Also, either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion 30 fin. [00031 In one embodiment, a method of fabricating a semiconductor device is disclosed. The method includes providing a substrate. The method also includes forming a first transistor on the substrate, such that the first transistor has a source region and a drain region within a first WO 2013/106799 PCT/US2013/021345 2 diffusion fin, and such that the first diffusion fin is formed to project from a surface of the substrate, and such that the first diffusion fin is formed to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The method also includes forming a second transistor on the substrate, such that the second transistor has a 5 source region and a drain region within a second diffusion fin, and such that the second diffusion fin is formed to project from the surface of the substrate, and such that the second diffusion fin is formed to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, and such that the second diffusion fin is formed at a position next to and spaced apart from the first diffusion fin. Also, the first and 10 second transistors are formed such that either the first end or the second end of the second diffusion fin is formed at a position in the first direction between the first end and the second end of the first diffusion fin. [00041 In one embodiment, a data storage device has computer executable program instructions stored thereon for rendering a layout of a semiconductor device. The data storage 15 device includes computer program instructions for defining a first transistor to be formed on a substrate, such that the first transistor is defined to have a source region and a drain region within a first diffusion fin, and such that the first diffusion fin is defined to project from a surface of the substrate, and such that the first diffusion fin is defined to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. 20 The data storage device also includes computer program instructions for defining a second transistor to be formed on the substrate, such that the second transistor is defined to have a source region and a drain region within a second diffusion fin, and such that the second diffusion fin is defined to project from the surface of the substrate, and such that the second diffusion fin is defined to extend lengthwise in the first direction from a first end of the second 25 diffusion fin to a second end of the second diffusion fin, and such that the second diffusion fin is defined to be positioned next to and spaced apart from the first diffusion fin, and such that the second diffusion fin is defined to have either its first end or its second end positioned in the first direction between the first end and the second end of the first diffusion fin. Brief Description of the Drawings 30 [00051 Figures 1A and 1B show an example layout view of a finfet transistor, in accordance with some embodiments of the present invention. [00061 Figure IC shows a variation of the finfet transistor of Figures 1AI1B in which the diffusion fin 102 is more pyramid-shaped in the vertical cross-section view A-A, in accordance with some embodiments of the present invention.
WO 2013/106799 PCT/US2013/021345 3 [00071 Figure ID shows a simplified vertical cross-section view of the substrate having a number of finfet transistors formed thereon, in accordance with some embodiments of the present invention. [00081 Figure 1E shows a diagram of fin pitch relationship in which the internal fin pitch Psi 5 is substantially equal to the external fin pitch Ps2, in accordance with some embodiments of the present invention. [00091 Figure 1F shows a variation of the fin pitch relationship diagram of Figure 1E in which the denominator (y) of the rational number is two, in accordance with some embodiments of the present invention. 10 [00101 Figure 1 G shows a variation of the fin pitch relationship diagram of Figure 1 E in which the denominator (y) of the rational number is three, in accordance with some embodiments of the present invention. [00111 Figure 1H shows a more generalized version of the fin pitch relationship diagram of Figure lE in which the internal fin pitch Psi and external fin pitch Ps2 are different, in 15 accordance with some embodiments of the present invention. [00121 Figure 2A shows an exemplary cell layout incorporating finfet transistors, in accordance with some embodiments of the present invention. [00131 Figure 2B shows a circuit diagram corresponding to the 2-input NAND configuration of Figure 2D, in accordance with some embodiments of the present invention.. 20 [00141 Figure 2C shows a circuit diagram corresponding to the 2-input NOR configuration of Figure 2E, in accordance with some embodiments of the present invention.. [00151 Figure 2D shows the layout of Figure 2A in which the diffusion fins 201A are formed of an n-type diffusion material and the diffusion fins 201B are formed of a p-type diffusion material, in accordance with some embodiments of the present invention.. 25 [00161 Figure 2E shows the layout of Figure 2A in which the diffusion fins 201A are formed of a p-type diffusion material and the diffusion fins 201B are formed of an n-type diffusion material, in accordance with some embodiments of the present invention.. [00171 Figure 2F shows a variation of the layout of Figure 2A in which the gate electrode structures have their ends substantially aligned on the top of the cell and on the bottom of the 30 cell, in accordance with some embodiments of the present invention. [00181 Figure 2G shows a variation of the layout of Figure 2A in which contacts are formed to extend from the met1 interconnect structure to the horizontal local interconnect structure under the power rail at the top of the cell and at the bottom of the cell, in accordance with some embodiments of the present invention.
WO 2013/106799 PCT/US2013/021345 4 [00191 Figure 2H shows a variation of the cell of Figure 2A in which two different diffusion fin pitches are used, in accordance with some embodiments of the present invention. [00201 Figure 21 shows a variation of the layout of Figure 2A in which the diffusion fins and horizontal local interconnect structures under the power rails at the top and bottom of the cell 5 are extended to the full width of the met1 interconnect structures that serve as the power rails, in accordance with some embodiments of the present invention. [00211 Figure 3 shows a variation of the layout of Figure 2A in which the met1 power rails are connected to vertical local interconnect, such that the met1 power rails serve as local power supplies, in accordance with some embodiments of the present invention. 10 [00221 Figure 4 shows a variation of the layout of Figure 2A in which a two-dimensionally varying met1 interconnect structure is used within the cell for intra-cell routing, in accordance with some embodiments of the present invention. [00231 Figure 5 shows a variation of the layout of Figure 2A in which the met1 power rails are connected to vertical local interconnect and in which a two-dimensionally varying metl 15 interconnect structure is used within the cell for intra-cell routing, in accordance with some embodiments of the present invention. [00241 Figure 6 shows a variation of the layout of Figure 2A in which fixed, minimum width, shared local met1 power supplies are used, along with a two-dimensionally varying met1 interconnect structure within the cell for intra-cell routing, in accordance with some 20 embodiments of the present invention. [00251 Figure 7 shows a variation of the layout of Figure 2A having shared local and global power supplies with hard connections in the cell, and a two-dimensionally varying met1 interconnect structure within the cell for intra-cell routing, in accordance with some embodiments of the present invention. 25 [0026] Figure 8A shows a layout of an example standard cell in which input pins are placed between diffusion fins of the same type to ease routing congestion, and in which some diffusion fins are used as interconnect conductors, in accordance with some embodiments of the present invention. [0027] Figure 8B shows a variation of Figure 8A in which two different gate electrode pitches 30 are used, in accordance with some embodiments of the present invention. [00281 Figure 8C shows a circuit schematic of the layout of Figure 8A, in accordance with some embodiments of the present invention.. [00291 Figure 9A shows an example standard cell layout in which diffusion fins are utilized as interconnect conductors, in accordance with some embodiments of the present invention.
WO 2013/106799 PCT/US2013/021345 5 [0030] Figure 9B shows the layout of Figure 9A with three sets of cross-coupled transistors identified, in accordance with some embodiments of the present invention. [0031] Figure 9C shows a circuit schematic of the layout of Figure 9A, in accordance with some embodiments of the present invention.. 5 [0032] Figure 10 shows an example standard cell layout with gate electrode contacts positioned substantially over the diffusion fins, in accordance with some embodiments of the present invention. [0033] Figure 11 shows an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. 10 [00341 Figures 12A/B show a variation of the layout of Figure 11 having minimum width metal power rails, in accordance with some embodiments of the present invention. [0035] Figures 13A/B show a variation of the layout of Figures 12A/B that does not have contacts from each of local interconnect and gate electrode structures to metal, in accordance with some embodiments of the present invention. 15 [0036] Figures 14A/B show a variation of the layout of Figure 11 having minimum width met1 power rails, with all metal structures of the same width and on the same pitch, including the power rails, in accordance with some embodiments of the present invention. [00371 Figures 15A/B show a variation of the layout of Figures 14A/B having metal routing structures populated so each (y) location has a met1 structure, in accordance with some 20 embodiments of the present invention. [0038] Figures 16A/B show a variation of the layout of Figure 11 having gate electrode structure contacts placed between p-type diffusion fins, in accordance with some embodiments of the present invention. [0039] Figures 17A/B show an example cell layout implementing diffusion fins, in accordance 25 with some embodiments of the present invention. [0040] Figures 18A/B show a variation of the layout of Figures 17A/B in which the contacts connect to the horizontal local interconnect, and in which the horizontal local interconnect connects directly to the vertical local interconnect, in accordance with some embodiments of the present invention. 30 [00411 Figures 19A/B show a variation of the layout of Figures 17A/B in which the power rail contact to local interconnect are not shared, and in which there is no shared local interconnect under the power rails, in accordance with some embodiments of the present invention.
WO 2013/106799 PCT/US2013/021345 6 [0042] Figures 20A/B show a variation of the layout of Figures 19A/B in which the diffusion fins are offset by a diffusion fin half-pitch with respect to the cell boundary, in accordance with some embodiments of the present invention. [00431 Figures 21A/B show a variation of the layout of Figures 20A/B having minimum width 5 power rails and negative vertical local interconnect overlap of the diffusion fins, in accordance with some embodiments of the present invention. [00441 Figures 22A/B show a variation of the layout of Figures 17A/B having minimum width power rails, no shared local interconnect or diffusion fins under the power rails, and a larger space between p-find and n-fins, in accordance with some embodiments of the present 10 invention. [00451 Figures 23A/B show a variation of the layout of Figures 17AB, in accordance with some embodiments of the present invention. [00461 Figures 24A/B show a variation of the layout of Figures 23A/B, in accordance with some embodiments of the present invention. 15 [00471 Figures 25A/B show a variation of the layout of Figures 23A/B, in which the cell is doubled in height, in accordance with some embodiments of the present invention. [00481 Figures 26A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. [00491 Figures 27A/B show a variation of the layout of Figures 26A/B, in accordance with 20 some embodiments of the present invention. [00501 Figures 28A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. [00511 Figures 29AB show a variation of the layout of Figures 28A/B in which there are no local interconnect structures present between two gate electrode structures of n-type transistors, 25 in accordance with some embodiments of the present invention. [00521 Figures 30A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. [0053] Figure 31A shows an example sdff cell layout with gate electrode and local interconnect line end gaps centered substantially between diffusion fins, in accordance with 30 some embodiments of the present invention. [00541 Figure 31B shows the example sdff cell layout of Figure 31A, with the local interconnect line end gaps centered substantially between the diffusion fins circled, in accordance with some embodiments of the present invention..
WO 2013/106799 PCT/US2013/021345 7 [00551 Figure 31C shows the example sdff cell layout of Figures 31A and 31B with annotation of the region between two adjacent gate electrode structures in which the diffusion fin ends overlap each other in the x direction, in accordance with some embodiments of the present invention. 5 [00561 Figure 32 shows an example layout in which all contact layer structures are placed between the diffusion fins, in accordance with some embodiments of the present invention.. [00571 Figures 33 and 34 shows example layouts in which all contact layer structures are placed on the diffusion fins, in accordance with some embodiments of the present invention.. [00581 Figures 35A/B through 47A/B show cross-couple transistor configurations having 10 transmission gate in both logic paths, requiring all the internal nodes to have a connection between p-type and n-type, in accordance with some embodiments of the present invention.. [00591 Figure 35C shows a circuit schematic of the layouts of Figures 35A/B through 47A/B and 63A/B through 67A/B, in accordance with some embodiments of the present invention. [00601 Figures 48A/B through 57A/B show cross-couple transistor configurations having 15 transmission gate in the logic path with larger transistors, and tristate gate in other paths, in accordance with some embodiments of the present invention.. [00611 Figure 48C shows a circuit schematic of the layouts of Figures 48A/B through 58A/B, in accordance with some embodiments of the present invention. [00621 Figures 58A/B through 59A/B show cross-couple transistor configurations having 20 transmission gate in the logic path with smaller transistors, and tristate gate in other paths, in accordance with some embodiments of the present invention.. [00631 Figure 59C shows a circuit schematic of the layout of Figures 59A/B, in accordance with some embodiments of the present invention. [00641 Figures 60A/B through 62A/B show cross-couple transistor configurations having 25 tristate gate in both logic paths, in accordance with some embodiments of the present invention.. [00651 Figure 60C shows a circuit schematic of the layouts of Figures 60A/B through 62A/B and Figures 68A/B through 69A/B, in accordance with some embodiments of the present invention. 30 [00661 Figures 63A/B through 67A/B show cross-couple transistor configurations having transmission gate in both logic paths, requiring all the internal nodes to have a connection between p-type and n-type, in accordance with some embodiments of the present invention..
WO 2013/106799 PCT/US2013/021345 8 [00671 Figures 68A/B through 69A/B show cross-couple transistor configurations having tristate gate in both logic paths, in accordance with some embodiments of the present invention.. [00681 Figure 70A shows an example of gate electrode tracks 70-1A through 70-IE defined 5 within the restricted gate level layout architecture, in accordance with some embodiments of the present invention. [00691 Figure 70B shows the exemplary restricted gate level layout architecture of Figure 70A with a number of exemplary gate level features 7001-7008 defined therein, in accordance with some embodiments of the present invention. 10 [00701 Figures 71A/B through 77A/B show a number of example SDFF circuit layouts that utilize both tri-state and transmission gate based cross-coupled circuit structures, in accordance with some embodiments of the present invention. [00711 Figure 71C shows a circuit schematic of the layouts of Figures 71A/B and 77A/B, in accordance with some embodiments of the present invention. 15 [00721 Figure 72C shows a circuit schematic of the layouts of Figures 72AB through 76A/B, in accordance with some embodiments of the present invention. Detailed Description [00731 In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled 20 in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention. Additionally, it should be understood that the various circuit and/or layout features depicted in a given figure presented herein can be utilized in combination with other circuit and/or layout features depicted in other figures 25 presented herein. [00741 A "finfet" is a transistor constructed from a vertical silicon island, i.e., fin. The finfet transistor can also be referred to as a tri-gate transistor. The term "finfet" transistor as used herein refers to any transistor configuration that includes a diffusion structure that projects upward from an underlying substrate. Figures IA and 1B show an example layout view of a 30 finfet transistor 100, in accordance with some embodiments of the present invention. The finfet transistor 100 is constructed from a diffusion fin 102 and a gate electrode layer 104. The diffusion fin 102 projects vertically upward from a substrate 105, as shown in Figure lB. A gate oxide layer 106 is disposed between the diffusion fin 102 and the gate electrode layer 104. The diffusion fin 102 can be doped to form either a p-type transistor or an n-type transistor.
WO 2013/106799 PCT/US2013/021345 9 The portion of the gate electrode layer 104 that covers the diffusion fin 102 forms the gate electrode of the finfet transistor 100. Therefore, the gate electrode of the finfet transistor 100 can exist on three or more sides of the diffusion fin 102, thereby providing for control of the finfet transistor channel from three or more sides, as opposed to from one side as in a non 5 finfet transistor. Also, in some embodiments, the finfet transistor is formed as a "wrap-around" transistor in which the gate oxide layer 106 and the gate electrode layer 104 also extend beneath the diffusion fin 102. [0075] It should be understood that the example finfet transistor 100 depicted in Figures 1A and 1 B is provided by way of example and does not represent any limitation on the manner in 10 which a finfet transistor, as referenced herein, may be designed and/or fabricated. Specifically, in some embodiments, the diffusion fin (e.g., 102) can be formed as a layering of different materials, including but not limited to Si (silicon), SiGe (silicon germanium), Ge (germanium), InP (indium phosphide), CNT (carbon nanotube), SiNT (silicon nanotube), or any combination thereof, among others. The gate oxide layer 106 can be formed from many different types of 15 dielectric materials. For example, in some embodiments, the gate oxide layer 106 may be formed as a layer of hafnium oxide on a layer of silicon dioxide. In other embodiments, the gate oxide layer 106 can be formed by one or more other dielectric materials. In some embodiments, the gate electrode layer 104 can be formed by any number of electrically conductive materials. For example, in some embodiments, the gate electrode layer 104 can be 20 formed as a film of TiN (titanium nitride) or TaN (tantalum nitride) covered by polysilicon. It should be understood, however, that in other embodiments the gate electrode layer 104 can be formed by other materials. [00761 Also, while the example diffusion fin 102 of Figure 1B is shown as having a substantially vertically projecting rectangular structure relative to the substrate 105 in the 25 vertical cross-section view A-A, it should be understood that diffusion fins 102 in as "as fabricated" state on a semiconductor chip may or may not have the substantially vertically projecting rectangular structure relative to the substrate 105. For example, in some embodiments, the diffusion fins 102 in their "as-fabricated" state may have a more triangular or pyramid-like shape in the vertical cross-section view A-A. Figure 1C shows a variation of 30 the finfet transistor 100 in which the diffusion fin 102 is more pyramid-shaped in the vertical cross-section view A-A. As depicted in Figure IC, in some embodiments, the sides of the diffusion fins 102 that extend upward from the substrate 105 may extend upward from the substrate at an angle to the substrate 105, so as to be non-perpendicular to the substrate 105. Also, it should be understood that such a non-perpendicular relationship between the substrate WO 2013/106799 PCT/US2013/021345 10 105 and the sides of the diffusion fins 102 that extend upward from the substrate 105 may be by design or may be a result of fabrication. [00771 Additionally, in some embodiments, a vertical projection distance of the diffusion fins 102 above the substrate 105 will be substantially equal across a region of the semiconductor 5 chip. However, in other embodiments, some diffusion fins 102 may be designed and fabricated to have multiple different vertical projection distances above the substrate 105 across one or more regions of the semiconductor chip. Because the channel area of the finfet transistor 100 is a function of the diffusion fin 102 vertical projection distance above the substrate 105, such a variation in diffusion fin 102 vertical projection distance above the substrate 105 can be used 10 to adjust a drive strength of selected finfet transistors 100 relative to others on the semiconductor chip. In one example, selective variation in diffusion fin 102 height can be provided through selective etching/overetching of the diffusion fin 102 structures during fabrication. [00781 Figure ID shows a simplified vertical cross-section view of the substrate 105 having a 15 number of finfet transistors 100 formed thereon, in accordance with some embodiments of the present invention. During fabrication of the finfet transistors 100, a series of cores 107 are formed to facilitate formation of side spacers 109 for each of the cores 107. The side spacers 109 are utilized as masking features to facilitate formation of the underlying finfet transistors 100. It should be understood that the cores 107, the side spacers 109, and the finfet transistors 20 100 extend lengthwise in a parallel manner, i.e., into the page as shown in Figure 1D. It should be understood that the cores 107 and side spacers 109 are ultimately removed so as not to be present in the final as-fabricated semiconductor chip/device. The relative spacing of the finfet transistors 100 to each other is a function of the sizes and spacings of the cores 107 and side spacers 109. 25 [00791 Figure ID shows the cores 107 as having a width Wb and a pitch Pb. Also, Figure 1D shows the side spacers 109 as having a width Ws. The finfet transistors 100 can then be characterized as having an alternating pair of fin pitches Psl, Ps2, where Psi is an average centerline-to-centerline pitch between side spacers 109 of a given core 107 (Ps1 is referred to as an internal fin pitch), and where Ps2 is an average centerline-to-centerline pitch between 30 neighboring side spacers 109 of a adjacently positioned cores 107 (Ps2 is referred to as an external fin pitch). Assuming uniformity in each of the core 107 width Wb, the core 107 pitch Pb, and the side spacer 109 width Ws, the internal fin pitch PsI is equal to the sum of the core 107 width Wb and side spacer 109 width Ws. And, the external fin pitch Ps2 is equal to the core 107 pitch Pb minus the sum of the core 107 width Wb and side spacer 109 width Ws.
WO 2013/106799 PCT/US2013/021345 11 Therefore, both the internal fin pitch PsI and the external fin pitch Ps2 will vary as each of the core 107 pitch Pb, core 107 width Wb, and/or side spacer 109 width Ws varies. Thus, it should be understood that reference to a given "fin pitch" refers to an average of a given fin pitch, i.e., fin pitch Psave is equal to an average of the internal fin pitch Psl and the external fin pitch 5 Ps2, where each of the internal fin pitch Psi and the external fin pitch Ps2 are themselves averages. [00801 Figure IE shows a diagram of fin pitch relationship in which the internal fin pitch PsI is substantially equal to the external fin pitch Ps2, in accordance with some embodiments of the present invention. A cell height He is equal to the average fin pitch multiplied by a rational 10 number, i.e., multiplied by a ratio of integers x and y, where x is the numerator of the rational number and y is the denominator of the rational number. In the case of Figure 1E where the internal fin pitch PsI and external fin pitch Ps2 are equal, the average fin pitch is equal to each of PsI and Ps2. Therefore, the cell height Hc is equal to either the internal fin pitch Psi or the external fin pitch Ps2 multiplied by the rational number. It should be understood that the 15 denominator (y) of the rational number indicates a number of cells required to obtain a repetition of a fin-to-cell boundary spacing when the number of cells are positioned in an abutting manner in the direction of the cell height Hc, i.e., in the direction perpendicular to the lengthwise direction of the fins. Also, when the numerator (x) of the rational number is evenly divisible by the denominator (y) of the rational number, the top and bottom cell boundaries can 20 have the same fin-to-cell boundary spacing when the internal fin pitch Psl and/or the external fin pitch Ps2 is aligned with (indexed to) the cell boundary. [00811 Figure iF shows a variation of the fin pitch relationship diagram of Figure lE in which the denominator (y) of the rational number is two, in accordance with some embodiments of the present invention. Therefore, in Figure 1F the fin-to-cell boundary spacing will repeat 25 every two cell heights Hc. Also, in the example of Figure IF, the numerator (x) of the rational number is not evenly divisible by the denominator (y) of the rational number. Therefore, the top and bottom fin-to-cell boundary spacings will be different when the internal fin pitch Psi and/or the external fin pitch Ps2 is aligned with (indexed to) the cell boundary. [00821 Figure 1 G shows a variation of the fin pitch relationship diagram of Figure lE in which 30 the denominator (y) of the rational number is three, in accordance with some embodiments of the present invention. Therefore, in Figure 1G the fin-to-cell boundary spacing will repeat every three cell heights Hc. Also, in the example of Figure IG, the numerator (x) of the rational number is not evenly divisible by the denominator (y) of the rational number. Therefore, the top and bottom fin-to-cell boundary spacings will be different when the internal WO 2013/106799 PCT/US2013/021345 12 fin pitch PsI and/or the external fin pitch Ps2 is aligned with (indexed to) the cell boundary. It should be appreciated that the rational number can be defined in any manner necessary to obtain any desired fin-to-cell boundary spacing repetition frequency in the direction of the cell height He and/or any desired fin-to-cell boundary spacing specification. 5 [00831 Figure 1H shows a more generalized version of the fin pitch relationship diagram of Figure iE in which the internal fin pitch Psi and external fin pitch Ps2 are different, in accordance with some embodiments of the present invention. In this example, the external fin pitch Ps2 is greater than the internal fin pitch Psi. It should be understood that the cell height He is equal to the average fin pitch Psave multiplied by the rational number (x/y), where x 10 and y are integers. Also, it should be understood that the integer y indicates the fin-to-cell boundary spacing repetition frequency in the direction of the cell height Hc. Also, it should be understood that the top and bottom fin-to-cell boundary spacings can be equal to each other when the rational number (x/y) reduces to an integer value, i.e., when x is evenly divisible by y. If the rational number (x/y) does not reduce to an integer value, different fin phasing 15 variations of a given cell may be defined in a cell library, where each fin phasing variation corresponds to a different possible fin-to-cell boundary spacing relationship for the given cell. Also, the number of possible fin phasing variations for a given cell will be equal to the denominator (y) of the rational number (x/y) in its most mathematically reduced form. [0084] As discussed above, Figure 1H shows use of two different diffusion fin pitches Psi and 20 Ps2, in accordance with some embodiments of the present invention. More specifically, in Figure 1H every other pair of adjacently positioned diffusion fin structures is placed according to a smaller pitch Psl. In some embodiments, the larger diffusion fin pitch Ps2 is about 80 nanometers (nm) and the smaller diffusion fin pitch Psi is about 60 nm. However, it should be understood that in other embodiments, the smaller diffusion fin pitch Psi can be any size, and 25 the larger diffusion fin pitch Ps2 can be any size. It should be understood that some embodiments can utilize more than two diffusion fin pitches within a given cell or block. And, some embodiments may utilize a single diffusion fin pitch within a given cell or block. Also, it should be understood that any layer of the semiconductor device, or portion thereof, can be formed in a manner similar to that described herein with regard to the diffusion fin pitch(es). 30 For example, a local interconnect layer or a higher-level interconnect layer of the semiconductor device, or portion thereof, can include interconnect conductive structures formed on one or more corresponding pitch(es) in a manner similar to that described herein with regard to the diffusion fin pitch(es).
WO 2013/106799 PCT/US2013/021345 13 [0085] Transistor scaling has slowed below the 45 nanometers (nm) critical dimension due to gate oxide limitations and/or source/drain leakage scaling issues. The finfet transistor mitigates these issues by controlling the channel of the finfet transistor from three sides. The increased electrical fields in the channel of the finfet transistor improve the relationship between I-on (on 5 drive current) and I-off (sub-threshold leakage current). Finfet transistors can be employed at the 22 nm critical dimension and below. However, due to their vertical projection, finfet transistors can have restricted placement in various circuit layouts. For instance, there can be a required finfet-to-finfet minimum spacing and/or a required finfet-to-finfet minimum pitch, among other restrictions. Embodiments are disclosed herein for cell layouts that utilize finfet 10 transistors in a manner which complements layout scaling. [0086] A cell, as referenced herein, represents an abstraction of a logic function, and encapsulates lower-level integrated circuit layouts for implementing the logic function. It should be understood that a given logic function can be represented by multiple cell variations, wherein the cell variations may be differentiated by feature size, performance, and process 15 compensation technique (PCT) processing. For example, multiple cell variations for a given logic function may be differentiated by power consumption, signal timing, current leakage, chip area, OPC (optical proximity correction), RET (reticle enhancement technology), etc. It should also be understood that each cell description includes the layouts for the cell in each level (or layer) of a chip within the associated vertical column of the chip, as required to 20 implement the logic function of the cell. More specifically, a cell description includes layouts for the cell in each level of the chip extending from the substrate level up through a particular interconnect level. [0087] Figure 2A shows an exemplary cell layout incorporating finfet transistors, in accordance with some embodiments of the present invention. The cell layout includes a 25 diffusion level within which a number of diffusion fins 201A/201B are defined for subsequent formation of finfet transistors and associated connections. In some embodiments, in an as drawn layout state, the diffusion fins 201A/201B are linear-shaped. The diffusion fins 201A/201B are oriented to be parallel to each other such that their lengths extend in a first direction (x), and such that their widths extend in a second direction (y) perpendicular to the 30 first direction (x). [00881 In some embodiments, such as shown in Figure 2A, the diffusion fins 201A/201B are placed in accordance with a fixed lengthwise centerline-to-lengthwise centerline pitch 203, as measured in the second direction (y). In this embodiment, the pitch 203 of the diffusion fins 201A/201B may be related to the cell height as measured in the second direction (y), such that WO 2013/106799 PCT/US2013/021345 14 the diffusion fin pitch 203 can be continued across cell boundaries. In Figure 2A, the cell abutment edges represent the cell boundaries that run parallel to the diffusion fins 201A/201B. In some embodiments, the diffusion fins for multiple neighboring cells will be placed in accordance with a common global diffusion fin pitch, thereby facilitating chip level 5 manufacturing of the diffusion fins in multiple cells. [00891 It should be understood that other embodiments may utilize multiple diffusion fin pitches within a given cell or among a collection of cells. For example, Figure 2H shows a variation of the cell of Figure 2A in which two different diffusion fin pitches 203 and 205 are used, in accordance with some embodiments of the present invention. It should be understood 10 in some embodiments the diffusion fins 201A/201B can be placed in accordance with one or more lengthwise centerline-to-lengthwise centerline pitches, or may be placed in an unrestricted manner with regard to lengthwise centerline-to-lengthwise centerline spacing. Also, in some embodiments, the diffusion fins 201A/201B can be placed in accordance with a given pitch and some pitch locations may be vacant with regard to diffusion fin placement. 15 Additionally, in some embodiments, diffusion fins can be placed in a spaced apart, end-to-end manner at a given diffusion fin pitch location within a cell. [0090] In each Figure presented herein, each diffusion fin, e.g., diffusion fins 201A/201B in Figure 2A, is of either an n-type diffusion material or a p-type diffusion material. Also, depending on the particular cell implementation, the type of material of the diffusion fins may 20 swapped to obtain a different cell logic function. Therefore, the notation type1_diff and type2_diff is used in the Figures to denote different material types for the diffusion fins. For example, if the type1_diff material is an n-type material, then the type2_diff material is a p type material, vice-versa. [0091] The cell layout also includes a number of linear-shaped gate electrode structures 207. 25 The linear-shaped gate electrode structures 207 extend in a substantially perpendicular direction to the diffusion fins 201A/201B, i.e., in the second direction (y). When fabricated, the linear-shaped gate electrode structures 207 wrap over the diffusion fins 201A/201B to form gate electrodes of finfet transistors. It should be understood that an appropriate gate oxide material is disposed, i.e., positioned/deposited, between the diffusion fins 201A/201B and the 30 gate electrode structures 207 formed thereover. [0092] In some embodiments, the linear-shaped gate electrode structures 207 are placed in accordance with a fixed gate pitch 209 as measured in the first direction (x) between lengthwise centerlines of adjacently positioned gate electrode structures 207. In some embodiments, the gate pitch 209 is related to the cell width as measured in the first direction WO 2013/106799 PCT/US2013/021345 15 (x), such that the gate pitch can be continued across cell boundaries. Therefore, in some embodiments, the gate electrode structures 207 for multiple neighboring cells can be placed in accordance with a common global gate pitch, thereby facilitating chip level manufacturing of the linear-shaped gate electrode structures 207 in multiple cells. 5 [0093] It should be understood that some of the gate pitch locations in a given cell may be occupied by gate electrode structures 207, while other gate pitch locations in the given cell are left vacant. Also, it should be understood that multiple gate electrode structures 207 can be placed in a spaced apart, end-to-end manner along any of the gate electrode pitch locations within a given cell. It should be further understood that in some embodiments, the gate 10 electrode structures 207 can be placed in accordance with one or more gate pitches, or can be placed in an unrestricted manner with regard to gate pitch. [00941 The cell layout can also include a number of horizontal linear-shaped local interconnect structures (lih) 211, and/or a number of vertical linear-shaped local interconnect structures (liv) 213. The vertical local interconnect structures 213 are oriented parallel to the gate electrode 15 structures 207. The horizontal local interconnect structures 211 are oriented parallel to the diffusion fins 201A/201B. In some embodiments, placement of the vertical local interconnect structures 213 is defined to be out of phase from placement of the gate electrode structures 207 by one-half of the gate pitch. Thus, in this embodiment, each vertical local interconnect structure 213 is centered between its neighboring gate electrode structures 207, when the 20 neighboring gate electrode structures 207 are positioned on the gate pitch. Therefore, in this embodiment, adjacently placed vertical local interconnect structures 213 will have a center-to center spacing equal to a local gate pitch or a global gate pitch, where the local gate pitch is applied within a given cell, and the global gate pitch is applied across multiple cells. [0095] In some embodiments, placement of the horizontal local interconnect structures 211 is 25 defined to be out of phase from placement of the diffusion fins 201A/201B by one-half of the diffusion fin pitch. Thus, in this embodiment, the horizontal local interconnect structures 211 can be centered between its neighboring diffusion fins 201A/201B, when the neighboring diffusion fins 201A/201B are positioned on the diffusion fin pitch. Therefore, in this embodiment, adjacently placed horizontal local interconnect structures 211 will have a center 30 to-center spacing equal to a local diffusion fin pitch or a global diffusion fin pitch, where the local diffusion fin pitch is applied within a given cell, and the global diffusion fin pitch is applied across multiple cells. [00961 In some embodiments, the cell layout also includes a number of linear-shaped metal 1 (met1) interconnect structures 215. The met1 interconnect structures 215 are oriented parallel WO 2013/106799 PCT/US2013/021345 16 to the diffusion fins 201A/201B and perpendicular to the gate electrode structures 207. In some embodiments, placement of the met1 interconnect structures 215 is defined to be out of phase from placement of the diffusion fins 201A/201B by one-half of the diffusion fin pitch. Thus, in this embodiment, each metal interconnect structure 215 is centered between its neighboring 5 diffusion fins, when its neighboring diffusion fins are positioned on the diffusion fin pitch, albeit within a higher chip level. Therefore, in this embodiment, adjacently placed metl interconnect structures 215 will have a center-to-center spacing equal to a local diffusion fin pitch or a global diffusion fin pitch, where the local diffusion fin pitch is applied within a given cell, and the global diffusion fin pitch is applied across multiple cells. In some embodiments, 10 the met1 interconnect structure 215 pitch, and hence the diffusion track pitch, is set at the single exposure lithographic limit, e.g., 80 nm for 193 nm wavelength light and 1.35 NA. In this embodiment, no double exposure lithography, i.e., multiple patterning, is required to manufacture the metal interconnect structures 215. It should be understood that other embodiments can utilize met1 interconnect structures 215 that are oriented perpendicular to the 15 diffusion fins 201A/20 IB and parallel to the gate electrode structures 207. [0097] The cell layout also includes a number of contacts 217 defined to connect various met1 interconnect structures 215 to various local interconnect structures 211/213 and gate electrode structures 207, thereby providing electrical connectivity between the various finfet transistors as necessary to implement the logic function of the cell. In some embodiments, the contacts 20 217 are defined to satisfy single exposure lithographic limits. For example, in some embodiments, layout features to which the contacts 217 are to connect are sufficiently separated to enable single exposure manufacture of the contacts 217. For instance, the met1 interconnect structures 215 are defined such that their line ends which are to receive contacts 217 are sufficiently separated from neighboring met1 interconnect structure 215 line ends 25 which are also to receive contacts 217, such that a spatial proximity between the contacts 217 is sufficiently large to enable single exposure lithography of the contacts 217. In some embodiments, neighboring contacts 217 are separated from each other by at least 1.5 times the gate pitch. It should be appreciated that line end cutting and the associated increased expense of double exposure lithography can be eliminated by sufficiently separating opposing line ends 30 of the met1 interconnect structures 215. It should be understood that contact separation and line end separation on metal layers can be independent of each other in some embodiments, depending on choices made in the manufacturing process. 10098] In some embodiments, the cell layout also includes a number of linear-shaped metal 2 (met2) interconnect structures 219. The met2 interconnect structures 219 are oriented parallel WO 2013/106799 PCT/US2013/021345 17 to the gate electrodes 207 and perpendicular to the diffusion fins 201A/201B. The met2 interconnect structures 219 can be physically connected to the metal interconnect structures 215 by via 1 structures (vl) 221, as necessary to implement the logic function of the cell. Although the example cell of Figure 2A shows the metal interconnect structures 219 extending in a 5 lengthwise manner perpendicular to the gate electrode structures 207 and the met 2 interconnect structures 219 extending in a lengthwise manner parallel to the gate electrode structures 207, it should be understood that in other embodiments the metal interconnect structures 219 and met 2 interconnect structures 219 can be defined to extend in any orientation relative to the gate electrode structures 207. It should be understood that other 10 embodiments can utilize met2 interconnect structures 219 are oriented perpendicular to the gate electrodes 207 and parallel to the diffusion fins 201A/201B. [00991 The cell of Figure 2A represents a multi-input logic gate having substantially aligned input gate electrodes, i.e., the center three gate electrode structures 207 that are co-aligned in the direction (y). Depending on the assignment of diffusion material type to the diffusion fins 15 of typel and type2, the cell of Figure 2A can have a different logic function. For example, Figure 2D shows the layout of Figure 2A in which the diffusion fins 201A are formed of an n type diffusion material and the diffusion fins 201B are formed of a p-type diffusion material. The layout of Figure 2D is that of a 2-input NAND gate. Figure 2B shows a circuit diagram corresponding to the 2-input NAND configuration of Figure 2D. Figure 2E shows the layout of 20 Figure 2A in which the diffusion fins 201A are formed of a p-type diffusion material and the diffusion fins 201B are formed of an n-type diffusion material. The layout of Figure 2E is that of a 2-input NOR gate. Figure 2C shows a circuit diagram corresponding to the 2-input NOR configuration of Figure 2E. In Figures 2B-2E, each of P1 and P2 identifies a respective p-type transistor (e.g., PMOS transistor), each of NI and N2 identifies a respective n-type transistor 25 (e.g., NMOS transistor), each of A and B identifies a respective input node, and Q identifies an output note. It should be understood that similar notation for p-type transistors, n-type transistors, input nodes, and output nodes is also used in other figures herein. [001001 Based on the foregoing, it should be appreciated that the logic function of a given cell layout can be changed by swapping the material types of the diffusion fins. 30 Therefore, for each cell layout present herein, it should be understood that multiple logic functions can be represented depending on the assignment of n-type and p-type materials to the diffusion fins. [001011 Figures 3 through 7 and 11 through 29 show variations on the layout of Figure 2A, in accordance with some embodiments of the present invention. Therefore, each of the WO 2013/106799 PCT/US2013/021345 18 cells depicted in Figures 3 through 7 and 11 through 29 represent either a 2-input NAND gate or a 2-input NOR gate, depending on the assignment of n-type and p-type materials to the typel_diff and type2 diff diffusion fins. Each of cell layouts shown in Figures 2A through 7 and 11 through 29 have the following features: 5 * a multi-input logic gate with all its input electrodes substantially aligned, e a local diffusion fin layer power supply, * a global higher level interconnect power supply, * a horizontal interconnect used to connect gate electrode to vertical local interconnect and to help improve manufacturability of the contact layers by enabling greater 10 flexibility in contact placement. [001021 It should be appreciated that each of the layouts in Figures 2A through 7 and 11 through 29 shows a different implementation of the same logic function. The layout of Figure 2A shows the following features: * gate electrodes for two or more inputs, with the gate electrodes substantially aligned, 15 e gate electrode end line spaces located between diffusion fins of the same diffusion type, * gate electrode contacts between diffusion fins of the same diffusion type, * type diff and type2_diff diffusion fins used for a local power supply, i.e., to the local interconnect of the cell, with met1 used for higher level interconnect (global) power supply, with both local and global power supplies shared with abutting cells, 20 * diffusion fins of typeldiff and type2_diff supply current to cell on a local level and can be connected to the higher level interconnect, e.g., metl, at prescribed intervals to support multiple chip power strategies, * use of horizontal local interconnect for connection to gate electrode, * a substantially horizontal local interconnect that connects the vertical local interconnect 25 layer to the gate electrode layer can be used to shift locations of the gate electrode contacts, thereby serving to increase flexibility in the contact mask patterns, which can ease potential lithography issues. [001031 Figure 2F shows a variation of the layout of Figure 2A in which the gate electrode structures have their ends substantially aligned on the top of the cell, as indicated by 30 the oval 250, and on the bottom of the cell, as indicated by the oval 251, in accordance with some embodiments of the present invention. [001041 Figure 2G shows a variation of the layout of Figure 2A in which contacts are formed to extend from the met1 interconnect structure to the horizontal local interconnect WO 2013/106799 PCT/US2013/021345 19 structure under the power rail at the top of the cell, as indicated by circle 260, and at the bottom of the cell, as indicated by circle 261, in accordance with some embodiments of the present invention. [001051 As previously mentioned, Figure 2H shows a variation of the cell of Figure 2A 5 in which two different diffusion fin pitches 203 and 205 are used, in accordance with some embodiments of the present invention. [001061 It should be understood that the diffusion fins and horizontal local interconnect structures under the power rails at the top and bottom of the cells in the various layouts depicted herein extend continuously in the horizontal direction (x) so as to service multiple 10 cells that are positioned in a row, and possibly in adjacent rows. To illustrate this point, Figure 21 shows a variation of the layout of Figure 2A in which the diffusion fins and horizontal local interconnect structures under the power rails at the top and bottom of the cell are extended to the full width of the met1 interconnect structures 215A/215B that serve as the power rails, in accordance with some embodiments of the present invention. It should be understood that the 15 diffusion fins and horizontal local interconnect structures under the power rails 215A/215B, along with the power rails 215A/215B themselves, extend continuously in the (x) direction, as indicated by arrows 270. [001071 Figure 3 shows a variation of the layout of Figure 2A in which the metal power rails are connected to vertical local interconnect, such that the met1 power rails serve as local 20 power supplies, in accordance with some embodiments of the present invention. It should be understood that the met1 power rails can be of variable width based on the cell library requirements. As with the layout of Figure 2A, the layout of Figure 3 uses multi-input logic gate with input electrodes substantially aligned. [001081 Figure 4 shows a variation of the layout of Figure 2A in which a two 25 dimensionally varying metal interconnect structure is used within the cell for intra-cell routing, in accordance with some embodiments of the present invention. As with the layout of Figure 2A, the layout of Figure 4 uses multi-input logic gate with input electrodes substantially aligned and shared local and global power supplies. In some embodiments, bends in met1, i.e., the two-dimensional changes in direction of met1, occur on a fixed grid. In some 30 embodiments, this met 1 fixed grid can include horizontal grid lines positioned between and extending parallel to the diffusion fins and positioned on the same pitch as the diffusion fins. Also, in some embodiments, this met 1 fixed grid can include vertical grid lines extending perpendicular to the diffusion fins and positioned so as to be centered on the vertical local interconnect.
WO 2013/106799 PCT/US2013/021345 20 1001091 Figure 5 shows a variation of the layout of Figure 2A in which the met1 power rails are connected to vertical local interconnect, such that the metal power rails serve as local power supplies, and in which a two-dimensionally varying met1 interconnect structure is used within the cell for intra-cell routing, in accordance with some embodiments of the present 5 invention. As with the layout of Figure 2A, the layout of Figure 5 uses multi-input logic gate with input electrodes substantially aligned. 1001101 Figure 6 shows a variation of the layout of Figure 2A in which fixed, minimum width, shared local met1 power supplies are used, along with a two-dimensionally varying metal interconnect structure within the cell for intra-cell routing, in accordance with some 10 embodiments of the present invention. As with the layout of Figure 2A, the layout of Figure 6 uses multi-input logic gate with input electrodes substantially aligned. [001111 Figure 7 shows a variation of the layout of Figure 2A having shared local and global power supplies with hard connections in the cell, and a two-dimensionally varying met1 interconnect structure within the cell for intra-cell routing, in accordance with some 15 embodiments of the present invention. As with the layout of Figure 2A, the layout of Figure 7 uses multi-input logic gate with input electrodes substantially aligned. 1001121 Figure 8A shows a layout of an example standard cell in which input pins are placed between diffusion fins of the same type to ease routing congestion, and in which some diffusion fins are used as interconnect conductors, in accordance with some embodiments of 20 the present invention. Figure 8C shows a circuit schematic of the layout of Figure 8A, including input pins 8a, 8b, 8c, and 8d. Planar standard cells, i.e., non-finfet cells, typically have input pins located between diffusion features of the opposite type, i.e., n-type versus p type, or between the diffusion features and the neighboring power rail, thereby creating a higher concentration of input pins in local areas of the planar cells. As demonstrated in Figure 25 8A, by utilizing diffusion fins and placing some input pins between diffusion fins of the same diffusion type, the input pins can be spread apart in a more even manner over a larger area, thereby easing routing congestion for the cell. Also, as demonstrated in Figure 8A, by selectively removing some gate electrode structures, as shown in the region 8001, the diffusion fin layers can be utilized as a substantially horizontal routing layer to connect to transistors or 30 local interconnect that is not neighboring. For example, in the region 8001, the diffusion fins 8003 are used as horizontal routing conductors. [001131 Figure 8B shows a variation of Figure 8A in which two different gate electrode pitches pl and p2 are used, in accordance with some embodiments of the present invention. More specifically, in Figure 8B every other pair of adjacently positioned gate electrode WO 2013/106799 PCT/US2013/021345 21 structures is placed according to a smaller pitch p2. In some embodiments, the larger gate electrode pitch pl is about 80 nanometers (nm) and the smaller gate electrode pitch p2 is about 60 nm. It should be understood that some embodiments can utilize more than two gate electrode structure pitches within a given cell or block. And, some embodiments may utilize a 5 single gate electrode structure pitch within a given cell or block. Also, it should be understood that any layer of the semiconductor device, or portion thereof, can be formed in a manner similar to that described herein with regard to the gate electrode pitch(es). For example, a local interconnect layer or a higher-level interconnect layer of the semiconductor device, or portion thereof, can include interconnect conductive structures formed on one or more corresponding 10 pitch(es) in a manner similar to that described herein with regard to the gate electrode pitch(es). [001141 Additionally, conductive structures in different layers (a.k.a. levels) of the semiconductor device, or portion thereof, can be positioned on respective pitch arrangements where a defined relationship exists between the conductive structure pitch arrangements of the 15 different layers. For example, in some embodiments, diffusion fins in the diffusion fin layer are positioned in accordance with a diffusion fin pitch arrangement that can include one or more diffusion fin pitches, and metal 1 (met1) interconnect structures in the met1 layer are positioned in accordance with a metl pitch arrangement that can include one or more met1 pitches, where one or more of the diffusion fin pitches are related to one or more of the metl 20 pitches by a rational number (x/y), where x and y are integer values. In some embodiments, a relationship between a diffusion fin pitch and a met1 pitch is defined by a rational number within a range extending from (1/4) to (4/1). [001151 Also, in some embodiments, vertical local interconnect structures (liv) can be positioned in accordance with a vertical local interconnect pitch that is substantially equal to 25 the gate electrode pitch. In some embodiments, the gate electrode pitch is less than 100 nanometers. Also, in a manner similar to that discussed above with regard to the diffusion fin pitch-to-metl pitch relationship, in some embodiments the diffusion fin pitch arrangement can be related to the horizontal local interconnect pitch arrangement by a rational number (x/y), where x and y are integer values. That is, one or more diffusion fin pitches can be related to 30 one or more horizontal local interconnect pitches by a rational number (x/y). 1001161 Figure 9A shows an example standard cell layout in which diffusion fins are utilized as interconnect conductors, in accordance with some embodiments of the present invention. Figure 9C shows a circuit schematic of the layout of Figure 9A. The example standard cell layout of Figure 9A includes multiple gate electrode line ends in a single track, WO 2013/106799 PCT/US2013/021345 22 such as in the gate electrode track 9001. Figure 9B shows the layout of Figure 9A with three sets of cross-coupled transistors identified. The first set of cross-coupled transistors is identified by the pair of lines ccla and celb. The second set of cross-coupled transistors is identified by the pair of lines cc2a and cc2b. The third set of cross-coupled transistors is 5 identified by the pair of lines cc3a and cc3b. [001171 Figure 10 shows an example standard cell layout with gate electrode contacts positioned substantially over the diffusion fins, instead of between the diffusion fins, in accordance with some embodiments of the present invention. The example standard cell layout of Figure 10 also shows variable-width met1 local power structures. In the example standard 10 cell layout of Figure 10, the contact layer is vertically aligned over the diffusion fins instead of between them. This technique could enable sharing on an abutment edge between diffusion fin structures without a dummy diffusion fin, providing a more efficient layout. It should be understood that a dummy diffusion fin is a diffusion fin that does not form a transistor. Also, it should be appreciated that this technique of vertically aligning the contact layer over the 15 diffusion fins can change the vertical alignment relationship between the metal interconnect structures and the diffusion fins. [001181 Figure 11 shows an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. In the example layout of Figure 11, the gate electrode layer includes the following features: 20 * substantially linear gate electrode structures, * three or more linear-shaped gate electrode structures on gate electrode layer, two of which are dummies, i.e., gate electrode level structures that do not form a gate electrode of a transistor, * three or more gate electrode structures on gate electrode layer that have the same 25 vertical dimension (length), i.e., same length in the y direction perpendicular to the lengthwise direction of the diffusion fins (x direction), * gate electrode structures on gate electrode layer substantially evenly spaced at substantially equal lengthwise centerline-to-lengthwise centerline pitch, * dummy gate electrode structures shared with adjacent cell on left and/or right, and 30 * dummy gate electrode structures cut under met1 power rails. [001191 In the example layout of Figure 11, the diffusion fins include the following features: WO 2013/106799 PCT/US2013/021345 23 * substantially evenly spaced diffusion fins in accordance with substantially equal pitch, diffusion fins can be on a grid, diffusion fin pitch less than 90 nm in some embodiments, * one or more diffusion fins for each of p-type and n-type, Figure 11 shows two diffusion 5 fins of n-type and two diffusion fins of p-type, but other embodiments can include any number of diffusion fins of either type, * same number of p-type and n-type diffusion fins, other embodiments may have different number of p-type versus n-type diffusion fins * one or more diffusion fins omitted under power rails, 10 e one of more diffusion fins omitted between p-type and n-type sections, and " each diffusion fin of substantially equal width and length. [001201 In the example layout of Figure 11, the local interconnect include the following features: * gate electrodes and diffusion fin source/drain connections are on different conductor 15 layers, and these different conductor layers are isolated from each other, * substantially linear conductor layer parallel to gate for source drain connection; in some embodiments, on same pitch as gate layer; and in some embodiments, this linear conductor layer may be offset by the gate half-pitch. * positive overlap of local interconnect with diffusion fins. 20 [001211 In the example layout of Figure 11, the higher level metl interconnect layer includes the following features: * gate conductor contact between p-type and n-type diffusion fins, e contacts gridded in both directions, * contacts connect local interconnect and gate conductors to the metal layer above, 25 0 substantially linear metal; metal on a pitch; metal on a pitch that is same as diffusion fin pitch with half-pitch offset vertically, e output node and input node pins on same layer, * wide power rails on top and bottom edges, each shared; power rails connect to left and right by abutment, 30 e output and input nodes on highest metal level; contacts positioned between p-type and n-type diffusion fins, and e power rail contacts to local interconnect shared with abutting cells on top and bottom.
WO 2013/106799 PCT/US2013/021345 24 [001221 Figures 12A/B show a variation of the layout of Figure 11 having minimum width metal power rails, in accordance with some embodiments of the present invention. Figure 12B shows the same layout as Figure 12A, with the layout depicted in a merged format for clarity. The example layout of Figures 12A/B also has all metal of the same width, on the same 5 pitch, including the power rails. Also, in the layout of Figures 12/B, metl is positioned at the same (y) direction locations as the diffusion fin pitch. [001231 Figures 13A/B show a variation of the layout of Figures 12A/B that does not have contacts from each of local interconnect and gate electrode structures to metal, in accordance with some embodiments of the present invention. Figure 13B shows the same 10 layout as Figure 13A, with the layout depicted in a merged format for clarity. In this embodiment, metal is formed to directly connect with the local interconnect and gate electrode structures. Also, in other embodiments, either the local interconnect structure, gate electrode structures, or both local interconnect and gate electrode structures can directly connect to met 1. [001241 Figures 14A/B show a variation of the layout of Figure 11 having minimum 15 width metl power rails, with all metal structures of the same width and on the same pitch, including the power rails, in accordance with some embodiments of the present invention. Figure 14B shows the same layout as Figure 14A, with the layout depicted in a merged format for clarity. [001251 Figures 15A/B show a variation of the layout of Figures 14A/B having metal 20 routing structures populated so each (y) location has a metl structure, in accordance with some embodiments of the present invention. Figure 15B shows the same layout as Figure 15A, with the layout depicted in a merged format for clarity. [001261 Figures 16A/B show a variation of the layout of Figure 11 having gate electrode structure contacts placed between p-type diffusion fins, in accordance with some embodiments 25 of the present invention. Figure 16B shows the same layout as Figure 16A, with the layout depicted in a merged format for clarity. The example layout of Figures 16A/B also shows diffusion fins positioned under the metal power rails and connected to VSS/VDD. Also, the diffusion fin VDD/VSS structures are shared with the cells above and/or below. For ease of illustration, the contact layer is not shown in the layout of Figures 16A/B. 30 [001271 Figures 17A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. Figure 17B shows the same layout as Figure 17A, with the layout depicted in a merged format for clarity. In the example layout of Figures 17A/B, the gate electrode layer includes the following features: 0 substantially linear gate electrode structures, WO 2013/106799 PCT/US2013/021345 25 " three or more linear structures on gate electrode layer, at least two of which are dummies, * dummy structures on gate electrode layer are of same vertical dimension (length), i.e., same length in the y direction perpendicular to the lengthwise direction of the diffusion 5 fins (x direction), * structures on gate electrode layer substantially evenly spaced and/or equal pitched in x direction, e dummy structures shared with adjacent cell on left and/or right, e dummy structures as well as gate electrode structures drawn as a single line and then 10 cut under power rails as well as where needed; gate electrode structure cuts drawn on separate layer; gate electrode layer shown as final result with cuts in Figures 17A/B, " three or more segments of gate electrode, controlling two of more type p-type and n type transistors, * multiple gate electrodes structures in the same x location, each connected to a different 15 net; and connected to two different input nets. [00128] In the example layout of Figures 17A/B, the diffusion fins include the following features: * substantially evenly spaced diffusion fins in accordance with substantially equal pitch, diffusion fins can be on a grid, diffusion fin pitch less than 90 nm in some 20 embodiments, * one or more diffusion fins for each of p-type and n-type, * same number of p-type and n-type diffusion fins, * shared diffusion fins under power rails, e diffusion fins may or may not be omitted between p-type and n-type sections; Figures 25 17A/B show all fins present, * each diffusion fin of substantially equal width and length, with the diffusion fin width measured in the y direction and the diffusion fin length measured in the x direction, e diffusion fins drawn as continuous lines; separate cut mask drawn to separate them into segments; Figures 17A/B show diffusion fin segments after separation; it should be 30 understood that in some embodiments the diffusion fin line ends can be drawn in the diffusion fin level layout or forced using the cut mask. [00129] In the example layout of Figures 17A/B, the local interconnect include the following features: WO 2013/106799 PCT/US2013/021345 26 " gate electrodes and diffusion fin source/drain connections are on different conductor layers; these different conductor layers may be merged during fabrication, e substantially linear conductor layer parallel to gate for source drain connection; in some embodiments, on same pitch as gate layer; and in some embodiments, this linear 5 conductor layer may be offset by the gate half-pitch. * positive, zero, or negative overlap of local interconnect with diffusion fins, e direct connection of local interconnect to diffusion fin source/drain and gate electrode structures, * shared local interconnect under power rail; local interconnect under power rail may be 10 omitted in some embodiments. [001301 In the example layout of Figures 17A/B, the higher level met1 interconnect layer includes the following features: * gate electrode structure contact between diffusion fins, * contacts gridded in one or both of the x and y directions, 15 e contacts connect local interconnect and gate conductors to the metal layer above, * metal locations may be fixed in one or both of x and y directions, * output node and input node pins on same layer, * wide power rails on top and bottom are shared; power rails connect to left and right by abutment; power rails contact to local interconnect are shared, 20 0 metal can have bends. In some embodiments, the bends in metal interconnect can be centered between adjacent diffusion fins. Also, in some embodiments, the vertical segments of the metal interconnect that extend in the y direction can be aligned with the vertical local interconnect so as to extend along an over the vertical local interconnect in the y direction. 25 [00131] Figures 18A/B show a variation of the layout of Figures 17A/B in which the contacts connect to the horizontal local interconnect, and in which the horizontal local interconnect connects directly to the vertical local interconnect, in accordance with some embodiments of the present invention. Figure 18B shows the same layout as Figure 18A, with the layout depicted in a merged format for clarity. In the layout of Figures 18A/B, the cuts on 30 diffusion fin, gate electrode, and local interconnect layers are not shown. [00132] Figures 19A/B show a variation of the layout of Figures 17A/B in which the power rail contact to local interconnect are not shared, and in which there is no shared local interconnect under the power rails, in accordance with some embodiments of the present WO 2013/106799 PCT/US2013/021345 27 invention. Figure 19B shows the same layout as Figure 19A, with the layout depicted in a merged format for clarity. 1001331 Figures 20A/B show a variation of the layout of Figures 19A/B in which the diffusion fins are offset by a diffusion fin half-pitch with respect to the cell boundary, in 5 accordance with some embodiments of the present invention. Figure 20B shows the same layout as Figure 20A, with the layout depicted in a merged format for clarity. The layout of Figures 20A/B also includes diffusion fin locations which are the same as the metal locations. Also, the diffusion fins are not shared on the top and bottom of the cell. Figures 20A/B also show the contacts positioned on the top of the gate electrodes and diffusion fins. Figures 10 20A/B also show different diffusion fin/local interconnect overlaps. It should be understood that in the particular layout of Figures 20AB, although the horizontal local interconnect lih and vertical local interconnect liv are shown to overlap each other in region 2001, the horizontal local interconnect lih and vertical local interconnect liv do not contact each other in region 2001. This is also true for region 2001 in Figures 21A/B to follow. However, it should 15 also be understood that in some other layouts, the horizontal local interconnect lih and vertical local interconnect liv can be made to contact each other at locations where they cross each other. 1001341 Figures 21A/B show a variation of the layout of Figures 20A/B having minimum width power rails and negative vertical local interconnect overlap of the diffusion 20 fins, in accordance with some embodiments of the present invention. Figure 21B shows the same layout as Figure 21 A, with the layout depicted in a merged format for clarity. [001351 Figures 22A/B show a variation of the layout of Figures 17A/B having minimum width power rails, no shared local interconnect or diffusion fins under the power rails, and a larger space between p-find and n-fins, in accordance with some embodiments of 25 the present invention. Figure 22B shows the same layout as Figure 22A, with the layout depicted in a merged format for clarity. 1001361 Figures 23A/B show a variation of the layout of Figures 17A/B, in accordance with some embodiments of the present invention. Figure 23B shows the same layout as Figure 23A, with the layout depicted in a merged format for clarity. The layout of Figures 23A/B has 30 the following features: " uni-directional metal interconnect structures, i.e., linear-shaped metal interconnect structures, " no shared local interconnect or fins under power rails, WO 2013/106799 PCT/US2013/021345 28 * one input pin on highest metal layer, and another input pin and the output pin on the metal layer below, e gate electrode contact isolated from local interconnect. 1001371 Also, Figures 23A/B show the diffusion fins before they are cut on the left and 5 right edges. 1001381 Figures 24A/B show a variation of the layout of Figures 23A/B, in accordance with some embodiments of the present invention. Figure 24B shows the same layout as Figure 24A, with the layout depicted in a merged format for clarity. The layout of Figures 24A/B has the following features: 10 e diffusion fin pitch smaller than metal pitch; diffusion fin pitch one-half of the metal pitch, * gate electrode and local interconnect cuts shown between diffusion fins; an alternate implementation can have cuts above diffusion fin cuts; this would reduce number of diffusion fins in one or more transistors, 15 e one input pin on highest metal layer, another input pin and the output pin on the metal layer below, * spacing between p-type and n-type diffusion fins larger than minimum; one or more diffusion fins omitted between p-type and n-type diffusion fin sections, * gate electrode contact placed on diffusion fin, 20 e local interconnect contact placed on diffusion fin, and * vertical met2 has a different offset in the x direction within the cell. [001391 Figures 25A/B show a variation of the layout of Figures 23A/B, in which the cell is doubled in height, in accordance with some embodiments of the present invention. Figure 25B shows the same layout as Figure 25A, with the layout depicted in a merged format 25 for clarity. The layout of Figures 25A/B includes twice the total number of diffusion fins in the layout of Figure 23A/B. The diffusion fin cuts are shown in the layout of Figure 25A/B. [001401 Figures 26A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. Figure 26B shows the same layout as Figure 26A, with the layout depicted in a merged format for clarity. In the example 30 layout of Figures 26A/B, the gate electrode layer includes the following features: * substantially linear gate electrode structures, * three or more linear structures on gate electrode layer, at least two of which are dummies, WO 2013/106799 PCT/US2013/021345 29 " dummy structures on gate electrode layer are of same dimension, " structures on gate electrode layer substantially evenly spaced and/or equal pitched in x direction, " dummy structures shared with adjacent cell on left and/or right, 5 e dummy structures cut under power rails, * single gate electrode structure controlling two or more p-type and n-type transistors, to be separated later in the manufacturing process to form two or more distinct gate electrodes, such as depicted by gate electrode structures 2601 and 2603, * gate electrodes in the same x location connected to two or more different nets, 10 connected to two or more different input nets, such as depicted by gate electrode structure 2601 connected to input net 2605, and by gate electrode structure 2603 connected to input net 2607, and " two or more dummy segments in same x location. [001411 In the example layout of Figures 26A/B, the diffusion fins include the following 15 features: * substantially evenly spaced diffusion fins in accordance with substantially equal pitch, diffusion fins can be on a grid, diffusion fin pitch less than 90 nm in some embodiments, * one or more diffusion fins for each of p-type and n-type, 20 * same number of p-type and n-type diffusion fins, e one or more diffusion fins omitted under power rails, " no diffusion fins omitted between p-type and n-type sections, e each diffusion fin of substantially equal width and length, and " p-type diffusion fins positioned between n-type diffusion fins, vice-versa. 25 [001421 In the example layout of Figures 26A/B, the local interconnect include the following features: * gate electrodes and diffusion fin source/drain connections are on different conductor layers; these different conductor layers are isolated from each other, * substantially linear conductor layer parallel to gate for source drain connection; in some 30 embodiments, on same pitch as gate layer; and in some embodiments, this linear conductor layer may be offset by the gate half-pitch, and " positive overlap of local interconnect with diffusion fins.
WO 2013/106799 PCT/US2013/021345 30 [001431 In the example layout of Figures 26A/B, the higher level metal interconnect layer includes the following features: * gate electrode structure contact between diffusion fins, * contacts gridded in one or both of the x and y directions, 5 * contacts connect local interconnect and gate conductors to the metal layer above, * substantially linear-shaped conductor on output node, * output node and input node pins on different layers, * power rail in middle, opposite power rail at top and bottom; top and bottom power rails shared; all power rails connect to left and right by abutment, and 10 * output node on highest metal level. [001441 Figures 27A/B show a variation of the layout of Figures 26A/B, in accordance with some embodiments of the present invention. Figure 27B shows the same layout as Figure 27A, with the layout depicted in a merged format for clarity. The layout of Figures 27A/B includes the following features: 15 * gate conductor is drawn with a cut layer, such as a cut layer that includes the cut shape 2701, * two gate conductor segments at same x location, each connecting to a different net, each connected to an input net, each controlling a p-type and an n-type transistor constructed with multiple fins, such as gate conductors 2703 and 2705, and 20 * one input pin on highest metal layer, another input pin and the output pin on the metal layer below. [001451 Figures 28A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. Figure 28B shows the same layout as Figure 28A, with the layout depicted in a merged format for clarity. In the example 25 layout of Figures 28A/B, the gate electrode layer includes the following features: " substantially linear gate electrode structures, * three or more linear structures on gate electrode layer, at least two of which are dummies, " three or more gate electrode structures are of same dimension, 30 * structures on gate electrode layer substantially evenly spaced and/or equal pitched in x direction, e dummy structures shared with adjacent cell on left and/or right, " dummy structures cut under power rails, WO 2013/106799 PCT/US2013/021345 31 [001461 It should be understood that any of the figures presented herein, including the example layout of Figures 28A/B, can have the type 1 diffusion fins defined as p-type diffusion fins and the type 2 diffusion fins defined as n-type diffusion fins, or can have the type 1 diffusion fins defined as n-type diffusion fins and the type 2 diffusion fins defined as p-type 5 diffusion fins, depending on the particular implementation embodiment. In the example layout of Figures 28A/B, the diffusion fins include the following features: * substantially evenly spaced diffusion fins in accordance with substantially equal pitch, diffusion fins can be on a grid, diffusion fin pitch less than 90 nm in some embodiments, 10 e one or more diffusion fins for each of p-type and n-type, * different number of p-type and n-type diffusion fins, * one or more diffusion fins omitted under power rails, e one or more diffusion fins omitted between p-type and n-type sections, * each diffusion fin of substantially equal width and length. 15 [001471 In the example layout of Figures 28A/B, the local interconnect include the following features: * gate electrodes and diffusion fin source/drain connections are directly from a conductor layer, * substantially linear conductor layer parallel to gate for source drain connection; in some 20 embodiments, on same pitch as gate layer; and in some embodiments, this linear conductor layer may be offset by the gate half-pitch, * zero or negative overlap of local interconnect with diffusion fins and gate electrode structures, * local interconnect can be constructed in two steps, vertical local interconnect structures 25 first, followed by horizontal local interconnect structures; each of the steps creates a set of linear, uni-directional local interconnect structures, and * alternatively, two separate local interconnect layers -- one vertical local interconnect layer, and one horizontal local interconnect layer. [001481 In the example layout of Figures 28A/B, the higher level metl interconnect 30 layer includes the following features: " diffusion fins can be positioned underneath the power rails " contacts gridded in one or both of the x and y directions, " contacts connect all local interconnects to the metal layer above, and WO 2013/106799 PCT/US2013/021345 32 contacts can be placed anywhere. [001491 Figures 29A/B show a variation of the layout of Figures 28A/B in which there are no local interconnect structures present between two gate electrode structures of n-type transistors, in accordance with some embodiments of the present invention. Figure 29B shows 5 the same layout as Figure 29A, with the layout depicted in a merged format for clarity. [00150] Figures 30A/B show an example cell layout implementing diffusion fins, in accordance with some embodiments of the present invention. Figure 30B shows the same layout as Figure 30A, with the layout depicted in a merged format for clarity. In the example layout of Figures 30A/B, the gate electrode layer includes the following features: 10 * substantially linear gate electrode structures, " three or more linear structures on gate electrode layer, at least two of which are dummies, * three or more gate electrode structures are of same dimension, " structures on gate electrode layer substantially evenly spaced and/or equal pitched in x 15 direction, " dummy structures shared with adjacent cell on left and/or right, " dummy structures cut under power rails, [001511 In the example layout of Figures 30A/B, the diffusion fins include the following features: 20 e substantially evenly spaced diffusion fins in accordance with substantially equal pitch, diffusion fins can be on a grid, diffusion fin pitch less than 90 nm in some embodiments, * one or more diffusion fins for each of p-type and n-type, e same number of p-type and n-type diffusion fins, 25 * one or more diffusion fins omitted under power rails, e one or more diffusion fins omitted between p-type and n-type sections, e each diffusion fin of substantially equal width and length. [00152] In the example layout of Figures 30A/B, the local interconnect include the following features: 30 e gate electrodes and diffusion fin source/drain connections are directly from a conductor layer, WO 2013/106799 PCT/US2013/021345 33 * substantially linear conductor layer parallel to gate for source drain connection; in some embodiments, on same pitch as gate layer; and in some embodiments, this linear conductor layer may be offset by the gate half-pitch, * zero or negative overlap of local interconnect with diffusion fins and gate electrode 5 structures, " local interconnect can be constructed in two steps, vertical local interconnect structures first, followed by horizontal local interconnect structures; each of the steps creates a set of linear, uni-directional local interconnect structures, and * in some embodiments, vertical and horizontal local interconnect structures can be 10 formed to cross and connect with each other, thereby forming a two-dimensionally varying local interconnect structure, i.e., a local interconnect structure with bends, " alternatively, two separate local interconnect layers -- one vertical local interconnect layer, and one horizontal local interconnect layer. [001531 In the example layout of Figures 30A/B, the higher level metl interconnect 15 layer includes the following features: * diffusion fins can be positioned underneath the power rails e contacts gridded in one or both of the x and y directions, e metal interconnect structures are positioned in accordance with same pitch as gate electrode structures, 20 e contacts connect all local interconnects to the metal layer above, and * contacts can be placed anywhere. 1001541 Figure 31A shows an example sdff cell layout with gate electrode and local interconnect line end gaps centered substantially between diffusion fins, in accordance with some embodiments of the present invention. In Figure 31A, the gate electrode line end gaps are 25 circled. Figure 31B shows the example sdff cell layout of Figure 31A, with the local interconnect line end gaps centered substantially between the diffusion fins circled. Based on Figures 31A through 31B, it should be understood that a cell library architecture can be generated in which all gate electrode and vertical interconnect line end gaps are centered substantially between the diffusion fins. Figure 31C shows the example sdff cell layout of 30 Figures 31A and 31B with annotation of the region 3105 between two adjacent gate electrode structures in which the diffusion fin ends overlap each other in the x direction, in accordance with some embodiments of the present invention.
WO 2013/106799 PCT/US2013/021345 34 [001551 Figures 32-34 show three examples of a part of a standard cell circuit layout, in accordance with some embodiments of the present invention. Figure 32 shows an example layout in which all contact layer structures are placed between the diffusion fins. Figures 33 and 34 shows example layouts in which all contact layer structures are placed on the diffusion 5 fins. In the example of Figure 32, the gate electrode line end gaps in some instances are substantially centered over the diffusion fins, as noted by circles 3201, and in some instances the gate electrode line end gaps are substantially centered between the diffusion fins, as noted by circles 3203. By using a cell architecture that places all of the contact layer structures over the diffusion fins, all gate electrode line end gaps can be substantially centered between the 10 diffusion fins, as noted by circles 3301 in Figures 33 and 34. One benefit here is that the gate electrode line end gaps are all on a fixed pitch. From a manufacturing perspective, it does not matter whether the gate electrode line end gaps are centered on the diffusion fins or between the diffusion fins. However, it does matter that the gate electrode line end gaps are not mixed, as in the example of Figure 32. Having the gate electrode line end gaps all on the same pitch 15 should result in a gate electrode manufacturing process that is either less expensive, more reliable or both. [001561 Figures 35A-69A show various cell layouts which demonstrate examples of different ways in which a cross-coupled transistor configuration can be implemented using finfet transistors. The cross-couple layouts of Figures 35A-69A are shown in the context of a 20 two-input multiplexor circuit (MUX2). Figure 35C shows a circuit schematic of the layouts of Figures 35A/B through 47A/B and 63A/B through 67A/B, in accordance with some embodiments of the present invention. Figure 48C shows a circuit schematic of the layouts of Figures 48A/B through 58A/B, in accordance with some embodiments of the present invention. Figure 59C shows a circuit schematic of the layout of Figures 59A/B, in accordance with some 25 embodiments of the present invention. Figure 60C shows a circuit schematic of the layouts of Figures 60A/B through 62A/B and Figures 68A/B through 69A/B, in accordance with some embodiments of the present invention. Figure 71C shows a circuit schematic of the layouts of Figures 71A/B and 77A/B, in accordance with some embodiments of the present invention. Figure 72C shows a circuit schematic of the layouts of Figures 72A/B through 76A/B, in 30 accordance with some embodiments of the present invention. The transistors on the left and right edges are added to the cross-couple to achieve MUX2 functionality. For other functions with cross-couple circuits, these may be different. Figures 35B-69B show the same layouts as Figures 35A-69A, respectively, with the layouts depicted in a merged format for clarity, and WO 2013/106799 PCT/US2013/021345 35 with the nodes of the circuit identified based on the cell layout's circuit schematic. Also, cross coupled transistor connections are identified in Figures 35A-69A by lines cel and cc2. [001571 Figures 35A/B through 47A/B and 63A/B through 67A/B show cross-couple transistor configurations having transmission gate in both logic paths, requiring all the internal 5 nodes to have a connection between p-type and n-type. Figures 48A/B through 57A/B show cross-couple transistor configurations having transmission gate in the logic path with larger transistors, and tristate gate in other paths. Tristate gate does not require a connection between p-type diffusion and n-type diffusion on the internal node. [001581 Figures 58A/B through 59A/B show cross-couple transistor configurations 10 having transmission gate in the logic path with smaller transistors, and tristate gate in other paths. Tristate gate does not require a connection between p-type diffusion and n-type diffusion on the internal node. [001591 Figures 60A/B through 62A/B and 68A/B through 69A/B show cross-couple transistor configurations having tristate gate in both logic paths. 15 [001601 Figures 63A/B through 69A/B show cell layouts that have a number of p-type diffusion fins equal to a number of n-type diffusion fins. Some of the other Figures 35A/B through 62A/B show cell layouts that a number of p-type diffusion fins not equal to a number of n-type diffusion fins. [001611 Figures 40A/B shows a cell layout that utilizes tighter spacing between 20 horizontal/vertical local interconnect structures. Figures 37A/B, 45A/B, and 49A/B show cell layout examples that utilize a larger spacing between diffusion fins. Figures 63A/B through 69A/B show cell layout examples that utilize tighter spacing between diffusion fins. Figures 43A/B and 44A/B show cell layout examples that utilize a diffusion fin as a wire. [001621 Figures 35A/B through 41A/B, 48A/B through 65A/B, and 68A/B through 25 69A/B shows cell layout examples that utilize a dense gate electrode structure implementation without split gates. Figures 42A/B through 47A/B and 66A/B through 67A/B show cell layout examples that utilize a split gate implementation with less wiring and larger transistor sizes. [001631 Figures 35A/B through 69A/B show cell layout examples that demonstrate a number of different wiring examples for various cell layouts. Figures 35A/B through 69A/B 30 show cell layout examples that demonstrate use of a fully populated gate electrode layer, including extension of gate electrode end caps and use of dummy structures where possible within the gate electrode layer. Some of the cell layouts shown in Figures 35A/B through 69A/B show examples of dummy gate electrode layer structures without the cuts at the top and bottom of the cell, i.e., prior to cut mask operation during the fabrication process. Some of the WO 2013/106799 PCT/US2013/021345 36 cell layouts, e.g., Figures 53A/B through 55A/B and 66A/B shows example cell layouts where power buses are omitted. [001641 These cross-coupled transistor configuration of Figures 35A/B through 69A/B include structures formed on each layer as well as on a combination of layers, and many of the 5 cell layout features mentioned above can be applied independent of each other. It should be understood that the cell layouts of Figures 35A/B through 69A/B show examples of what can be done with the finfet-based cross-coupled transistor configuration, and in no way represent an all inclusive set of possible cell layout configurations. Any of the features demonstrated in the various cell layout examples of Figures 35A/B through 69A/B can be combined to generate 10 additional cell layouts. [001651 Technologies for which the optical resolution is not sufficient to resolve line patterns directly will use some form of pitch division. The pitch division can be self-aligned, using spacers, or through multiple exposure steps at an achievable resolution. For example, for an ArF excimer laser scanner using water immersion of the final lens and a portion of the 15 wafer to be exposed, the optical resolution is limited to ~40nm. This corresponds to a kl value of 0.28 for a wavelength of 193 nm and an effective numerical aperture of 1.35. For diffusion fin layers and gate electrode layers and other layers formed with pitch division (for example, spacer double patterning, spacer quadruple patterning, multiple exposure Litho-Etch-Litho Etch, etc...), even though the layout is done with uniform pitches (lengthwise centerline-to 20 lengthwise centerline pitches) for the conductive structures, i.e., for the lines, the as-fabricated conductive structures can end up slightly off target due to processing variations, such that multiple (e.g., two, four, etc...) pitches end up on the wafer. [001661 Pitch division can be applied multiple times, for example pitch-division-by-2, pitch-division-by-4, with either the self-aligned spacer approach or multiple lithographic 25 exposures. Pitch-division-by-4 has been reported to achieve lines/spaces of about 11 nm. One limitation of pitch division is that the resultant line patterns can have slightly different pitches within a pattern. For pitch-division-by-2, this means that groups of two lines will have one pitch, the next group of two lines can have a slightly different pitch, the next group of two lines will have the same pitch as the first group, etc. The result on a finished wafer will be lines 30 which were intended to be on a uniform, fixed pitch but will end up on two or four or other multiple pitches. For self-aligned spacers, the original core line pattern will be drawn on a fixed, uniform pitch. For multiple exposures, each of the exposures will have lines drawn on a uniform fixed pitch. The non-uniform pitch introduced by the pitch division process may be on WO 2013/106799 PCT/US2013/021345 37 the order of 10% or less of the final pitch. For example, for a final target pitch of 50 nm, the pitches of each group of two lines may differ by less than 5 nm. Restricted Gate Level Layout Architecture [00167] The various circuit layouts incorporating finfet transistors, as discussed above, 5 can be implemented within a restricted gate level layout architecture. For the gate level, a number of parallel virtual lines are defined to extend across the layout. These parallel virtual lines are referred to as gate electrode tracks, as they are used to index placement of gate electrodes of various transistors within the layout. In some embodiments, the parallel virtual lines which form the gate electrode tracks are defined by a perpendicular spacing therebetween 10 equal to a specified gate electrode pitch. Therefore, placement of gate electrode segments on the gate electrode tracks corresponds to the specified gate electrode pitch. In another embodiment, the gate electrode tracks can be spaced at variable pitches greater than or equal to a specified gate electrode pitch. [001681 Figure 70A shows an example of gate electrode tracks 70-lA through 70-lE 15 defined within the restricted gate level layout architecture, in accordance with some embodiments of the present invention. Gate electrode tracks 70-lA through 70-lE are formed by parallel virtual lines that extend across the gate level layout of the chip, with a perpendicular spacing therebetween equal to a specified gate electrode pitch 70-3. 1001691 Within the restricted gate level layout architecture, a gate level feature layout 20 channel is defined about a given gate electrode track so as to extend between gate electrode tracks adjacent to the given gate electrode track. For example, gate level feature layout channels 70-5A through 70-5E are defined about gate electrode tracks 70-lA through 70-1E, respectively. It should be understood that each gate electrode track has a corresponding gate level feature layout channel. Also, for gate electrode tracks positioned adjacent to an edge of a 25 prescribed layout space, e.g., adjacent to a cell boundary, the corresponding gate level feature layout channel extends as if there were a virtual gate electrode track outside the prescribed layout space, as illustrated by gate level feature layout channels 70-5A and 70-5E. It should be further understood that each gate level feature layout channel is defined to extend along an entire length of its corresponding gate electrode track. Thus, each gate level feature layout 30 channel is defined to extend across the gate level layout within the portion of the chip to which the gate level layout is associated. [001701 Within the restricted gate level layout architecture, gate level features associated with a given gate electrode track are defined within the gate level feature layout channel associated with the given gate electrode track. A contiguous gate level feature can include both WO 2013/106799 PCT/US2013/021345 38 a portion which defines a gate electrode of a transistor, i.e., of a finfet transistor as disclosed herein, and a portion that does not define a gate electrode of a transistor. Thus, a contiguous gate level feature can extend over both a diffusion region, i.e., diffusion fin, and a dielectric region of an underlying chip level. 5 [00171] In some embodiments, each portion of a gate level feature that forms a gate electrode of a transistor is positioned to be substantially centered upon a given gate electrode track. Furthermore, in this embodiment, portions of the gate level feature that do not form a gate electrode of a transistor can be positioned within the gate level feature layout channel associated with the given gate electrode track. Therefore, a given gate level feature can be 10 defined essentially anywhere within a given gate level feature layout channel, so long as gate electrode portions of the given gate level feature are centered upon the gate electrode track corresponding to the given gate level feature layout channel, and so long as the given gate level feature complies with design rule spacing requirements relative to other gate level features in adjacent gate level layout channels. Additionally, physical contact is prohibited between gate 15 level features defined in gate level feature layout channels that are associated with adjacent gate electrode tracks. [001721 Figure 70B shows the exemplary restricted gate level layout architecture of Figure 70A with a number of exemplary gate level features 7001-7008 defined therein, in accordance with some embodiments of the present invention. The gate level feature 7001 is 20 defined within the gate level feature layout channel 70-5A associated with gate electrode track 70-1A. The gate electrode portions of gate level feature 7001 are substantially centered upon the gate electrode track 70-1A. Also, the non-gate electrode portions of gate level feature 7001 maintain design rule spacing requirements with gate level features 7002 and 7003 defined within adjacent gate level feature layout channel 70-5B. Similarly, gate level features 7002 25 7008 are defined within their respective gate level feature layout channels, and have their gate electrode portions substantially centered upon the gate electrode track corresponding to their respective gate level feature layout channel. Also, it should be appreciated that each of gate level features 7002-7008 maintains design rule spacing requirements with gate level features defined within adjacent gate level feature layout channels, and avoids physical contact with 30 any another gate level feature defined within adjacent gate level feature layout channels. [001731 A gate electrode corresponds to a portion of a respective gate level feature that extends over a diffusion structure, i.e., over a diffusion fin, wherein the respective gate level feature is defined in its entirety within a gate level feature layout channel. Each gate level feature is defined within its gate level feature layout channel without physically contacting WO 2013/106799 PCT/US2013/021345 39 another gate level feature defined within an adjoining gate level feature layout channel. As illustrated by the example gate level feature layout channels 70-5A through 70-5E of Figure 70B, each gate level feature layout channel is associated with a given gate electrode track and corresponds to a layout region that extends along the given gate electrode track and 5 perpendicularly outward in each opposing direction from the given gate electrode track to a closest of either an adjacent gate electrode track or a virtual gate electrode track outside a layout boundary. [001741 Some gate level features may have one or more contact head portions defined at any number of locations along their length. A contact head portion of a given gate level feature 10 is defined as a segment of the gate level feature having a height and a width of sufficient size to receive a gate contact structure. In this instance, "width" is defined across the substrate in a direction perpendicular to the gate electrode track of the given gate level feature, and "height" is defined across the substrate in a direction parallel to the gate electrode track of the given gate level feature. The gate level feature width and height may or may not correspond to the 15 cell width W and cell height H, depending on the orientation of the gate level features within the cell. It should be appreciated that a contact head of a gate level feature, when viewed from above, can be defined by essentially any layout shape, including a square or a rectangle. Also, depending on layout requirements and circuit design, a given contact head portion of a gate level feature may or may not have a gate contact defined thereabove. 20 1001751 A gate level of the some embodiments disclosed herein is defined as a restricted gate level, as discussed above. Some of the gate level features form gate electrodes of transistor devices. Others of the gate level features can form conductive segments extending between two points within the gate level. Also, others of the gate level features may be non functional with respect to integrated circuit operation. It should be understood that the each of 25 the gate level features, regardless of function, is defined to extend across the gate level within their respective gate level feature layout channels without physically contacting other gate level features defined with adjacent gate level feature layout channels. [001761 In some embodiments, the gate level features are defined to provide a finite number of controlled layout shape-to-shape lithographic interactions which can be accurately 30 predicted and optimized for in manufacturing and design processes. In this embodiment, the gate level features are defined to avoid layout shape-to-shape spatial relationships which would introduce adverse lithographic interaction within the layout that cannot be accurately predicted and mitigated with high probability. However, it should be understood that changes in WO 2013/106799 PCT/US2013/021345 40 direction of gate level features within their gate level layout channels are acceptable when corresponding lithographic interactions are predictable and manageable. [001771 It should be understood that each of the gate level features, regardless of function, is defined such that no gate level feature along a given gate electrode track is 5 configured to connect directly within the gate level to another gate level feature defined along a different gate electrode track without utilizing a non-gate level feature. Moreover, each connection between gate level features that are placed within different gate level layout channels associated with different gate electrode tracks is made through one or more non-gate level features, which may be defined in higher interconnect levels, i.e., through one or more 10 interconnect levels above the gate level, or by way of local interconnect features at or below the gate level. [001781 Figures 71A/B through 77A/B show a number of example SDFF circuit layouts that utilize both tri-state and transmission gate based cross-coupled circuit structures, in accordance with some embodiments of the present invention. Figure 71C shows a circuit 15 schematic for Figures 71A/B and 77A/B, in accordance with some embodiments of the present invention. Figure 72C shows a circuit schematic for Figures 73A/B through 76A/B, in accordance with some embodiments of the present invention. Figures 71B-77B show the same layouts as Figures 71A-77A, respectively, with the layouts depicted in a merged format for clarity, and with the nodes of the circuit identified based on the cell layout's circuit schematic. 20 The example SDFF circuit layouts of Figures 71A/B through 77A/B include the following features: 1. Gate conductors: a. Substantially evenly spaced gate conductors. b. Uniform gate conductor line end gaps formed with cut mask, combined with 25 large gate conductor line end gaps to avoid local interconnect, or if there is sufficient space to permit larger gate conductor line end gaps that do not require cuts. c. Some gate conductors used as wires in some instances to reduce metal usage, i.e., to reduce higher level interconnect usage. 30 2. Diffusion fins: a. Substantially evenly spaced diffusion fins. b. Diffusion fins omitted between p-type and n-type, and on top and bottom cell edges.
WO 2013/106799 PCT/US2013/021345 41 c. Diffusion fin width-to-space relationship may vary, or may have a substantially equal relationship such as depicted in the examples of Figures 71A/B through 77A/B. 3. Local interconnect: 5 a. Local interconnect structures can connect directly to diffusion fins and gate conductors. b. Local interconnect structures can connect to metal 1 (met1 or Ml) through a contact layer. c. Horizontal and vertical local interconnect structures, such as shown in Figures 10 76A/B by way of example, can be fabricated using separate design layers, i.e., fabricated using separate mask layers. d. Horizontal and vertical local interconnect structures can be on the same layer, i.e., on the same mask layer, as shown in the examples of Figures 71A/B through 75A/B and 77A/B. Also, during manufacturing, the horizontal and 15 vertical local interconnect structures can be fabricated in two distinct steps, or in a single step. e. Local interconnect structures can have positive, zero, or negative overlap with diffusion fins and gate conductors. f. Vertical local interconnect can be on similar pitch as gate conductor with half 20 pitch offset from gate conductors. 4. Contacts: a. Contacts can be defined to connect local interconnect structures to metal 1 (metI or M1). b. Local interconnect structures can have positive, zero, or negative overlap on 25 contact. c. Metal I metall or M1) can have positive, zero, or negative overlap on contact. 5. Metal 2 (met2 or M2) a. Metal 2 structures can be uni-directional, i.e., linear-shaped, in some embodiments. 30 b. Metal 2 structures can extend in horizontal (x) and/or vertical (y) directions. [001791 The example SDFF circuit layout of Figures 71 A/B shows the following features, among others: * Metal 2 is not used for internal wiring. " Metal 2 is used for power rails.
WO 2013/106799 PCT/US2013/021345 42 " Tri-state and transmission gate cross-coupled transistor structures are utilized. " Local interconnect structures extend in both horizontal (x) and vertical (y) directions. " Some gate conductors are used as wires, and do not form a gate electrode of a transistor. 5 0 Gate conductor cuts are provided in various locations and combinations. * Gate conductor cuts are uniform in size. " Gate conductor layer is fully populated, i.e., at least one gate conductor is positioned at each available gate conductor pitch position within the cell. [001801 The example SDFF circuit layout of Figures 72A/B shows the following 10 features, among others: " Metal 2 structures are used for internal wiring in vertical (y) direction. " Denser circuit layout than the example of Figures 71A/B. * Both tri-state and transmission gate cross-coupled transistor structures are utilized. * Gate conductor layer is fully populated, i.e., at least one gate conductor is positioned at 15 each available gate conductor pitch position within the cell. " Gate conductor cuts are shown. * Substantially uniform gate conductor cuts are utilized in various combinations and/or locations to optimize layout. 1001811 The example SDFF circuit layout of Figures 73A/B shows a version of the 20 SDFF circuit that uses both the gate conductor and metal 2 layers for vertical (y-direction) wiring. The example SDFF circuit layout of Figures 74A/B shows a version of the SDFF circuit that uses horizontally oriented, i.e., in the x-direction, metal 2 structures for internal wiring. The example SDFF circuit layout of Figures 75A/B shows an alternate version of the SDFF circuit that again uses horizontally oriented, i.e., in the x-direction, metal 2 structures for 25 internal wiring. The example SDFF circuit layout of Figures 76A/B shows a variation of the layout of Figure 72A/B with horizontal local interconnect and vertical local interconnect used as separate conductors to allow for removal of the internal metal 2 conductors. The example SDFF circuit layout of Figures 77A/B shows a partial SDFF layout illustrating an alternate way to define circuit structures so as to minimize use of metal 2 and maximize transistor density. 30 [001821 It should be understood based on the circuit layouts and description provided herein that in some embodiments one or more of the following features can be utilized: * a separation distance between co-aligned and adjacently positioned diffusion fin ends (i.e., diffusion fin cut distance) can be less than a size of the gate electrode pitch, WO 2013/106799 PCT/US2013/021345 43 e a vertical local interconnect structure may overlap a diffusion fin (that is horizontally oriented) on one edge (horizontally oriented edge) of the diffusion fin; in this case, some cuts (in a cut mask) used to separate vertical local interconnect structures can be defined to touch or overlap a diffusion fin, 5 e a horizontal local interconnect structure may overlap a gate electrode structure (that is vertically oriented) on one edge (vertically oriented edge) of the gate electrode structure, * a size of a gate end cap (i.e., a distance by which a gate electrode structure extends beyond an underlying diffusion fin) can be less than a size of one or more diffusion fin 10 pitches, or less than a size of an average diffusion fin pitch, * a separation distance between co-aligned and adjacently positioned gate electrode structure ends (i.e., gate electrode structure cut distance) can be less than or equal to a size of one or more diffusion fin pitches, or less than a size of an average diffusion fin pitch, 15 * a lengthwise centerline separation distance between adjacently positioned n-type and p type diffusion fins (as measured in the direction perpendicular to the diffusion fins) can be defined as an integer multiple of one or more diffusion fin pitches, or as an integer multiple of an average diffusion fin pitch. [001831 In an example embodiment, a semiconductor device includes a substrate, a first 20 transistor, and a second transistor. The first transistor has a source region and a drain region within a first diffusion fin. The first diffusion fin is structured to project from a surface of the substrate. The first diffusion fin is structured to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The second transistor has a source region and a drain region within a second diffusion fin. The second diffusion fin is 25 structured to project from the surface of the substrate. The second diffusion fin is structured to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Also, either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first 30 diffusion fin. [001841 The above-mentioned first and second transistors can be located at different positions in the second direction. Also, each of the first and second transistors can be a three dimensionally gated transistor.
WO 2013/106799 PCT/US2013/021345 44 [001851 The above-mentioned first transistor includes a first linear-shaped gate electrode structure that extends lengthwise in a second direction perpendicular to the first direction as viewed from above the substrate. The above-mentioned second transistor includes a second linear-shaped gate electrode structure that extends lengthwise in the second direction 5 perpendicular to the first direction as viewed from above the substrate. At least one of the first and second ends of the first diffusion fin can be positioned in the first direction between the first and second linear-shaped gate electrode structures. And, at least one of the first and second ends of the second diffusion fin can be positioned in the first direction between the first and second linear-shaped gate electrode structures. The first linear-shaped gate electrode 10 structure is positioned next to and spaced apart from the second linear-shaped gate electrode structure. [001861 The semiconductor device can also include a linear-shaped local interconnect structure that extends in the second direction and that is positioned between the first and second linear-shaped gate electrode structures. The linear-shaped local interconnect structure 15 can be substantially centered in the first direction between the first and second linear-shaped gate electrode structures. The linear-shaped local interconnect structure can connect to one or more of the first and second diffusion fins. [001871 The semiconductor device can also include a linear-shaped local interconnect structure that extends in the first direction and that is positioned between the first and second 20 diffusion fins. This linear-shaped local interconnect structure can be substantially centered in the second direction between the first and second diffusion fins. Also, this linear-shaped local interconnect structure can connect to one or more of the first and second gate electrode structures. [001881 The above-mentioned linear-shaped local interconnect structure that extends in 25 the first direction can be referred to as a first linear-shaped local interconnect structure. The semiconductor device can also include a second linear-shaped local interconnect structure that extends in the second direction and that is positioned between the first and second linear shaped gate electrode structures. The second linear-shaped local interconnect structure can be substantially centered in the first direction between the first and second linear-shaped gate 30 electrode structures. Also, the second linear-shaped local interconnect structure can connect to one or more of the first diffusion fin, the second diffusion fin. Additionally, in some embodiments, the first linear-shaped local interconnect structure can be a first linear segment of a two-dimensionally varying non-linear local interconnect structure, and the second linear shaped local interconnect structure can be a second linear segment of the two-dimensionally WO 2013/106799 PCT/US2013/021345 45 varying non-linear local interconnect structure. And, in some instances, the first and second linear-shaped local interconnect structures can be connected to each other. [001891 The semiconductor device can also include a contact structure positioned between the first and second diffusion fins. In some embodiments, the contact structure can be 5 substantially centered between the first and second diffusion fins. In some embodiments, the contact structure can connect to either the first gate electrode structure or the second gate electrode structure. [001901 The semiconductor device can also include a contact structure positioned between the first and second gate electrode structures. In some embodiments, the contact 10 structure can be substantially centered between the first and second gate electrode structures. Also, in some embodiments, the semiconductor device can include a conductive interconnect structure positioned in the second direction between first and second diffusion fins, where the contact structure connects to the conductive interconnect structure. In some embodiments, the conductive interconnect structure is a lowest level interconnect structure extending in the first 15 direction that is not a diffusion fin. [001911 The semiconductor device can also include a conductive interconnect structure positioned in the first direction between first and second diffusion fins, where the contact structure connects to a conductive interconnect structure. In some embodiments, the conductive interconnect structure is higher-level interconnect structure. 20 [001921 The semiconductor device can also include one or more interconnect structures, where some of the one or more interconnect structures include one or more interconnect segments that extend in the first direction. In some embodiments, some of the one or more interconnect segments that extend in the first direction are positioned between the first and second diffusion fins. Also, in some embodiments, some of the one or more interconnect 25 segments that extend in the first direction are positioned over either the first diffusion fin or the second diffusion fin. In some embodiments, the one or more interconnect segments that extend in the first direction are positioned in accordance with a second direction interconnect pitch as measured in the second direction between respective first direction oriented centerlines of the one or more interconnect segments. 30 [001931 In some embodiments, the first and second diffusion fins can be positioned in accordance with a diffusion fin pitch as measured in the second direction between respective first direction oriented centerlines of the first and second diffusion fins, where the second direction interconnect pitch is a rational multiple of the diffusion fin pitch, with the rational multiple defined as a ratio of integer values.
WO 2013/106799 PCT/US2013/021345 46 [001941 In some embodiments, each of the first and second diffusion fins is centerline positioned in accordance with either a first diffusion fin pitch as measured in the second direction or a second diffusion fin pitch as measured in the second direction, where the first and second diffusion pitches successively alternate in the second direction, and where an 5 average diffusion fin pitch is an average of the first and second diffusion fin pitches, and [001951 where the second direction interconnect pitch is a rational multiple of the average diffusion fin pitch, with the rational multiple defined as a ratio of integer values. In some embodiments, the first diffusion fin pitch is equal to the second diffusion fin pitch. In some embodiments, the first diffusion fin pitch is different than the second diffusion fin pitch. 10 [001961 The above-mentioned one or more interconnect structures can include either a local interconnect structure, a higher-level interconnect structure, or a combination thereof, where the local interconnect structure is a lowest level interconnect structure that is not a diffusion fin, and where the higher-level interconnect structure is an interconnect structure formed at a level above the local interconnect structure relative to the substrate. 15 [001971 In some embodiments, each of the first and second diffusion fins is centerline positioned in accordance with either a first diffusion fin pitch as measured in the second direction or a second diffusion fin pitch as measured in the second direction, where the first and second diffusion pitches successively alternate in the second direction, and where an average diffusion fin pitch is an average of the first and second diffusion fin pitches. Also, the 20 one or more interconnect segments that extend in the first direction can be centerline positioned in accordance with either a first interconnect pitch as measured in the second direction or a second interconnect pitch as measured in the second direction, where the first and second interconnect pitches successively alternate in the second direction, and where an average interconnect pitch is an average of the first and second interconnect pitches. Also, the 25 average interconnect pitch is a rational multiple of the average diffusion fin pitch, with the rational multiple defined as a ratio of integer values. [001981 In some embodiments, the first diffusion fin pitch is equal to the second diffusion fin pitch, and the first interconnect pitch is equal to the second interconnect pitch. In some embodiments, the first diffusion fin pitch is different than the second diffusion fin pitch, 30 and the first interconnect pitch is different than the second interconnect pitch. In some embodiments, the first diffusion fin pitch is equal to the first interconnect pitch, and the second diffusion fin pitch is equal to the second interconnect pitch. [001991 The semiconductor device can also include one or more interconnect structures, where some of the one or more interconnect structures include one or more interconnect WO 2013/106799 PCT/US2013/021345 47 segments that extend in the second direction. In some embodiments, some of the one or more interconnect segments that extend in the second direction are positioned between the first and second gate electrode structures. In some embodiments, some of the one or more interconnect segments that extend in the second direction are positioned over either the first gate electrode 5 structure or the second gate electrode structure. 1002001 In some embodiments, the one or more interconnect segments that extend in the second direction are positioned in accordance with a first direction interconnect pitch as measured in the first direction between respective second direction oriented centerlines of the one or more interconnect segments. Also, the first and second gate electrode structures can be 10 positioned in accordance with a gate electrode pitch as measured in the first direction between respective second direction oriented centerlines of the first and second gate electrode structures. The first direction interconnect pitch can be a rational multiple of the gate electrode pitch, with the rational multiple defined as a ratio of integer values. 1002011 The above-mentioned one or more interconnect structures can include either a 15 local interconnect structure, a higher-level interconnect structure, or a combination thereof, where the local interconnect structure is a lowest level interconnect structure that is not a diffusion fin, and where the higher-level interconnect structure is an interconnect structure formed at a level above the local interconnect structure relative to the substrate. [002021 In some embodiments, the semiconductor device can also include a first 20 plurality of transistors each having a respective source region and a respective drain region formed by a respective diffusion fin. Each diffusion fin of the first plurality of transistors is structured to project from the surface of the substrate. Each diffusion fin of the first plurality of transistors is structured to extend lengthwise in the first direction from a first end to a second end of the respective diffusion fin. The first ends of the diffusion fins of the first plurality of 25 transistors are substantially aligned with each other in the first direction. [002031 Also, the semiconductor device can include a second plurality of transistors each having a respective source region and a respective drain region formed by a respective diffusion fin. Each diffusion fin of the second plurality of transistors is structured to project from the surface of the substrate. Each diffusion fin of the second plurality of transistors is 30 structured to extend lengthwise in the first direction from a first end to a second end of the respective diffusion fin. The first ends of the diffusion fins of the second plurality of transistors are substantially aligned with each other in the first direction. And, one or more of the first ends of the diffusion fins of the second plurality of transistors are positioned in the first WO 2013/106799 PCT/US2013/021345 48 direction between the first and second ends of one or more of the diffusion fins of the first plurality of transistors. 1002041 In some embodiments, each of the first ends of the diffusion fins of the second plurality of transistors is positioned in the first direction between the first and second ends of 5 one or more of the diffusion fins of the first plurality of transistors. In some embodiments, at least one of the diffusion fins of the second plurality of transistors is positioned next to and spaced apart from at least one diffusion fin of the first plurality of transistors. Also, in some embodiments, the first plurality of transistors can include either n-type transistors, p-type transistors, or a combination of n-type and p-type transistors, and the second plurality of 10 transistors can include either n-type transistors, p-type transistors, or a combination of n-type and p-type transistors. In some embodiments, the first plurality of transistors are n-type transistors and the second plurality of transistors are p-type transistors. [002051 In some embodiments, the first and second pluralities of diffusion fins are positioned to have their respective first direction oriented centerlines substantially aligned to a 15 diffusion fin alignment grating defined by a first diffusion fin pitch as measured in the second direction and a second diffusion fin pitch as measured in the second direction. The first and second diffusion fin pitches occur in an alternating sequence in the second direction. Also, in some embodiments, the diffusion fins of the first and second pluralities of transistors collectively occupy portions at least eight consecutive alignment positions of the diffusion fin 20 alignment grating. [002061 In an example embodiment, a method of fabricating a semiconductor device is disclosed. The method includes providing a substrate. The method also includes forming a first transistor on the substrate, such that the first transistor has a source region and a drain region within a first diffusion fin, and such that the first diffusion fin is formed to project from a 25 surface of the substrate, and such that the first diffusion fin is formed to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The method also includes forming a second transistor on the substrate, such that the second transistor has a source region and a drain region within a second diffusion fin, and such that the second diffusion fin is formed to project from the surface of the substrate, and such that the 30 second diffusion fin is formed to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, and such that the second diffusion fin is formed at a position next to and spaced apart from the first diffusion fin. Also, the first and second transistors are formed such that either the first end or the second end of the WO 2013/106799 PCT/US2013/021345 49 second diffusion fin is formed at a position in the first direction between the first end and the second end of the first diffusion fin. [002071 It should be understood that any circuit layout incorporating finfet transistors as disclosed herein can be stored in a tangible form, such as in a digital format on a computer 5 readable medium. For example, a given circuit layout can be stored in a layout data file, and can be selectable from one or more libraries of cells. The layout data file can be formatted as a GDS II (Graphic Data System) database file, an OASIS (Open Artwork System Interchange Standard) database file, or any other type of data file format suitable for storing and communicating semiconductor device layouts. Also, multi-level layouts of a cell incorporating 10 finfet transistors as disclosed herein can be included within a multi-level layout of a larger semiconductor device. The multi-level layout of the larger semiconductor device can also be stored in the form of a layout data file, such as those identified above. [002081 Also, the invention described herein can be embodied as computer readable code on a computer readable medium. For example, the computer readable code can include a 15 layout data file within which a layout of a cell incorporating finfet transistors as disclosed herein is stored. The computer readable code can also include program instructions for selecting one or more layout libraries and/or cells that include finfet transistors as disclosed herein. The layout libraries and/or cells can also be stored in a digital format on a computer readable medium. 20 [002091 The computer readable medium mentioned herein is any data storage device that can store data which can thereafter be read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. Multiple computer readable media distributed 25 within a network of coupled computer systems can also be used to store respective portions of the computer readable code such that the computer readable code is stored and executed in a distributed fashion within the network. [002101 In an example embodiment, a data storage device has computer executable program instructions stored thereon for rendering a layout of a semiconductor device. The data 30 storage device includes computer program instructions for defining a first transistor to be formed on a substrate, such that the first transistor is defined to have a source region and a drain region within a first diffusion fin, and such that the first diffusion fin is defined to project from a surface of the substrate, and such that the first diffusion fin is defined to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the WO 2013/106799 PCT/US2013/021345 50 first diffusion fin. The data storage device also includes computer program instructions for defining a second transistor to be formed on the substrate, such that the second transistor is defined to have a source region and a drain region within a second diffusion fin, and such that the second diffusion fin is defined to project from the surface of the substrate, and such that the 5 second diffusion fin is defined to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, and such that the second diffusion fin is defined to be positioned next to and spaced apart from the first diffusion fin, and such that the second diffusion fin is defined to have either its first end or its second end positioned in the first direction between the first end and the second end of the first diffusion 10 fin. [00211] It should be further understood that any circuit layout incorporating finfet transistors as disclosed herein can be manufactured as part of a semiconductor device or chip. In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on a semiconductor 15 wafer. The wafer includes integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions and/or diffusion fins are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by 20 dielectric materials. [002121 While this invention has been described in terms of several embodiments, it will be appreciated that those skilled in the art upon reading the preceding specifications and studying the drawings will realize various alterations, additions, permutations and equivalents thereof. Therefore, it is intended that the present invention includes all such alterations, 25 additions, permutations, and equivalents as fall within the true spirit and scope of the invention. What is claimed is:

Claims (53)

1. A semiconductor device, comprising: a substrate; a first transistor having a source region and a drain region within a first diffusion fin, 5 the first diffusion fin structured to project from a surface of the substrate, the first diffusion fin structured to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin; a second transistor having a source region and a drain region within a second diffusion fin, the second diffusion fin structured to project from the surface of the substrate, the second 10 diffusion fin structured to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, the second diffusion fin positioned next to and spaced apart from the first diffusion fin, wherein either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin. 15
2. A semiconductor device as recited in claim 1, wherein the first and second transistors are located at different positions in the second direction.
3. A semiconductor device as recited in claim 1, wherein each of the first and second transistors is a three-dimensionally gated transistor.
4. A semiconductor device as recited in claim 1, wherein the first transistor 20 includes a first linear-shaped gate electrode structure that extends lengthwise in a second direction perpendicular to the first direction as viewed from above the substrate, and wherein the second transistor includes a second linear-shaped gate electrode structure that extends lengthwise in the second direction perpendicular to the first direction as viewed from above the substrate, 25 wherein at least one of the first and second ends of the first diffusion fin is positioned in the first direction between the first and second linear-shaped gate electrode structures, and wherein at least one of the first and second ends of the second diffusion fin is positioned in the first direction between the first and second linear-shaped gate electrode structures. 30
5. A semiconductor device as recited in claim 4, wherein the first linear-shaped gate electrode structure is positioned next to and spaced apart from the second linear-shaped gate electrode structure.
6. A semiconductor device as recited in claim 4, further comprising: a linear-shaped local interconnect structure that extends in the second direction and that WO 2013/106799 PCT/US2013/021345 52 is positioned between the first and second linear-shaped gate electrode structures.
7. A semienductor device as recited in claim 6, wherein the linear-shaped local interconnect structure is substantially centered in the first direction between the first and second linear-shaped gate electrode structures. 5
8. A seiconductor device as recited in claim 6, wherein the linear-shaped local interconnect structure connects to one or more of the first and second diffusion fins.
9. semiconductor device as recited in claim 4, further comprising: a linear-shaped local interconnect structure that extends in the first direction and that is positioned between the first and second diffusion fins.
10 10. A semiconductor device as recited in claim 9, wherein the linear-shaped local interconnect structure is substantially centered in the second direction between the first and second diffusion fins.
11. A semiconductor device as recited in claim 9, wherein the linear-shaped local interconnect structure connects to one or more of the first and second gate electrode structures. 15
12. A semiconductor device as recited in claim 9, wherein the linear-shaped local interconnect structure is a first linear-shaped local interconnect structure, the semiconductor device further including a second linear-shaped local interconnect structure that extends in the second direction and that is positioned between the first and second linear-shaped gate electrode structures. 20
13. A semiconductor device as recited in claim 12, wherein the second linear shaped local interconnect structure is substantially centered in the first direction between the first and second linear-shaped gate electrode structures.
14. A semiconductor device as recited in claim 12, wherein the second linear shaped local interconnect structure connects to one or more of the first diffusion fin, the second 25 diffusion fin.
15. A semiconductor device as recited in claim 12, wherein the first linear-shaped local interconnect structure is a first linear segment of a two-dimensionally varying non-linear local interconnect structure, and wherein the second linear-shaped local interconnect structure is a second linear segment of the two-dimensionally varying non-linear local interconnect 30 structure.
16. A semiconductor device as recited in claim 15, wherein the first and second linear-shaped local interconnect structures are connected to each other.
17. A semiconductor device as recited in claim 4, further comprising: a contact structure positioned between the first and second diffusion fins. WO 2013/106799 PCT/US2013/021345 53
18. A semiconductor device as recited in claim 17, wherein the contact structure is substantially centered between the first and second diffusion fins.
19. A semiconductor device as recited in claim 18, wherein the contact structure connects to either the first gate electrode structure or the second gate electrode structure. 5
20. A semiconductor device as recited in claim 4, further comprising: a contact structure positioned between the first and second gate electrode structures.
21. A semiconductor device as recited in claim 20, wherein the contact structure is substantially centered between the first and second gate electrode structures.
22. A semiconductor device as recited in claim 20, further comprising: 10 a conductive interconnect structure positioned in the second direction between first and second diffusion fins, wherein the contact structure connects to the conductive interconnect structure.
23. A semiconductor device as recited in claim 22, wherein the conductive interconnect structure is a lowest level interconnect structure extending in the first direction 15 that is not a diffusion fin.
24. A semiconductor device as recited in claim 20, further comprising: a conductive interconnect structure positioned in the first direction between first and second diffusion fins, wherein the contact structure connects to a conductive interconnect structure. 20
25. A semiconductor device as recited in claim 22, wherein the conductive interconnect structure is higher-level interconnect structure.
26. A semiconductor device as recited in claim 4, further comprising: one or more interconnect structures, wherein some of the one or more interconnect structures include one or more interconnect segments that extend in the first direction. 25
27. A semiconductor device as recited in claim 26, wherein some of the one or more interconnect segments that extend in the first direction are positioned between the first and second diffusion fins.
28. A semiconductor device as recited in claim 26, wherein some of the one or more interconnect segments that extend in the first direction are positioned over either the first 30 diffusion fin or the second diffusion fin.
29. A semiconductor device as recited in claim 26, wherein the one or more interconnect segments that extend in the first direction are positioned in accordance with a second direction interconnect pitch as measured in the second direction between respective first direction oriented centerlines of the one or more interconnect segments. WO 2013/106799 PCT/US2013/021345 54
30. A semiconductor device as recited in claim 29, wherein the first and second diffusion fins are positioned in accordance with a diffusion fin pitch as measured in the second direction between respective first direction oriented centerlines of the first and second diffusion fins, and 5 wherein the second direction interconnect pitch is a rational multiple of the diffusion fin pitch, the rational multiple defined as a ratio of integer values.
31. A semiconductor device as recited in claim 29, wherein each of the first and second diffusion fins is centerline positioned in accordance with either a first diffusion fin pitch as measured in the second direction or a second diffusion fin pitch as measured in the 10 second direction, wherein the first and second diffusion pitches successively alternate in the second direction, and wherein an average diffusion fin pitch is an average of the first and second diffusion fin pitches, and wherein the second direction interconnect pitch is a rational multiple of the average diffusion fin pitch, the rational multiple defined as a ratio of integer values. 15
32. A semiconductor device as recited in claim 31, wherein the first diffusion fin pitch is equal to the second diffusion fin pitch.
33. A semiconductor device as recited in claim 31, wherein the first diffusion fin pitch is different than the second diffusion fin pitch.
34. A semiconductor device as recited in claim 26, wherein the one or more 20 interconnect structures include either a local interconnect structure, a higher-level interconnect structure, or a combination thereof, wherein the local interconnect structure is a lowest level interconnect structure that is not a diffusion fin, and wherein the higher-level interconnect structure is an interconnect structure formed at a level above the local interconnect structure relative to the substrate. 25
35. A semiconductor device as recited in claim 26, wherein each of the first and second diffusion fins is centerline positioned in accordance with either a first diffusion fin pitch as measured in the second direction or a second diffusion fin pitch as measured in the second direction, wherein the first and second diffusion pitches successively alternate in the second direction, and wherein an average diffusion fin pitch is an average of the first and 30 second diffusion fin pitches, and wherein the one or more interconnect segments that extend in the first direction are centerline positioned in accordance with either a first interconnect pitch as measured in the second direction or a second interconnect pitch as measured in the second direction, wherein the first and second interconnect pitches successively alternate in the second direction, and WO 2013/106799 PCT/US2013/021345 55 wherein an average interconnect pitch is an average of the first and second interconnect pitches, wherein the average interconnect pitch is a rational multiple of the average diffusion fin pitch, the rational multiple defined as a ratio of integer values. 5
36. A semiconductor device as recited in claim 35, wherein the first diffusion fin pitch is equal to the second diffusion fin pitch, and the first interconnect pitch is equal to the second interconnect pitch.
37. A semiconductor device as recited in claim 35, wherein the first diffusion fin pitch is different than the second diffusion fin pitch, and the first interconnect pitch is different 10 than the second interconnect pitch.
38. A semiconductor device as recited in claim 35, wherein the first diffusion fin pitch is equal to the first interconnect pitch, and the second diffusion fin pitch is equal to the second interconnect pitch.
39. A semiconductor device as recited in claim 4, further comprising: 15 one or more interconnect structures, wherein some of the one or more interconnect structures include one or more interconnect segments that extend in the second direction.
40. A semiconductor device as recited in claim 39, wherein some of the one or more interconnect segments that extend in the second direction are positioned between the first and second gate electrode structures. 20
41. A semiconductor device as recited in claim 39, wherein some of the one or more interconnect segments that extend in the second direction are positioned over either the first gate electrode structure or the second gate electrode structure.
42. A semiconductor device as recited in claim 39, wherein the one or more interconnect segments that extend in the second direction are positioned in accordance with a 25 first direction interconnect pitch as measured in the first direction between respective second direction oriented centerlines of the one or more interconnect segments.
43. A semiconductor device as recited in claim 42, wherein the first and second gate electrode structures are positioned in accordance with a gate electrode pitch as measured in the first direction between respective second direction oriented centerlines of the first and second 30 gate electrode structures, and wherein the first direction interconnect pitch is a rational multiple of the gate electrode pitch, the rational multiple defined as a ratio of integer values.
44. A semiconductor device as recited in claim 39, wherein the one or more interconnect structures include either a local interconnect structure, a higher-level interconnect WO 2013/106799 PCT/US2013/021345 56 structure, or a combination thereof, wherein the local interconnect structure is a lowest level interconnect structure that is not a diffusion fin, and wherein the higher-level interconnect structure is an interconnect structure formed at a level above the local interconnect structure relative to the substrate. 5
45. A semiconductor device as recited in claim 1, further comprising: a first plurality of transistors each having a respective source region and a respective drain region formed by a respective diffusion fin, each diffusion fin of the first plurality of transistors structured to project from the surface of the substrate, each diffusion fin of the first plurality of transistors structured to extend lengthwise in the first direction from a first end to a 10 second end of the respective diffusion fin, wherein the first ends of the diffusion fins of the first plurality of transistors are substantially aligned with each other in the first direction, a second plurality of transistors each having a respective source region and a respective drain region formed by a respective diffusion fin, each diffusion fin of the second plurality of transistors structured to project from the surface of the substrate, each diffusion fin of the 15 second plurality of transistors structured to extend lengthwise in the first direction from a first end to a second end of the respective diffusion fin, wherein the first ends of the diffusion fins of the second plurality of transistors are substantially aligned with each other in the first direction, and wherein one or more of the first ends of the diffusion fins of the second plurality of 20 transistors are positioned in the first direction between the first and second ends of one or more of the diffusion fins of the first plurality of transistors.
46. A semiconductor device as recited in claim 45, wherein each of the first ends of the diffusion fins of the second plurality of transistors is positioned in the first direction between the first and second ends of one or more of the diffusion fins of the first plurality of 25 transistors.
47. A semiconductor device as recited in claim 46, wherein at least one of the diffusion fins of the second plurality of transistors is positioned next to and spaced apart from at least one diffusion fin of the first plurality of transistors.
48. A semiconductor device as recited in claim 45, wherein the first plurality of 30 transistors includes either n-type transistors, p-type transistors, or a combination of n-type and p-type transistors, and wherein the second plurality of transistors includes either n-type transistors, p-type transistors, or a combination of n-type and p-type transistors.
49. A semiconductor device as recited in claim 45, wherein the first plurality of WO 2013/106799 PCT/US2013/021345 57 transistors are n-type transistors and the second plurality of transistors are p-type transistors.
50. A semiconductor device as recited in claim 45, wherein the first and second pluralities of diffusion fins are positioned to have their respective first direction oriented centerlines substantially aligned to a diffusion fin alignment grating defined by a first diffusion 5 fin pitch as measured in the second direction and a second diffusion fin pitch as measured in the second direction, where the first and second diffusion fin pitches occur in an alternating sequence in the second direction.
51. A semiconductor device as recited in claim 50, wherein the diffusion fins of the first and second pluralities of transistors collectively occupy portions at least eight consecutive 10 alignment positions of the diffusion fin alignment grating.
52. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a first transistor on the substrate, the first transistor having a source region and a drain region within a first diffusion fin, the first diffusion fin formed to project from a surface 15 of the substrate, the first diffusion fin formed to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin; forming a second transistor on the substrate, the second transistor having a source region and a drain region within a second diffusion fin, the second diffusion fin formed to project from the surface of the substrate, the second diffusion fin formed to extend lengthwise 20 in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, the second diffusion fin formed at a position next to and spaced apart from the first diffusion fin, wherein either the first end or the second end of the second diffusion fin is formed at a position in the first direction between the first end and the second end of the first diffusion fin. 25
53. A data storage device having computer executable program instructions stored thereon for rendering a layout of a semiconductor device, comprising: computer program instructions defining a first transistor to be formed on a substrate, the first transistor defined to have a source region and a drain region within a first diffusion fin, the first diffusion fin defined to project from a surface of the substrate, the first diffusion fin 30 defined to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin; computer program instructions defining a second transistor to be formed on the substrate, the second transistor defined to have a source region and a drain region within a second diffusion fin, the second diffusion fin defined to project from the surface of the WO 2013/106799 PCT/US2013/021345 58 substrate, the second diffusion fin defined to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, the second diffusion fin defined to be positioned next to and spaced apart from the first diffusion fin, the second diffusion fin defined to have either its first end or its second end positioned in the first 5 direction between the first end and the second end of the first diffusion fin.
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