WO2006090445A1 - Semiconductor circuit device, and method for manufacturing the semiconductor circuit device - Google Patents

Semiconductor circuit device, and method for manufacturing the semiconductor circuit device Download PDF

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Publication number
WO2006090445A1
WO2006090445A1 PCT/JP2005/002908 JP2005002908W WO2006090445A1 WO 2006090445 A1 WO2006090445 A1 WO 2006090445A1 JP 2005002908 W JP2005002908 W JP 2005002908W WO 2006090445 A1 WO2006090445 A1 WO 2006090445A1
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Prior art keywords
wiring
tankomi
substrate
connected
silicon
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PCT/JP2005/002908
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French (fr)
Japanese (ja)
Inventor
Hidenobu Fukutome
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Fujitsu Limited
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Priority to PCT/JP2005/002908 priority Critical patent/WO2006090445A1/en
Publication of WO2006090445A1 publication Critical patent/WO2006090445A1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28132Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743Making of internal connections, substrate contacts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

To provide a semiconductor integrated circuit device, which has components of a fin-type FET suited for a high integration LSI and formed on a supporting substrate and which uses wires buried in trenches of the supporting substrate for connecting the components, and a method for manufacturing the semiconductor integrated circuit device. The semiconductor integrated circuit device comprises a MOS transistor element or the fin-type FET having a stereoscopic isolation area of silicon formed on a supporting substrate and a gate electrode formed on the surface of the stereoscopic isolation area of silicon, buried wires buried in trenches formed in self-alignment in the stereoscopic isolation area of silicon of the supporting substrate, and on-substrate wires on the supporting substrate. The MOS transistor elements are connected by the buried wires and the on-subsrate wires.

Description

Specification

The method of manufacturing a semiconductor circuit device and a semiconductor circuit device

Technical field

[0001] The present invention is suitable for high integration LSI, a semiconductor integrated circuit device and a manufacturing method thereof as a component of the fin-type FET formed on a supporting substrate. In particular, for connect between components, a method for manufacturing a semiconductor integrated circuit device 及 patron using the embedded groove in the support substrate wiring.

BACKGROUND

[0002] In today's highly integrated LSI is composed of a vast number logic macrocell. Thus, because of the improvements in LSI, the power integration of LSI has been required which, as a demand for miniaturization of the logic macrocell. Here, the logic macrocells, NOT circuit, a logic circuit such as a NAND circuit, a result of the circuit layout is patterned, in which the cells of. Therefore, reduction of the logic macrocell is their components

MOSFET (Metal

Toko filtrate by Oxide Semiconductor Field- Effect-Transistor) reduction in the size of the device is large.

Incidentally, the size reduction of the MOSFET, the increase in current between the source and the drain when the MOSFET cutoff, and are expected to decrease in the driving current of the active in Banre ,, size reduction and next-generation performance compatibility between the maintenance of improvement was difficult. Therefore, as an area for MOSFET, isolated in the insulating supporting substrate, three-dimensional region (hereinafter, referred to as "fin region") of the silicon (Si) provided, except for the surface of the Fin region in contact with the insulating support substrate, structure of a MOSFET disposing a gate electrode on the band state (hereinafter, referred to as "fin type FET") is being adopted. By isolate the area for MOSFET, is because it is possible to reduce the current between the source and the drain due to the substrate. Also, more placing the gate electrode in a band state is because it blocks the current path between the source and the drain in the surface of the fm region. Furthermore, since it is possible to use as side also current path steric Fin region, because the driving current of the fm-type FET is increased. [0003] Therefore, a reduction in the size of the logic circuit, in order to achieve both the maintenance of the performance improvement, configured LSI has been proposed by the logic circuit using a Fin-FET on the supporting substrate. For example, Patent Document 1, using the fm-type FET, a processor constructed in accordance with the conventional logic circuit is described. Hereinafter, with reference to FIG. 1, using a fin type FET, the processor configured by a conventional logic circuit will be described. Processor 1 of Figure 1 comprises at least one chip 2, the chip 2 has a logic circuit 3 on its surface. These mouth logic circuit 3 includes a fm-type FET 4. The processor 1 is configured logic circuit 3 by the interconnect child.

Thus, the logic circuit 3 is used in the processor 1 of Figure 1, due to the use of fm type FET, reduction of the logic circuit 3 is achieved. Also, high integration of the processor 1 of Figure 1 is realized.

Patent Document 1: JP 2004-266274

Disclosure of the Invention

Problems that the Invention is to you'll solve

[0004] and forces, and, reduction of the layout area of ​​the logic macrocells, only reduction in size of the MOSFET device is left to Ru problem largely on the structure and arrangement of the wiring connecting between circuit elements Nag.

The present invention utilizes the embedded groove in the support substrate wiring, by making connections between circuit elements, thereby the reduction of the layout area, and an object thereof is to provide a semiconductor circuit device. Further, the present invention aims that you provide a method for manufacturing the semiconductor integrated circuit device.

Here, examples of construction and the arrangement of wiring for connecting the circuit elements prevent the reduction in layout area of ​​the logic macrocell, there is less.

First, when wiring MOSFET devices together can not exchange difference wirings belonging to the same wiring layer. Further, in the same wiring layer, the minimum wiring width and the wiring interval also need to be maintained. Thus, the logic macrocells, avoiding exchange difference wirings belonging to the same wiring layer, it is necessary to become a problem to ensure a wiring region for connecting the circuit elements. Meanwhile, in order to solve the above problems, it is conceivable to use two wiring layers, connection between the wiring of the circuit element and the wiring layers, or, between the first layer wiring and the second layer wiring it is necessary to secure a positioning region for connection, not necessarily a problem not follow the reduction of the logic macrocell.

Furthermore, the pattern shape of the wiring for connecting the circuit elements, Oite the photolithography process, it is also required to be resolved easily shaped. When the pattern shape of the wiring is peg shape was resolved, in consideration of this point, if enlarging a space wiring pattern Narazu, there is a problem that can not be ensured reduction of logic macrocells.

Moreover, today, an interlayer insulating film of the wiring on the substrate tends to be thinner, inter-wire capacitance of the first wiring layer and the second layer wiring, there is a problem that can not be reduced. Then, since that would avoid proximity of the first layer wiring and the second layer wiring, a problem which can not be ensured reduction of logic macrocells. It means for solving the problems

[0005] In order to solve the above problems, a first invention, a wiring for connecting circuit elements of the fin-FET or the like formed on the support substrate, which is the fm-type FET and a self-aligning manner supported to provide a semiconductor circuit device, which comprises using a Tankomi wirings written Tanme the groove base in the plate.

That is, the first invention comprises a MOS transistor device having a gate electrode formed on the surface of the solid isolated areas of the silicon formed on the supporting substrate and the solid isolated region, Tan groove before SL in the support substrate and Tankomi wirings written order, to provide a semiconductor device and a substrate on the support substrate wiring. Then. The semiconductor device is characterized in that a connection is made between the MOS transistor device using said Tankomi wiring on the board wiring. The above Tankomi wiring is solid isolated area self-aligned manner above the MOSFET device les, is Rukoto Shi desired les.

[0006] In order to solve the above problem, the second invention is a semiconductor device according to the first invention, aligning Tankomi wired to the first direction, on the substrate wiring, the first direction aligning a second direction perpendicular to a semiconductor circuit device according to claim to.

That is, the second invention is a semiconductor circuit device according to the first invention, said buried lines arranged in a first direction, the connection portion of the circuit elements connected by the substrate wiring, the second direction, that provide a semiconductor circuit device which is characterized in that the linearly arranged. The first and second directions mentioned above, it is desirable to orthogonal.

[0007] To solve the above problems, a third invention is a method of manufacturing a semiconductor circuit device according to the first invention or second invention, fm type FET and a self-aligned manner buried forming a wiring groove, to provide a manufacturing method of a semiconductor circuit device, which comprises forming a self-aligned manner Tankomi wiring.

That is, the third invention is a method of manufacturing a semiconductor circuit device according to the first invention or second invention, wherein the solid isolated region forming step of forming the solid isolated region of the MOS transistor device a groove forming step of forming a three-dimensional isolated area and groove self-aligned with the buried wiring in the support substrate, and the buried step of writing sputum Me a Tankomi material with silicon and the etching selectivity force to the Tankomi wiring trench the MOS transistor and the gate electrode formation step that form the gate electrode of the element, the removal of the embedding material Tankomi wiring groove, Tanme included a metallic material into the Tankomi wiring trench, the Tankomi and Tankomi wiring forming step of forming the wiring, to provide a method of manufacturing a semiconductor circuit device and a substrate on the wiring forming step of forming the substrate wiring. Note that the embedding material is silicon and etching selectivity, Shi desired silicon 'gate Noremaniumu (SiGe) is Rere.

(Effect of the invention)

[0008] In the first aspect of the invention, after forming the fin-type FET formed on a supporting substrate, using a Fin-FET as E Tsuchingumasuku, grooves for Tankomi wiring is formed. Then, since it is wiring between the circuit elements by using two wiring layers of Tankomi wiring and substrate wiring, compared to performing connection in the same wiring layer, the intersection of lines belonging to the same wiring layer avoid, it is not necessary to secure a wiring region for connecting the circuit elements. Further, in a self-aligned manner, since the positional relationship between the fin-type FET and Tankomi wiring are determined, it is not necessary to take the area of ​​Me other alignment between the fin-type FET and buried interconnection. Further, an interlayer insulating film between the embedded wiring and substrate wiring thicker than the interlayer insulating film between the first wiring and the second wiring on the substrate, the reduction of inter-wiring capacitance. Then, it is possible to close the Tankomi wiring and substrate wiring. Accordingly, thereby to provide a reduction the semiconductor circuit device.

[0009] In the second invention, since placing the Tankomi wire in the first direction can be the minimum interval the arrangement interval of Tankomi wiring and the Fin FET. Further, since the aligned connection points of the circuit elements to be connected by a second substrate on the wiring in the direction perpendicular to the first direction may be a linear shape of the substrate on the wiring. Further, when arranging in parallel on a board wiring, and can be arranged on the substrate wiring minimum interval. Furthermore, in the case of forming a circuit pattern by photolithography one, if it is linear pattern, the pattern is likely to be resolved. Therefore, further than the semiconductor circuit device according to the first invention, thereby to provide a reduction the semiconductor circuit device.

[0010] Further, in the third invention, the Tankomi wiring groove is formed in a self-aligned manner, once, writes silicon 'Genore Maniumu the (SiGe) Tan Me. Then, thereafter, process steps heat treatment is applied, if example embodiment, it is possible to form the gate electrode of the fin FET is Porishinkon layer. After completion of the heat treatment Kuwawa that process step, and removing the silicon 'germanium (SiGe) from the groove for buried wiring, by writing Tanme a metal material Tankomi wiring trench, forming a buried wiring There kill in. Therefore, after embedded wiring formation, heat treatment heat stress is not generated in the Nag Tankomi wiring to participate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] [FIG 1] FIG 1 is a diagram illustrating a processor constructed in accordance with a conventional logic circuit.

[2] Not circuit a fin type FET was circuitry according to Figure 2 Example 1, Nand circuit, and a diagram showing a circuit layout of a logic macrocell of Nor circuit.

[3] FIG. 3 has a fin type FET circuit elements, illustrates a circuit layout of an SRAM macrocell storage circuit and cell Norei spoon of SRAM according to the second embodiment.

[4] FIG. 4 has a fin type FET as a circuit element, and feature for using the shared contact, the circuit-les Iauto of SRAM Macrocells cells the memory circuit of the SRAM according to Embodiment 3 It illustrates.

[5] FIG 5 is a shows a flow chart of manufacturing steps of the logic macrocells, or SRAM macrocell.

FIG. 6 is, 6A, 6B, 6C, FIG. 6D, FIG. 6E and are composed of FIG 6F, a diagram showing the detailed steps in manufacturing fin type region forming step.

[7] FIG. 7 is a diagram 7G, FIG. 7H, 71, 7], Figure 7K, and are configured Figure 7L force et a diagram showing the details of groove forming step for buried wiring is there. [8] FIG. 8 is a diagram 8M, Figure 8N, FIG. 80, FIG. 8P, Figure 8Q and are composed of FIG 8R, is a diagram showing the details of groove forming step for Tankomi wire.

[9] FIG. 9 is a diagram 9R, FIG 9S, FIG 9T, FIG 9U, Figure 9V, and are composed of FIG 9W, the details of Tankomi wiring step and board wiring formation step (Part 1) it is a diagram showing.

[10] FIG 10 is a diagram 10R, FIG 10SS, FIG 10TT, FIG 10UU, FIG 10VV, and has been consists of 10 stomach, Tankomi wiring step and board wiring formation step (Part 2) is a diagram showing the details.

[11] FIG 11 is a diagram 11XX, FIG 11YY and are composed of FIG 11ZZ, is a diagram showing the details of Tankomi wiring step and board wiring formation step (2).

BEST MODE FOR CARRYING OUT THE INVENTION

[0012] Hereinafter, Embodiment 1 of the present invention, Example 2, Example 3, and Example 1 to be described for Example 4

[0013] (Not circuit, Nand circuit, and, in the Nor circuits, logic Makurosenore with fm type FET) in Figure 2, Not circuits in which the fin-type FET according to the first embodiment and the circuit element, Nand circuit and, Nor shows the circuit layout of the logic macrocells of the circuit. It should be noted, fin means "fin fish", initially, fm area had meant a three-dimensional space to defeat the triangular prism next. However, in today, fm region is used in its sense including isolated stereoscopic region of rectangular parallelepiped, and the like. Also, the fm-type FET, isolated in the insulating support substrate, a three-dimensional fin region of silicon (Si) for MOSFET provided, except for the face of the fin region in contact with the insulating support substrate, strip-shaped gate electrode refers to a MOSFET be placed.

[0014] upper and lower part of FIG. 2A is a circuit pattern of a logic macrocells Not circuits using embedded wiring and the wiring on the board to connect the circuit elements.

In the upper Not circuit of FIG. 2A, 5 is a substrate on the wiring that connects to the positive power supply, 6 P Chiyane Honoré fin type FET, 7 is an N-channel fm type FET, 8 on the substrate to be connected to the input terminal wiring 9 substrate wiring connected to the output terminal, 10 on the substrate to be connected to a ground power source wiring, 11 Tankomi wiring, 13 denotes a contact Via respectively. Incidentally, the substrate wiring 5, 8, 9, 10, also always, it may be not a wiring belonging to a single wiring layer. For example, the substrate wiring 5 is connected to the board wiring 10 and the positive power source connected to the ground power supply, it belongs to the second wiring layer, on the substrate to connect to the board wiring 8 and the output terminal is connected to the input terminal wiring 9 Les, is good even if it belongs to the first wiring layer.

Then, the substrate wiring 5 to be connected to the drain and the positive power of the P-channel fin type FET6 is connected via a con tact Vial3. The source of the P-channel fm type FET 6, the drain of N-channel fin type FET 7, and board wiring 9 connected to the output terminal is connected via a contact Vial3. The gate electrodes of the N-channel fin type FET7 of P-channel fin type FET 6, and is connected via the embedded wiring 11 and the contact Vial3. The board wiring 8 connecting the buried wiring 11 to the input terminal are connected via a contact Vial3. The source of the N Channel fin type FET7 includes a substrate on the wiring 10 connected to the ground power supply, through a contact Via23, are connected.

Therefore, the P-channel fin type FET6 and N-channel fm type FET 7, and between the positive power supply and a ground power supply are connected in series, not circuits, i.e., to form an inverter circuit. Upper not circuit of Figure 2, the output from the output terminal a logic signal having a logic signal with inverted logic which receives at the input terminal.

The upper circuit layout of Figure 2A, Tankomi wiring 11 and the substrate wiring 5, 8, 9, 10 and the interlayer insulating layer of, for that would include the circuit elements such as fm type FET, the substrate wiring 5, 8, 9, 10 thicker than the insulating layer of the plurality of wiring layers forming the. Therefore, the wiring capacity between the embedded wiring 11 and the substrate wiring 5, 8, 9, 10, on the substrate wiring 5, 8, 9, 10 from the wiring capacitance of the plurality of wiring layers forming a small.

In the lower Not circuit layout of Figure 2A, 15 is a substrate on the wiring that connects to the positive power source, 16 P-channel fin type FET, 17 is N-channel fm type FET, 18 on the substrate to be connected to the input terminal wiring 19 board wiring connected to the output terminal, 20 denotes a substrate on the wiring that connects to the ground power supply, 21 is embedded wiring, 23 denotes a contact Via, 24 is a wire-bonding region, respectively. Incidentally, board on the wiring 15, 18, 19, 20 is not necessarily belong to the same wiring layer, there Rukoto force S belonging to a plurality of wiring layers are the same as the circuit layout of the upper part of FIG. 2A.

The connection relationship of each component is the same as the upper Not circuit of Figure 2A. The functions of the lower Not circuit of Figure 2 A is also similar to the function of the upper Not circuit of Figure 2A. However, the gate electrodes of the N-channel fm type FET17 of P-channel f ln type FET 16, the force is connected via a buried interconnection 21 S, without passing through the contact Via23, the buried wiring 21 each different in that it connects through a direct wiring connection area 24 and the gate electrode of the fm-type FET. Further, as the embedded wiring 21 and the board wiring 19 intersect in an orthogonal state, the embedded wiring 21, P-channel fin type FET16 contact source via23 and, the drain of N-channel fin type FET17 contact v ia23 is also different in that it is arranged. In addition, N-channel fin type

And FET17 and P-channel fm type FET 16, in the point is embedded wiring 21 is self-aligned manner different. Accordingly, the gate electrode of Tankomi wiring and fm-type FET, and it is possible to omit the region for alignment with fm region of Tankomi wiring and fin type FET. Further, Tankomi wiring 21 and the substrate wiring 15, 18, 19, 20 becomes linear, the resolution of a pattern when forming a pattern by photolithography techniques is facilitated. Further, it becomes possible placement as to overlap the buried wiring 21 and the board wiring 19. Then, compared with the layout area of ​​the upper Not circuit of FIG. 2A, the layout area of ​​the lower Not circuit of Figure 2 A is miniaturized.

Upper and lower part of FIG. 2B is a pattern of a logic macrocells Nand circuits using Tankomi wiring and wiring on the board to connect the circuit elements.

In the layout of the upper Nand circuit of FIG. 2B, 25 denotes a substrate on the wiring that connects to the positive power supply, 26, 33 connected to P-channel fm type FET, 27, 34 is N-channel fm type FET, 28 input terminal 1 substrate wiring, 36 denotes a substrate on the wiring connected to the input terminal 2, 29 on the substrate to be connected to the output terminal wiring 30 on the substrate to be connected to a ground power source wiring, 31, 35 Tankomi wiring, 38 denotes a substrate upper wire, 39 denotes a contact Via respectively. The substrate on the wiring 25, 28, 36, 29, 30 is not necessarily belong to the same wiring layer, a point that may belong to a plurality of wiring layers are the same as the circuit layout of the upper part of FIG. 2A.

The drain of the P-channel fin type FET26 via the contact Via39, connected to the board wiring 25 to connect to the positive supply. The source of the P-channel fin type FET26 via the board wiring 29 to be connected to the contact Via39 an output terminal, the drain of N-channel fin type FET 27, connected to the source of P-channel f ln type FET 33. The gate electrode of the P-channel fm type FET26 via Tankomi wiring 31 and the contact Via39, the gate electrode of the N-channel fm type FET 27, and is connected to the board wiring 28 connected to the input terminal 1. The gate electrode of the P-channel fin type FET33, through the embedded wiring 35 and the contact Via39, connected to the board wiring 36 connected to the gate electrodes and the input terminal 2 of the N-channel fm type FET 34. Drain of P-channel fin type FET33 are connected via the board wiring 25 and the contact Via39 connected to the positive supply. The drain of the N Channel fin type FET34 via the board wiring 38 and the contact Via39, connected to the source of N-channel fin type FET 27. The source of N-channel fm type FET34 is connected to the board wiring 30 connected to the ground power supply by via contacts Via39.

[0017] That is, P-channel fin type FET 26, 33 is connected in parallel between the drain of the board wiring 25 and N Channel-type fin-type FET 27 to be connected to a positive power supply, N-channel fin type FET 27, 34 are connected in series between the board wiring 30 connected to the source and the ground power supply of P-channel fm type FET 26, 33. Thus, a P-channel fm type FET 26, 33, N-channel fin type FET 27, 34 is a so-called constitute a nand circuit. Further, the upper Nand circuit of FIG. 2B, the input pin 1, the logical signal input from the input terminal 2, the inversion of the logical product (Iwaruyu, nand) a logic signal indicating, from the output terminal Output.

[0018] In the lower Nand circuit of FIG. 2B, 40 denotes a substrate on the wiring that connects to the positive power supply, 41, 48 connected to the P-channel fin type FET, 42, 49 are N-channel fm type FET, 43 is an input terminal 1 substrate wiring, 56 is a substrate on the wiring connected to the input terminal 2, 44 on the substrate to be connected to the output terminal wiring 45 on the substrate to be connected to a ground power source wiring, 46, 50 is embedded wiring, 53 denotes a substrate upper wire, 54 denotes a contact Via, 55 denotes a wire-bonding region, respectively. The connection relationship of each component is the same as the Nand circuit of the upper of Figure 2B. The functions of the lower Nand circuit of Figure 2B is also the same as the function of the upper Nand circuit of Figure 2B.

[0019] However, the gate electrodes of the N-channel fm type FET42 of P-channel fm type FET 41, are connected through a buried line 21, without passing through the contact Via54, respectively buried wiring 21 of the gate electrode of the fin-type FET varies with Les, Ru point connected directly in wire-bonding region 55. Gate electrodes of the gate electrode and the N-channel fin type FET49 of P-channel fin type FET48 is connected via the Tankomi wiring 50, not via the contact Via54, the gate of each of the fin-type FET and Tankomi wiring 50 the electrode differs in that it connects directly in the wiring connection area 55. Tankomi As the wiring 46 and the upper substrate layer wiring 47 intersect in an orthogonal state, the contact of the source of Tankomi lines 46, P-channel fin type FET41 Via54, N-channel fm type

Drain contacts Via54 the FET 42, and, different sources of contacts Via54 of P Chiyanenore fm type FET48 is disposed les, Ru in terms.

Further, a P-channel fin type FET41 and N-channel fm type FET 42, differ in the Tankomi wiring 46 is self-aligned manner. Further, a P-channel fin type FET48 and N-channel fin type FET 49, sputum write wiring 50 is different in that it is self-aligned.

[0020] Thus, the gate electrode of Tankomi wiring and fm-type FET, and it is possible to omit the region for alignment with fm region of Tankomi wiring and fin type FET. Further, Tankomi wiring 43, 50 and the substrate wiring 40, 43, 44, 45, 53, 56 becomes linear, the resolution of the pattern when that form a pattern by a photolithography technique is facilitated. Further, the embedded wiring 46 and the board wiring 44 becomes possible arranged so heavy. Then, compared with the layout area of ​​the upper Nand circuit of FIG. 2B, the layout area of ​​the lower Nand circuit of Figure 2B is miniaturized.

[0021] upper and lower part of FIG. 2C is a pattern of a logic macrocells Nor circuits using Tankomi wiring and wiring on the board to connect the circuit elements.

In the upper Nor circuit of Figure 2C, 57a is a substrate on the wiring that connects to the positive power supply, 57 b, 63 are P-channel fin type FET, 57c, 64 are N-channel fin type FET, 58 on the substrate to be connected to the input terminal 1 wiring 66 on the substrate to be connected to the input terminal 2 lines, 59 on a base plate connected to the output terminal wiring 60 on the substrate to be connected to a ground power source wiring, 61, 65 embedded wiring 67 on the substrate wiring , 69 denotes a contact Via respectively. The substrate on the wiring 57a, 58, 66, 59, 60, 67 are not necessarily belong to the same wiring layer, a point that may belong to a plurality of wiring layers are the same as the circuit layout of the stage on the Figure 2A .

[0022] The drain of the P-channel fm type FET57b is connected to the board wiring 57a to be connected to a positive supply via a contact Via69. The gate electrode of the P-channel fm type FET57b through the embedded wiring 61 and the contact Via69, are connected to the board wiring 58 to connect to the gate electrode and an input terminal 2 of the N-channel fin type FET57C. The source of the P-channel fin type FET57b via the wiring 67 and the contact Via69 substrate is connected to the drain of the P-channel fin type FET 63. The source of the P-channel fin type FET63 is, N-channel fm-type drain of FET57c through the board wiring 59 and contactor preparative Via69 connected to the output terminal, and is connected to the drain of N-channel fm type FET 64. The gate electrode of the P-channel fin type FET63 through the embedded wiring 65 and contactor preparative Via69, connected to the base plate on the wiring 66 connected to the gate electrode and an input terminal 2 of the N-channel fin type FET64 les, Ru. The source of the source and the N-channel fin type FET64 of N-channel fin type FET57 is connected to the board wiring 60 to be connected to the ground power supply. That, N-channel fin type FET57 and N-channel fin type FET64 are connected in parallel between the source and the substrate wiring 60 is connected to the ground power source P-channel fin type FET 63. Further, P-channel fin type FET56 and P-channel fm type FET63 are connected in series between the drain of the board wiring 55 to be connected to the positive power supply N Channel fin type FET57 and N-channel fin type FET 64. Thus, N-channel fm type FET 57, N-channel fin type FET 64, P-channel fm type FET 56, 及 Beauty, the P-channel fin type FET63 constitute a so-called nor circuit. Then, an inverted signal of the logical sum of the upper of the NOT circuit is inputted from the substrate wiring 66 which connects the board wiring 58 to be connected to the input terminal 1 to the input terminal 2 logic signal Figure 2C, the output from the output terminal to.

[0023] In the lower Nor circuit of FIG. 2C, 70 is a substrate on the wiring that connects to the positive power supply, 71, 78 connected to the P-channel fm type FET, 72, 79 are N-channel fm type FET, 73 is an input terminal 1 substrate wiring, 81 on the substrate to be connected to the input terminal 2 lines, 74 on the substrate to be connected to the output terminal wiring 75 on the substrate to be connected to a ground power source wiring, 76, 80 is embedded wiring, 77 denotes a substrate upper wire, 82 wire-bonding region, 83 denotes a contact Via respectively. Incidentally, the substrate wiring 70, 73, 81, 74, 75, 77 may not necessarily belong to the same wiring layer, a point that may belong to a plurality of wiring layers are the same as the circuit layout of the upper part of FIG. 2A.

The connection relationship of each component are the same as Nor circuit of the upper of Figure 2C. The functions of the lower Nor circuit of Figure 2C is also similar to the function of the upper Nor circuit of Figure 2C.

[0024] However, the gate electrodes of the N-channel fm type FET72 of P-channel fin type FET 71, are connected via a buried interconnection 76, not via the contact Via83, respectively buried wiring 76 of the gate electrode of the fin-type FET connected directly in the wiring connection area 82. The gate electrode of the gate electrode and the N-channel fin type FET79 of P-channel fin type FET78 is connected via a Tankomi wiring 80 les, but not through the contact Via83, fm type their respective and Tankomi wiring 80 It is connected directly to the wire-bonding region 82 and the gate electrode of the FET. As the board wiring 74 to be connected to the buried wiring 80 output terminals intersect in an orthogonal state, Tankomi wiring 80, P-channel fin type source contact Via83 of FET 78, N contacts drain channel fm type FET 72 Via83 and, source contact Via83 of N-channel fin type FET79 is arranged. Further, a P-channel fm type FET71 and N-channel fin type FET 72, the embedded wiring 76 is self-aligned manner. Further, P-channel fin type FET78 and N-channel fin type

And FET79, Tankomi wiring 80 is a self-aligned manner.

Accordingly, the gate electrode of Tankomi wiring and fin type FET, and it is possible to omit the space for positioning the fin region of the buried wiring and fin type FET. Also, the embedded wiring 76, 80 and the substrate wiring 70, 73, 74, 75, 77, 81 becomes linear, the resolution of a pattern when forming a pattern by photolithography techniques is facilitated. Furthermore, it is possible to arranged such that the embedded wiring 80 and the substrate wiring 74 overlap.

Therefore, compared with the layout area of ​​the upper Nor circuit of Figure 2C, the layout area of ​​the lower Nor circuit of FIG. 2C reduction has been les, Ru.

According to Example 1, 2A, 2B and, according to the circuit pattern shown in the upper part of FIG. 2C, an interlayer insulating film between Tankomi wiring and substrate wiring becomes thick to include the fin-type FET. Accordingly, the capacitance between Tankomi wiring and substrate wiring, than the capacity of the wiring layers board wiring belongs, to decline. Then, and the embedded wiring and the substrate-like wiring is not necessary to avoid to close. Further, according to Embodiment 1, 2A, 2B and, according to the circuit pattern shown in the lower part of FIG. 2C Tankomi wiring, the silicon formed on fin area (supporting substrate of each fin type FET because it is self-aligned manner with solid independent area), ensuring alignment area between the fin region and Tankomi wiring is not necessary.

Moreover, it aligned the direction Tankomi wires are wired, to so that Do board wiring is a linear, contact via a respective fm type FET are arranged. Thus, in the formation of the board wiring pattern, thereby facilitating the resolution of the pattern. Then, it is possible to reduce the distance of the substrate on the wiring pattern.

Further, the wiring direction and the substrate strip lines are orthogonal buried wiring and buried wiring and substrate wiring is such that there is the intersection, Tankomi wiring and substrate wiring is disposed. Therefore, it is possible to superimpose arrangement of wiring.

From the above, according to Embodiment 1, 2A, 2B and, according to the circuit pattern shown in Figure 2C, attained is reduction of the logic macrocell.

Example 2 [0026] (SRAM macro cell using a Fin FET)

3 has a fin type FET circuit elements, illustrates a circuit layout of an SRAM macrocell storage circuit was Serui spoon of SRAM according to the second embodiment. Then, 3A, 3B, 3C and,, and a FIG. 3D.

Figure 3A is a circuit showing a portion of a SRAM storage element. In one part of the SRAM storage element of FIG. 3A, 85, 86 are inverters, 87 denotes an input terminal, 88 is an output terminal, to indicate, respectively. Then, one inverter inverts amplification logic signal input from the input terminal 87, an output signal from the output terminal. The other inverter, a logic signal having an inverted logic of the output terminal or al, further inverted amplified Keru force feed back to the input terminal 87 side. That is, the logic of the logic signal from the input terminal 87, a part of the SRAM storage element has a function of storing.

[0027] Figure 3B is a diagram showing a circuit layout including a fin type FET constituting a part of the SRAM storage element of FIG. 3A, a buried wiring and substrate wiring to connect the the fin type FET . In Fig. 3B, 90 denotes a substrate on the wiring that connects to the positive power supply, 91, 93 P-channel fin type FET, 92, 94 are N-channel fin type FET, 95, 96 is Tankomi wiring 97 is the ground power supply board wiring for connecting, 98 on the substrate to be connected to the input terminal wiring 99 on the substrate to be connected to the output terminal wiring, 100 denotes a contact Via respectively.

The above substrate wiring 90, 97, 98, 99 are not necessarily required to be composed of a wiring layer of single layer. For example, the substrate on the wiring 99 to connect to the substrate on the wiring 98 and the output terminal connected to the input terminal on the substrate to be connected to the board wiring 90 及 beauty ground power supply connected board wiring of the first layer, the positive power supply wire 97 may be configured plurality of wiring layers force such that the substrate on the wiring of the second layer.

The gate electrode of the P-channel fin type FET91 is connected to the gate electrode of the N-channel fm type FET92 through the embedded wiring 95 and the contact VialOO, Tankomi wiring 95, board wiring 98 connected to the input terminal and, , through a contact VialOO, connecting the source of P-channel fin type FET93, 及 beauty, the drain of N-channel fin type FET 94. Drain of P-channel fin type FET91 Les connected to the board wiring 90 connected to the positive supply, Ru. Source of P-channel fin type FET91 via the wiring 99 and the contact vialOO substrate connected to the output terminal, connected to the drain of N-channel fin type FET 92, the substrate on the wiring 99 connected to the output terminal, the embedded wiring 96, and, via the contact VialOO, connected to the gate electrode of the gate electrode and the N-channel fin type FET94 of P-channel fin type FET93. Drain of P-channel fin type FET93 via the contact VialOO, connected to the board wiring 90 connected to the positive supply. N-channel fin type

The source of FET94 will be connected to the board wiring 97 to be connected to the ground power supply through a contact VialOO. The source of N-channel fm type FET92 is connected to the board wiring 97 to connect to the ground power supply through a contact VialOO.

[0028] Thus, the P-channel fin type FET91 and N-channel fm type FET 92, and between the positive power supply and a ground power supply are connected in series, not circuits, i.e., to form an inverter circuit.

The P-channel f ln type FET93 and N-channel fin type FET 94, and between the positive power supply and a ground power supply are connected in series, not circuits, i.e., to form an inverter circuit. As a result, as described in FIG. 3A, the entire circuit, which have a function similar to that of the portion of the storage element of the SRAM.

Here, in the circuit layout of FIG. 3B, because the will contain the circuit elements such as fin-type FET, Tankomi wiring 95, 96 and the board wiring 90, 97, 98, 99 and the interlayer insulating layer of the substrate upper wire 90, 97, 98, thicker than the insulating layer of the plurality of wiring layers constituting 99. Thus, the embedded wiring 95, 96 and the substrate wiring 90, 97, 98, the wiring capacitance between 99 board wiring 90, 97, 98, 99 than the wiring capacitance of the plurality of wiring layers forming a small les, .

[0029] Figure 3C is a diagram showing a circuit layout including a fm-type FET constituting a part of the SRAM storage element of FIG. 3A, a buried wiring and substrate wiring to connect the the fm-type FET point, FIG. 3 B and from forming a part of the pattern in manner fin region and a self-alignment of the fin-type FET of a force Tankomi wiring similar, and, the connection of the gate electrode and Tankomi wires fm type FET a different circuit layouts in that connecting without using the contact Via.

[0030] In FIG. 3C, 105 is a substrate on the wiring that connects to the positive power supply, 106, 107 P-channel fm type FET, 108, 109 are N-channel fin type FET, 110 on the substrate to be connected to a ground power source wiring, 111 the substrate to be connected to the output terminal wiring, 112 denotes a substrate on the wiring connected to the input terminal, 113 contactors Via, 114 are wire-bonding region, 115, 116, 117, 118 a Tankomi wiring respectively. Incidentally, the point of the substrate on the wiring 105, 110, 111, 112 belong to a plurality of substrates on the wiring layer is the same as the circuit layout of FIG. 3B.

The drain of the P-channel fin type FET106 is connected to the board wiring 105 to be connected to a positive supply via a contact vial 13. The gate electrode of the P-channel fin type FET106 via Umakomihai line 115 is connected to one end of the gate electrode of the N-channel fm type FET 108. The other end of the N-channel fin type FET108 is buried interconnection 117, substrate wiring 112 connected to the input terminal and, via a contact vial 13, the source and N Channel fin-type P-channel fin type FET 107 FET 109 It is connected to the drain. The source of the P-channel fm type FET106 through the board wiring 111 connected to the output terminal, connected to the drain of N-channel fm type FET 108, further, the substrate on the wiring 111 connected to the output terminal, the contact via and, through the embedded wiring 116 is connected to one end of the gate electrode of the P-channel fin type FET 107. The other end of the gate electrode of the P-channel fin type FET107 via Tankomi wiring 118, N-channel fm type

Connected to the gate electrode of the FET 109. Drain of P-channel fm type FET107 is connected to the board wiring 105 to be connected to a positive supply via a contact Via. Source of N-channel fm type FET108 via the contact Via, connected to the board wiring 110 connected to the ground power supply. The source of the N Chiyane Honoré fin type FET109 via the contact Via, connected to the board wiring 110 connected to the ground power supply.

[0031] In the circuit layout of FIG. 3C, a part of the pattern of the embedded wiring for forming the self-aligned manner and fin regions of fm type FET, it can be reduced interval fm type FET and buried interconnection.

Further, when the connection of the gate electrode and Tankomi wire fin type FET, since connected not through a contact via, among alignment region, a gate electrode and the contact via the fm-type FET, and the position of the buried wiring and contact via it is possible to omit the region combined.

Moreover, aligning the fin region of the buried wiring and fin type FET in one direction, and, as board wiring becomes linear, since by arranging the contact Via, by photolithography and foremost, when forming a pattern, the pattern go up the resolution. As a result, it is possible to reduce the distance between the patterns.

Therefore, compared to the circuit layout of FIG. 3B, it is possible to reduce the layout area.

[0032] Figure 3D point is a diagram showing a circuit layout including a fm-type FET constituting a part of the SRAM memory elements, a buried wiring and substrate wiring to connect the fm-FET of Figure 3A is similar to Figure 3B, a contact time of a point to a pattern of Tankomi wirings forms fin region and a self-aligned manner form of fin type FET, and connects the gate electrode and Tankomi wires fm type FET Via which is a different circuit layouts in that connection without intervention. Furthermore, when comparing the circuit layout of FIG. 3C, except that the formation of the entire pattern of Tankomi wiring fin region in self-alignment with the fin-type FET.

In Figure 3D, 120 is a substrate on the wiring that connects to the positive power supply, 121, 122 P-channel fin type FET, 123, 124 are N-channel fin type FET, 125 on the substrate to be connected to a ground power source wiring, 126 denotes an output terminal substrate wiring connected to, 127 board wiring connected to the input terminal, 128 is a contact Via, 129 are wire-bonding region, 130, 131 denotes a Tankomi wiring. Incidentally, the board wiring 120, 125, 126, 127 is a point that belongs to the plurality of substrate interconnection layers is the same as the circuit layout of FIG. 3B.

Then, in FIG. 3D, a gate electrode of each fm type FET, the source of each fin type FET, the drain of each fin type FET, an input terminal, and connects the output terminal, connection between the embedded wiring and the substrate wiring is the same as the connection relationship in Figure 3B. However, that each fm type FET 121, 122, 123, 124 gate electrode and Tankomi wires 130, 131 connect, not through the contact Vial28, a direct connection in the Rooster himself line connection region 129, have been made different. Further, except that the wiring 130 embedded with respect to fm region of each fm type FET, 131 are formed in a self-aligned manner. Further, the substrate on the wiring 127 connected to the board wiring 126 and the input terminal connected to the output terminal such that the straight line, Ntakuto Vial28 differ also in that they are disposed. In addition, it is arranged so that the board wiring 126 connected to the output terminal and Tankomi wiring 130 intersect, board wiring 127 connected to the input terminal and Tankomi wiring 131 is arranged so as to intersect different in that it is.

Note that constitutes the inverter and the P-channel fin type FET121 and N-channel fm type FET 123, it is similar to FIG. 3B where the P-channel f ln type FET122 and N-channel fin type FET124 constituting the inverter. Further, P-channel fin type FET 121, 122, and, N-channel fin type

FET 123, 124 is also the same that forms a part of the SRAM storage element.

According to Embodiment 2, 3B, 3C and, according to the circuit pattern shown in FIG. 3D, an interlayer insulating film between Tankomi wiring and substrate wiring becomes thick to include the fin-type FET. Accordingly, the capacitance between buried wiring and substrate wiring, than the capacity of the substrate on the wiring layers board wiring belongs, it decreases. Then, and the embedded wiring and the substrate-like wiring is not necessary to avoid to close. Further, according to Embodiment 2, FIG. 3C, and, according to the circuit pattern shown in FIG. 3D embedded wiring, and fm area of ​​each fin type FET (solid independent area of ​​silicon formed on a support substrate) Self aligned manner by which, because, ensuring alignment region between fm region and the buried wiring is not required.

Moreover, it aligned the direction that are wired in Tankomi wiring in so that Do board wiring is a linear, contact via the position of each fm type FET are arranged. Therefore, in the form configuration of the pattern, thereby facilitating the resolution of the pattern. Then, it is possible to reduce the distance of the wiring pattern on the substrate wiring.

Further, the wiring direction and the substrate strip lines are orthogonal buried wiring and buried wiring and substrate wiring is such that there is the intersection, Tankomi wiring and substrate wiring is disposed. Therefore, the wiring is overlapped arranged.

From the above, according to Embodiment 2, 3B, 3C and, according to the circuit pattern shown in FIG. 3D, attained is reduction of the logic macrocell.

Example 3

[0034] (Yore ,, and the fm-type FET, SRAM macro cell using a shared contact in the contact Via)

Figure 4 has a fm-type FET as a circuit element, characterized by using the Xue ard contact a diagram showing a circuit Reia © bets SRAM Macrocells cells the memory circuit of the SRAM according to Embodiment 3 is there. Then, FIGS. 4A, 4B, 4C and,, and a FIG. 4D. Figure 4A is a circuit showing a portion of a SRAM storage element. In one part of the SRAM storage element of FIG. 4A, 130, 131 are inverters, 132 denotes an input terminal, 133 is a substrate connected to the output terminal wiring respectively.

Then, in FIG. 4A, operation of the circuit shown a portion of a SRAM storage element, and the function is similar to the circuit showing a portion of an SRAM memory device of FIG. 3A.

[0035] Figure 4B is a circuit layout including a fm-type FET constituting a part of the SRAM storage element of FIG. 4A, and a buried wiring and substrate wiring to connect the the fin-type FET, a portion in is a diagram showing a circuit layout characterized by using the share one de contact.

Similar to Figure 3C, that the part of the pattern of the embedded wirings forms fm region and self-aligned manner form of fm type FET, and, upon connection of the gate electrode and Tankomi wires fm type FET, through the contact via a circuit layout with a feature in that connection without further a circuit layout characterized by using a shared contact.

[0036] In FIG. 4B, 135 denotes a substrate on the wiring that connects to the positive power supply, 136, 137 P-channel fin type FET, 138, 139 are N-channel fin type FET, 140 on the substrate to be connected to a ground power source wiring, 141 substrate wiring connected to the output terminal 142 on the substrate to be connected to the input terminal wiring, 143 denotes a contact Via, 144 are wire-bonding region, 145, 146, 147, 148 embedded wiring, the share one de Contacts 149 It is shown, respectively. The above substrate wiring 135, 140, 141, 142 necessarily, need not be configured wiring layers force of one layer. For example, the input terminal to the connection board wiring 141 to be connected to the board on the wiring 142 and the output terminal of the first layer on the substrate wiring board wiring to be connected to the substrate on the wiring 135 and the ground power supply is connected to the positive power supply 140 may be configured plurality of wiring layers force such that the substrate on the wiring of the second layer.

[0037] Te me, in Figure 4B, the fm-type FET, the power, and, the terminals, to connect the buried wiring and the wiring on the PCB is the same as FIG. 3C. However, when performed through the board wiring 141 for connecting the drain and Tankomi wire 146 of the N-channel fm type FET138 to the output terminal, in proximity and the drain of Tankomi wiring 146 and N-channel fm type FET138 because we are using a shared contact 149, except that is aimed to connect to the board wiring 141 connected to the output terminal. Further, when performed through the board wiring 142 for connecting the source and the buried wiring 147 of P-channel fm type FET137 the input terminal, and the drain of the Tankomi wiring 147 and the P-channel fin type FET137 is close Therefore, by using the shared contact 149, also in that the aim of connecting the substrate wiring 142 connected to the input terminal different. Here, the shared contact, when two or more patterns are connected to the same wiring pattern, the same contact via the position of the wiring pattern and one of the pattern, the same con tact the wiring pattern and other patterns to close the via positions, ligated, it refers to those with one contact via. Chi words, in some shared contact, the same wiring pattern and one of the pattern is connected, furthermore, in the portion of the remaining shared contact, the same wiring and the other patterns are connected form.

[0038] Accordingly, it is possible to reduce the area for acquiring the minimum spacing between the contact Via. For example, in Figure 4B, in the normal, the contacts via the N-channel fm type FET138 sheet We § over de contacts by connecting two contacts via the contact via is necessary force above the drain of the Tankomi wiring 146 it makes is possible reduce the space required between the contacts Via, distance between the drain and the buried wiring 146 of N-channel fm type FET can also be narrowed. Therefore, compared to the circuit layout of FIG. 3C, furthermore, Ru can reduce the circuit layout area.

[0039] Figure 4C is a circuit showing an SRAM memory device. In SRAM storage element of FIG. 4C,

152, 153 signal line, 154, 155 inverter, 156, 157 transfer gate transistor, 158 is an input terminal, 159 indicates an output terminal, respectively.

[0040] Then, SRAM storage element of FIG. 4C, the circuit of a portion of an SRAM memory device of FIG. 4A, the transfer gate transistors 156, 157 is in the additional configuration. The operation of the circuit shown in FIG. 4C, the SRAM memory elements, and, in function, taking the circuit the same as the structure of a part of the SRAM storage element of FIG. 4A, the portion of the inverter 154, 155, FIG. 4A and the same kind of operation, has a function.

[0041] On the other hand, the transfer gate transistor 156 of the circuit shown the SRAM storage element of FIG. 4C, a logic signal stored in the portion of the inverter one coater 154, 155, from the input terminal 158, whether the signal line receives the 152 logic, has a function of selecting. That is, the gate electrode of the transfer gate transitional scan data 156, the potential of the logic value 'H' is applied, the circuit shown the SRAM storage element of FIG. 4C, the input signal, accept. The gate electrodes of the transfer gate transistor 156, the potential of the logic value 'L' is applied, the circuit shown the SRAM storage element of FIG. 4C, the input signal, receiving a record. On the other hand, the transfer gate transistor 157 of the circuit shown the SRAM storage element of FIG. 4C, a logic signal stored in the portion of the inverter 154, 155, whether power outputs, the logic of the signal 153, selects. That is, the Gate electrodes of the transfer gate transistor 158, the potential of the logic value 'H' is applied, the circuit shown the SRAM storage element of FIG. 4C, an output signal, and outputs. The gate electrode of the transfer gate transistor 157, the potential of the logic value 'L' is applied, the circuit shown the SRAM storage element of FIG. 4C, an output signal, no output.

[0042] Figure 4D is a circuit layout including a fin-type FET constituting the SRAM memory element of FIG. 4C, a Tankomi wiring and substrate wiring to connect the fm-type FET, shared con tact part it is a diagram showing a circuit layout, wherein the using.

In Figure 4D, 160 is a substrate on the wiring that connects to the positive power supply, 161, 162 P-channel fin type FET, 163, 164, 165, 166 are N-channel fm type FET, 167 on the substrate to be connected to the ground power supply line, 168 on the substrate to be connected to the output terminal wiring, 169 denotes a substrate on distribution lines connected to an input terminal, 170, 171 on the substrate wiring, 172, 173 embedded wiring, 174 denotes a contact Via, 175 market share over de contact, 176 the wire-bonding region, 177, 178 show, respectively Re its substrate on the wiring connected to a signal line. The substrate on the wiring 160, 167, 168, 169, 170, 171, one is consists from the wiring layer les, Ru need not, yo les, even constituted by a plurality of wiring layers les.

[0043] The drains of the P-channel fin type FET161 is connected to the board wiring 160 to be connected to a positive supply via a contact Vial74. The source of the P-channel fm type FET161 is the shared contact 175, the board wiring 170 is connected to the drain of N-channel fm type FET 164. The source of the P-channel fin type FET161 is the board wiring 170 through a contact v Ial74, connected to the drain of N-channel fm type FET 165. Furthermore, the source of P-channel fm type FET161 is a board wiring 170 and Tankomi wiring 173, Chez § over de contacts 175, contacts Vial74, and, via a wire-bonding region 176, the gate electrode and N-channel P-channel fin type FET162 It is connected to the gate electrode of the fin-type FET166.

The gate electrode of the P-channel fin type FET161 is a buried interconnection 172 is connected to the gate electrode of the N-channel fm type FET165 and through the wire-bonding region 176. The gate electrode of the P-channel fm type FET161 is by Tankomi wiring 172 and the board wiring 171, the wiring connection area 176, is connected to the source of P-channel fin type FET162 through contact v ial74. Furthermore, the gate electrode of the P-channel fin type FET161 is the embedded wiring 172 and the board wiring 171, Rooster himself wire connection region 176, the contact Vial74, and drain and N of the N-channel fin type FET166 through the shared contact 175 It is connected to the source of the channel fm type FET163.

[0044] The source of N-channel fin type FET164 is connected via a contact vial74 to the input terminal 168. The source of N-channel fin type FET 165, 166 is connected to the board wiring 167 to be connected to the ground power supply through a contact Vial74. Drain of P-channel fin type FET162 is connected to the board wiring 160 connected to the positive supply via a con tact Vial74. Drain of N-channel fin type FET163 is connected to the board wiring 168 connected to the output terminal through the contact Vial74. The gate electrode of the N-channel fm type FET163 is connected to the board wiring 178 connected to the signal line. The gate electrode of the N-channel fm type FET164 Les connected to board wiring 177 connected to the signal line, Ru.

By using a shared contact 175, the normal contact vial74 it is not necessary to take apart the order to arrange two, it is possible to further reduce the distance between the N-channel fm type FET164 and P-channel fin type FET 161. Similarly, by using a shared contact 175 may Rukoto force S to be further reduced spacing between N-channel fin type FET163 and N-channel fm type FET166. Thus, by using a shared contact 175, thereby reducing the circuit layout of the SRAM memory element.

Example 4

[0045] (with a Fin FET, the manufacturing process of logic macrocells or SRAM macro cell)

5, 6, 7, 8, 9, 10 and, with reference to FIG. 11, Example 4, Example 1, 2, and the production of logic macrocells or SRAM macrocells shown in 3 It shows a step.

Figure 5 shows a flow chart of a manufacturing process of logic macrocells or SRAM macrocell.

[0046] In FIG. 5, the fin region formation step 180, the fm region 181, the insulating support substrate 182, 183 is a groove forming step, the groove for buried wiring 184, 185 silicon-germanium (SiGe) Tankomi step, 186 silicon. germanium (SiGe), 187 denotes a gate electrode formation step, 188 polysilicon (P-Si) layer, Tankomi wiring step 189, 190 cavity, the metal (metal) 191, 192 substrate It shows the upper wiring formation step, respectively.

[0047] Then, the flow chart of FIG. 5, the manufacturing process fm region forming step 180 of logic macrocells or SRAM macrocell groove forming step 183, silicon. Germanium (SiGe) embedding step 185, the gate electrode formation step 187, the embedded wiring step 189, and shows that it consists board wiring formation step 192.

[0048] fm region formation step 180, on the insulating support substrate 182 is a step of forming a fin area 181 is a three-dimensional region made of a semiconductor. The above semiconductor is desirable that a silicon (Si) Les. Further, it is desirable that the above insulating support substrate 182 is desirable instrument insulating portions SOI (Silicon on insulator) is is a silicon oxide film. Groove forming step 183 is a step of forming a groove 184 for Tankomi wiring insulating supporting substrate 182. SiGe Tankomi step 185 is a step of embedding a silicon 'germanium (SiGe) 186 in the groove 184 for the embedded wiring in the insulating supporting substrate 182.

[0049] The gate electrode forming step, for example, of a conductive material such as polysilicon (P-SD188, a step of forming a gate electrode of the fm-type FET. To perform an embedded wiring process, a plurality of types Although steps can be considered, shows the first steps in the following. first, an insulating film is deposited on the gate electrode. then, with respect to Tanme written silicon 'germanium grooves, form a contact via form, depositing a metal (metal) 191, to contact. then the heat treatment, by heat treatment, by using the substitution phenomenon of silicon and metal to form a buried interconnection. Note that the silicon the metal used for substitution of the metals, aluminum (A1) is preferable. the second step of the embedded wiring process is as follows. first, silicon. germanium (SiGe) 186 a for Tankomi wire selectively removing from the groove 184. then, a groove 1 for embedded wiring 84 and cavity 190, then carried out by embedding the main barrel (metal) 191. Note that the above-mentioned metal, tungsten contact) is desirable.

[0050] board wiring forming step 192, the case of performing the embedded wiring step 189 in the first step, as it leaves the metal (metal) layer used to replace the silicon and metal, metal (metal) layer the registration list pattern to form a wiring pattern on, to form a wiring by etching. On the other hand, the case of performing Tankomi wiring step 189 in the second step, the substrate on the wiring formation step 192, first, the insulating layer, forming contact via relative buried interconnections or the like, metal after depositing a (metal) 191, a resist pattern to form a wiring pattern, to form a more wiring etching. The substrate on the wiring, such necessarily be formed in only one wiring layer les. In addition, the metal used for the substrate wiring, aluminum (Al), tungsten (W) or the like is desirable.

[0051] FIG. 6, 6A, 6B, 6C, FIG. 6D, FIG. 6E and FIG. 6F force are al structure, is a diagram showing a detailed manufacturing process of the fin-type region forming step . 6 is a diagram showing a cross section along the A- B of Figure 2A. 6, 195 is a silicon oxide film (Si02) layer, a single crystal layer of silicon 196, 197 silicon oxide film (Si02) layer, 198 is polysilicon (P-Si) layer, 199 a resist pattern, 200 an isolated region of the polysilicon, 201 is an interlayer insulating film of a silicon oxide film (Si02), 202 sidewall of the silicon oxide film, 203 denotes a isolated area of ​​silicon oxide layer.

[0052] Figure 6A, on the S_〇_I substrate comprising a silicon oxide layer 195 and silicon single crystal layer 196, a silicon oxide film 197 and polysilicon (P_Si) layer 198, CVD (chemical vapor deposition) method by a diagram showing a was deposited. Incidentally, S_〇_I substrate sheet to form a silicon oxide layer on a silicon substrate, further, it was created by pasting the silicon substrate on the silicon oxide layer. Thus, a single crystal layer of silicon, and has a sandwiched silicon oxide film. Further, in S_〇_I substrate, a single crystalline layer of silicon on the side forming the circuit element, by Migaku Ken or the like, as compared to the silicon single crystal side of the opposite side, thin summer. That is, in FIG. 6A, among the silicon single crystal layer, the single crystal layer 196 and Shinrikon oxide film 195 of silicon on the side forming the circuit elements are shown. The thickness of the silicon oxide film layer 195 in the SOI substrate, there is 70nm or more, about lOOnm is desirable. The thickness of the silicon single crystal layer 196 Shi desirable about 30nm les. Further, the silicon oxide film 197 is 10nm approximately, the thickness of the polysilicon Con (P-Si) layer 198 is preferably about 30 nm.

[0053] Figure 6B, a resist is coated on the polysilicon (P-Si) layer 198, and more photolithography technique is a diagram showing a was a resist pattern 199. The width of the resist pattern 199, since that would determine the distance fm region of fm type FET, it is desirable from 80nm is about 150 nm.

[0054] FIG. 6C, the resist pattern 199 as an etching mask, the polysilicon (P_Si) layer 198 is etched in the anisotropic property is where the polysilicon isolated region 200 is obtained. Similar to the width of the resist pattern over down 199, the width of the isolated region 200 of the polysilicon is 150nm order of 80 nm. The height of the polysilicon isolated areas 200 is preferably 30nm order of 20 nm. Later, it created on the side wall of the isolated region 200 of the polysilicon, in order to 30nm about a width from 20nm sidewall 202 of the silicon oxide film.

[0055] Figure 6D the interlayer insulating film 201 of a silicon oxide film (Si02) on the polysilicon of the isolated region 200 and the silicon oxide film 197 is a diagram showing a was deposited by CVD. The thickness of the interlayer insulating film 201 of a silicon oxide film (Si02), since the width of the side wall 202 of the silicon oxide film 20nm to about 30 nm, it is desirable to lOOnm order of 50nm.

[0056] Figure 6E, by anisotropic etching of the interlayer insulating film 201 of a silicon oxide film (Si02), is a diagram showing the place that created the sidewalls 202 of the silicon oxide film. Width of the sidewall 202 of the silicon oxidation film, later, that the Do because that determines the width of the fin region of the fin-type FET, it is desirable that the 30nm order of 20 nm.

[0057] Figure 6F, the isolated region 200 of the polysilicon is removed by etching isotropic, anisotropic etching sidewalls 202 of silicon oxide film (Si02) layer 197 as an etching mask of the silicon oxidation film, it is a diagram showing a place of forming the isolation region 203 of the silicon oxide layer. Thereafter, the isolated region 203 of the silicon oxide layer as an etching mask, the silicon single crystal layer 196 is anisotropically etched to form a fin region of the fin-type FET.

[0058] FIG. 7, FIG. 7G, Fig. 7H, Figure 71, Figure 7J, Figure 7K and, FIG. 7L force are al structure, is a diagram showing the details of groove forming step for buried wiring . 7 is a diagram showing a cross section between alpha-beta in FIG 2.alpha.

7, 195 denotes a silicon oxide film (Si02) layer, 202 is a silicon oxide film side War Honoré, isolated areas of the silicon oxide layer 203, 204 is three-dimensional isolation region of the silicon, i.e., the fm-type FET fm region, 205 denotes a silicon oxide film layer, 206 denotes a side War Honoré silicon oxide film, 207 is a resist pattern 208 is a groove for buried wiring, 209 denotes a silicon 'germanium (SiGe) layer, respectively.

[0059] Figure 7G, after the completion of the step of FIG. 6F, the sidewalls 202 of the silicon oxide film, and a single crystal layer of silicon isolated region 203 as an etching mask of the silicon oxide layer, and anisotropic E Tsuchingu Te is a diagram showing the place where to obtain a fm region 204. Here, as described FIG. 6D Oite, 30nm about a the possible forces et width from 20nm sidewall 202 of the silicon oxide film, the width of fm region 204 is about 30nm approximately 20nm. Further, since the thickness of the silicon single crystal was about 30 nm, the height of the fm region 204 is about 30 nm.

[0060] FIG. 7H, after the completion of the process of FIG. 7, by isotropic etching sidewalls 202 of the silicon oxide film, a diagram illustrating a was removed.

[0061] FIG. 71, after completing the step of FIG. 7H, a diagram showing the place depositing a silicon oxide film 205. Then, it is desirable that the width of the silicon oxide film 205 is 60nm order of 40 nm. In order to 30nm order of 20nm width of the sidewall 206 of the silicon oxide film to be formed later.

[0062] FIG. 7J, after completing the process of FIG. 71, the silicon oxide film 205 is anisotropically etched, a diagram showing the place where the formation of the side wall 206 of divorced oxide film. Further, after forming the sidewalls 206 of the silicon oxide film, a resist is applied, by a photolithography technique, a diagram showing a was formed a resist pattern 207. Spacing between the resist pattern 207, namely, the opening of the resist pattern 207 is wider than the spacing between fin area 204, the edge of the resist pattern 207 is located above the fm region 204.

[0063] FIG. 7K, after completion of the step of FIG. 7J, anisotropically etched, the trench 208 for the buried wiring is formed on the silicon oxide film layer 195 of the supporting substrate, removing the resist pattern 207 it is a diagram showing a place. Since fin area 204 interval is 150nm order of 80 nm, considering the width of the sidewall 206 of the silicon oxide film is 30nm order of 20 nm, the width of the groove 208 for Tankomi wire about 90nm from 40nm to become. Further, the groove 208 for the buried wiring by considering that writing Tanme metal (metals) for Tankomi wiring groove, or less desirably 50nm.

[0064] FIG. 7L, after step is completed in FIG. 7K, silicon in the groove 208 for Tankomi wire. Germanium

For embedding the (SiGe), a diagram showing the rollers and is deposited by CVD silicon germanium (SiGe) layer 209. The thickness of the silicon 'germanium (SiGe) layer, since the purpose silicon. That germanium (SiGe) writes Me Tan groove 208 for Tankomi wiring, it is desirable that lOOnm order of 75 nm. Note that later, in the groove 208 for the embedded wiring, since it would embed metal (metal), for preventing diffusion of metal (metal), the silicon nitride film after depositing about lnm force 5nm , arbitrary desired to deposit silicon 'germanium (SiGe) layer 209. However, after forme Tanme metal (metal) in the groove, as the diffusion of metal (metal) occurs, when a high heat treatment is not applied may be omitted deposition of silicon nitride film. The silicon nitride film is thinner because of the following, not shown.

Incidentally, silicon as the embedding material 'that used germanium (SiGe) is silicon' Genore Maniumu (SiGe) is, in the case of performing the isotropic etching, the silicon constituting the fin region 204 or the gate electrode (Si) or the polysilicon (P-Si), because with selectivity. Incidentally, selection 択性 is necessary because, fm region 204 or the gate electrode, silicon oxide (Si02) Saiduo Lumpur 206 or a silicon oxide film (Si02) film forces silicon oxide covered by such layer of film (Si02) film Due to the nature of the forming process, such as the sidewall 206, because no reliable necessarily covers all silicon (Si) portion.

[0065] FIG. 8, FIG. 8M, Figure 8N, FIG. 80, FIG. 8P, Figure 8Q and are composed of FIG 8R, is a diagram showing the details of groove forming step for sputum write wiring. Further, FIG. 8 is a diagram showing the cross-sectional surface between the A- B of Figure 2A.

8, 195 is a silicon oxide film (Si02) layer, isolated areas of the silicon oxide layer 203, three-dimensional isolation region of silicon 204, i.e., fm region of fm type FET, 206 is a silicon oxidation film side wall, 209 silicon 'germanium (SiGe) layer, 210 is polysilicon (P-Si) layer, 211 a silicon oxide film, 212 is a resist pattern, 213 denotes a gate electrodes of the fin-type FET.

[0066] FIG. 8M is silicon. Germanium (SiGe) layer 209 of FIG. 7L, at the top of fm region is a diagram showing a was flattened. Here, in performing the flattening of the silicon 'germanium (SiGe) layer 209 is, for example, CMP (chemical mechanical polishing) process, i.e., chemical, and can be achieved by performing a mechanical polishing process .

[0067] FIG. 8N, after the completion of the process of FIG. 8M, a diagram showing the place where the isotropic etching were performed on silicon 'germanium beam (SiGe) layer 209. The isotropic etching can be performed between a certain time, it is possible to remove the silicon 'germanium (SiGe) layer 209 in the portion other than the groove for buried wiring. Incidentally, in the step of FIG. 7L, as the diffusion preventing film, when obtained by sedimentary silicon nitride film, after removal of the silicon 'germanium (SiGe) layer 209, in an isotropic etch ring, for Tankomi wire removing the silicon nitride film other than the groove of.

Figure 80, after the completion of the process of FIG. 8M, the sidewalls 206 of the silicon oxide film, a diagram showing a were removed isolated region 203 of the silicon phosphorylation layer. Isotropic etching, by performing the silicon oxide film, it is possible to remove the silicon oxide film.

Figure 8P after step is completed in Fig 8_Rei a sedimentary the figure polysilicon (P-Si) layer 210 and the silicon oxide film 211. The deposition of polysilicon (P-Si) layer 210 and the silicon oxide film 211, for example, can be used CVD method. Note that the polysilicon (P-Si) layer 210 and silicon in the groove for buried wiring 'germanium (SiGe) not through the contact Via, are in direct contact. The thickness of the port Rishirikon (P-Si) layer 210 Shi desirable 50nm order of 30nm les. Further, the silicon oxide film 211 is to act as a etch stop, is preferably about 10 nm.

[0068] FIG. 8Q is, after completing the step of Fig. 8P, a resist is applied, Ri by the photolithography technique, a diagram showing a was formed a resist pattern 212.

Figure 8R is by anisotropic etching using the resist pattern 212 as an etching mask, the silicon oxide film 211 and polysilicon (P_Si) layer 210 is etched, exhibited was formed a gate electrode 213 of the fm-type FET Figure it is.

[0069] FIG. 9, FIG. 9R, FIG 9S, FIG 9T, FIG 9U, Figure 9V and are composed of FIG 9W, shows a detail of the buried wiring process and forming on the substrate a wiring step (Part 1) It was a diagram. 9 is a diagram showing a cross section along the A- B of Figure 2A. The substrate on the wiring formation step (1), in the description of the flowchart of FIG. 5 is a detailed description of the process described as the first step.

9, 195 denotes a silicon oxide film (Si02) layer, three-dimensional isolation region of silicon 204, i.e., fin region of the fin-type FET, 209 is silicon 'germanium (SiGe) layer, 213 a gate of the fin-type FET electrode, 214 is an interlayer insulating film of a silicon oxide film, 215 is a contact Via, 216 denotes an aluminum Niu (AL) layer, 217 denotes a silicon-germanium substitutions aluminum after replacing the (SiGe) layer (AL), respectively.

[0070] FIG 9R is a similar view to FIG. 8R.

Figure 9S, after the completion of the process of FIG. 9R, is a diagram showing the place where the interlayer insulating film 214 of a silicon oxide film was more deposited CVD method. The thickness of the interlayer insulating film 214 of a silicon oxide film is about 200nm from lOOnm is desirable. When performing planarization of the interlayer insulating film 214 of a silicon oxide film, such as a gate electrode 213 of the fin-type FET, because we need a sufficient thickness.

[0071] FIG. 9T, after the completion of the process of FIG. 9S, by CMP, polishing is performed, is a diagram showing a was flat I匕 interlayer insulating film 214 of a silicon oxide film. Here, the thickness of the layer insulating film 214 of a silicon oxide film, Shi desirable from the surface of the silicon oxide film (Si02) layer 195, LOOnm extent from 80nm Les. Height force 20nm from 30nm about fm type FET of fm region 204, the thickness of the Gate electrode of fin-type FET is, considering that the 30nm order of 20nm, it is necessary to include the entire fin type FET it is. Note that when the substrate on the wiring layer were multilayer wiring, the thickness of their wiring layers of the interlayer insulating film is considered to be a 50 醒程 degree from 30 nm, the silicon oxide film of the interlayer insulating film 214 thickness, thickness than the thickness of the interlayer insulating film on the substrate on the wiring interlayer les.

[0072] FIG. 9U, after the completion of the process of FIG. 9T, a diagram showing the place where the formation of the contact via215 the interlayer insulating film 214 of a silicon oxide film. Contact via215 are formed by the following procedure. First, a resist is applied on the upper surface of the interlayer insulating film 214 of a silicon oxide film. Next, by photolithography technique to form an opening pattern for the contact Via215. Next, a resist pattern as a mask, by anisotropic etching, the silicon oxide film is etched, the silicon. Forming a through hole to germanium (SiGe) layer 209, a contact Via215. Incidentally, in FIG. 9T, it was expressed contact via215 in dotted lines, in fact, contactor DOO via215 is the A- B cross section of FIG. 2A, because not come appear. A contact via215 in Figure 2A, illustrates a contact vai24 connecting the embedded wiring 21 and the input terminal 18. Therefore, the contact via215 is was expressed because Do and hiding behind the gate electrode of the fm-type FET, a contact via215 a dotted line.

[0073] FIG 9V, after the completion of the process of FIG. 9U, aluminum (AL) layer 216, a CVD method, or a diagram showing a was deposited by spatter method. The thickness of aluminum (AL) layer 216 is about 500nm from lOOnm is desirable. It is to secure the wiring resistance on the substrate wiring. Contact name Thereafter, a step of replacing the aluminum (AL) layer 216 of aluminum (AL) and silicon is embedded in the groove for Tankomi wiring 'germanium (SiGe) 209 is an aluminum (AL) layer at the connection point of 216 and a silicon-germanium (SiGe) 209, it is necessary to remove the insulating layer. Because the be sandwiched insulating layer because not occur substituted phenomenon. Wherein, for depositing aluminum (AL) layer 216, pre-processing, for example, it is common to etch a jog isotropic take insulating layer.

[0074] FIG 9W, after the completion of the process of FIG. 9W, row-substitution of aluminum aluminum in (AL) layer 216 (AL) and silicon in the groove for Tankomi wiring 'germanium (SiGe), , embedded aluminum (AL) in the groove for Tankomi wiring diagrams showing a place of forming the embedded wiring. Al Miniumu (AL) layer aluminum in 216 (AL) and silicon in the groove for Tankomi wire. To cause the substitution phenomenon and germanium arm (SiGe), it can be achieved by heat treatment. Here, the heat treatment Shi wishing to be about 60 minutes at 450 ° C les.

[0075] Next, with reference to FIGS. 10 and 11 show the details of the embedded wiring step and board wiring formation step (2). The substrate on the wiring formation step (2), in the description of the flowchart of FIG. 5 is a detailed description of the process described as the second procedure.

Figure 10 is a diagram 10R, FIG 10SS, FIG 10TT, FIG 10UU, FIG 10VV, and a diagram is composed of 10 stomach. Further, FIG. 10 is a diagram showing a cross section along the A- B of Figure 2A.

10, 195 denotes a silicon oxide film (Si02) layer, three-dimensional isolation region of silicon 204, i.e., fm region of fm type FET, 209 is silicon 'germanium (SiGe) layer, 213 a gate of the fin-type FET electrode, 218 is hollow state, 219 tungsten (W) layer, 220 is a resist pattern, 221 denotes a silicon oxide film layer, respectively.

[0076] FIG. 10R is a similar view to FIG. 8R and FIG 9R, branched Tankomi wiring step and board wiring formation step (1) buried wiring step and board wiring formation step (Part 2) but indicates that from after completing the step of FIG. 10R.

FIG 10SS, by performing the isotropic etching is a diagram showing a was removed silicon. Germanium (SiGe) layer 209 Le, Ru is written Tanme the groove for Tankomi wire.

FIG 10TT is tungsten (W) layer of CVD method, after depositing, a resist is applied, the mined lithography, a diagram shows formation of the resist pattern 220 covering the Tankomi wiring region. The thickness of the tungsten (W) layer 219 is Shi desirable 500nm order of LOOnm,. Sufficiently, because the writing sputum Me tungsten (W) in the groove for buried wiring.

[0077] FIG 10UU is a resist pattern 220 as an etching mask is a diagram showing the place where the anisotropic etching the tungsten (W) layer was removed row-,, resist pattern 220. Their to step is necessary because of FIG 10UU is less. First, when the tungsten (W) layer are present in a wide range, by performing the isotropic etching, so as to leave tungsten (W) in the groove for Tankomi wire, it is easy to control the isotropic etching Les, of the. Therefore, the process of FIG 10UU row of Le ,, tungsten (W) is a result to remain only in the peripheral groove for Tankomi wires, because the control of subsequent isotropic etching becomes easy.

[0078] FIG 10VV, after completion of the step of FIG 10UU, by performing the isotropic etching, when leaving a tungsten Tan Dasuten (W) layer 219 (W) only in the trench for Tankomi wire it is a diagram showing a. As a result, Tankomi wirings are formed.

FIG 10WW, after completion of Figure 10W step is a diagram showing the place where the silicon oxide film layer 221 is deposited by CVD. Silicon thickness of the oxide film layer 221, Shi then, 200 nm is desirable from lOOnm Considering row Ukoto planarization les. fm region 204 of the fm-type FET, and it is necessary to include a gate electrode of the fm-type FET. Incidentally, after this step, when the heat treatment such as the diffusion of data tungsten (W) is expected to participate, before depositing the silicon oxide film layer 221, it is desirable to deposit the silicon nitride film as a diffusion preventing film. The thickness of the silicon nitride film for the diffusion preventing film is desirably 10 匪程 degree from 5 negation. However, since the silicon nitride film for the diffusion preventing film is a thin film, not shown in FIG 10WW

[0079] FIG. 11 is a diagram 11XX, FIG 11YY, and a diagram and a diagram 11ZZ. 11 is a diagram showing a cross section between alpha-beta in FIG 2.alpha.

11, 195 denotes a silicon oxide film (Si02) layer, three-dimensional isolation region of silicon 204, i.e., fm region of fm type FET, 209 is silicon 'germanium (SiGe) layer, 213 a gate of the fin-type FET electrode, 219 tungsten (W) layer, 221 is a silicon oxide film layer, 222 contactors DOO Via, 223 denotes a tungsten (W) layer, respectively.

FIG 11XX is, after completion of the step of FIG 10WW, by a silicon oxide film layer 221 CMP method, a chemical is a diagram showing a was flat I匕 by performing mechanical polishing. Here, the thickness of the interlayer insulating film 221 of a silicon oxidation film, from the surface of the silicon oxide film (Si02) layer 195, about lOOnm desirably from 80 nm. Height force 20nm from 30nm about fm type FET of fm region 204, the thickness force S of the gate electrode of the fin-type FET, when considering that the 30nm order of 20nm, it is necessary to include a fin-type FET entire it is. Note that when the substrate on the wiring layer were multilayer wiring, and to take into account the thickness of their wiring layers of the interlayer insulating film is 50nm order of 30 nm, the thickness of the interlayer insulating film 214 of a silicon oxide film is is greater than the thickness of the interlayer insulating film on the substrate on the wiring layers.

[0080] FIG 11YY, after the completion of the process of FIG 11XX, a diagram showing the place where the formation of the con tact via222 the interlayer insulating film 221 of a silicon oxide film. Contact via222 are formed by the following procedure. First, a resist is applied on the upper surface of the interlayer insulating film 221 of a silicon oxide film. Next, by photolithography technique to form an opening pattern for the contact Via222. Next, a resist pattern as a mask, by anisotropic etching, the silicon oxide film is etched ring, a through hole is formed to tungsten (W) layer 209, a contact Via222. Note that in FIG 11YY, was expressed contact via222 in dotted lines, in fact, contact via222 is the A- B cross section of FIG. 2A, because not come appear. A contact via222 in Figure 2A, illustrates a contact vai24 connecting the embedded wiring 21 and the input terminal 18. Therefore, the contact via222 is was expressed because Do and hiding behind the gate electrode of the fm-type FET, a contact via222 a dotted line.

[0081] FIG 11ZZ, after the completion of the process of FIG 11YY, tungsten (W) layer 223, a CVD method, or a diagram showing a was deposited by sputtering. The thickness of the tungsten (W) layer 223 is about 500nm from lOOnm is desirable. It is to secure the wiring resistance on the substrate wiring. Industrial Applicability

[0082] The present invention provides a suitable semiconductor integrated circuit device and a manufacturing method thereof as a component of the Fin-FET formed on a supporting substrate in a highly integrated LSI.

DESCRIPTION OF SYMBOLS

[0083] 1 processor

2 chip

3 logic circuit

4 fm type FET

5, 15, 25, 40, 57a, 70 substrate wiring connected to the positive power supply

6, 16, 26, 33, 41, 48, 57b, 63, 71, 78 P-channel fin type FET

7, 17, 27, 34, 42, 49, 57c, 64, 72, 79 N-channel fin type FET

8, 18 board wiring connected to the input terminal

9, 19, 29, 44, 59, 74 on the substrate connected to the output terminal wiring

10, 20, 30, 45, 60, 75 on the substrate connected to the ground power source wiring

11, 21, 31, 35, 46, 50, 61, 65, 76, 80 Tankomi wiring

13, 23, 39, 54, 69, 83 contact Via, 55, 82 wire-bonding region

, 43, 58, 73 on the substrate to be connected to the input terminal 1 line, 56, 66, 81 on the substrate to be connected to the input terminal 2 lines, 53, 67, 77 on the substrate wiring

, 86 inverter

Input terminal

Output terminal

, 105, 120 board wiring to be connected to a positive power supply, 93, 106, 107, 121, 122 P-channel fin type FET, 94, 108, 109, 123, 124 N-channel fin type FET, 96, 115, 116, 117 , 118, 130, 131 buried interconnections, 110, 125 on the substrate to be connected to the ground power supply line, 112, 127 on the substrate to be connected to the input terminal wiring, 111, 126 on the substrate to be connected to the output terminal wiring 0, 113, 128 Contacts Via

4, 129 wiring connection area

0, 131 inverter

2 input terminal

Third output terminal

5, 160 board wiring to be connected to the positive power supply

6, 137, 161, 162 P-channel fm type FET

8, 139, 163, 164, 165, 166 N-channel fm type FET 0, 167 on the substrate connected to the ground power source wiring

1, 168 board wiring connected to the output terminal

2, 169 board wiring connected to the input terminal

3, 174 Contacts Via

4, 176 wiring connection area

5, 146, 147, 148, 172, 173 Tankomi wiring 149, 175 shared contact

152, 153 signal lines

154, 155 Inno rather Ta

156, 157 transfer gate transistor

158 input terminal

159 output terminal

170, 171 on a substrate wiring

177, 178 board wiring connected to a signal line

180 fin region formation step

181 fin area

182 insulating support substrate

183 groove forming step

184 groove for Tankomi wiring

185 silicon 'germanium (SiGe) Tankomi process

186 silicon 'germanium (SiGe)

187 a gate electrode formation step

188 polysilicon (P-Si)

189 Tankomi wiring process

190 cavity

191 metal (metal)

192 board wiring formation step

195 silicon oxide film (Si02) layer

196 single-crystal layer of silicon

197 silicon oxide film (Si02) layer

198 polysilicon (P-Si) layer

199 resist pattern

200 poly-silicon of the isolated region

201 sidewall of the interlayer insulating film 202 a silicon oxide film of a silicon oxide film (Si_rei_2)

203 isolated area of ​​silicon oxide layer

204 of fin-type FET fm region (solid isolated area of ​​silicon)

205 silicon oxide layer

206 side wall of the silicon oxide film

207 resist pattern

208 groove for Tankomi wiring

209 silicon 'germanium (SiGe) layer

208 groove for Tankomi wiring

209 silicon 'germanium (SiGe) layer

210 polysilicon (P- Si) layer

211 silicon oxide film

212 resist pattern

213 gate electrode of the fin-type FET

214 interlayer insulating film of silicon oxide film

215 Contacts Via

216 Aluminum (AL)

218 cavity state

219 tungsten (W)

220 resist pattern

221 silicon oxide film layer

222 Contacts Via

223 tungsten (W) layer

Claims

The scope of the claims
[1] and the MOS transistor device having a gate electrode formed on the surface of the solid isolated areas of the solid isolated areas of the silicon formed on the supporting substrate and the silicon,
And Tankomi wirings written Tanme the groove in said support substrate,
And a substrate on the wiring on the support substrate,
The semiconductor circuit device, wherein the dividing the row connected between said MOS transistor elements using said Tankomi wiring and the substrate wiring.
[2] The semiconductor circuit device according to claim 1, wherein Tankomi wiring and the solid isolated regions of the silicon is characterized in that it is formed in a self-aligned manner.
[3] The Tankomi wiring semiconductor circuit device according to claim 1, wherein Re, the isosamples connect a gate electrode of the MOS transistor elements.
[4] The Tankomi wiring, a semiconductor circuit device mounting serial to claim 1, characterized in that a material containing aluminum.
[5] The Tankomi wiring, a semiconductor circuit device mounting serial to claim 1, characterized in that a material containing tungsten.
[6] placing the Tankomi wire in a first direction,
The connection points of the circuit elements connected by the substrate wiring, a second direction, the semiconductor circuit device according to claim 1, characterized in that the linearly arranged.
[7] The semiconductor circuit device according to claim 6, wherein the first direction the second direction, characterized in that the perpendicular.
[8] as solid isolated region formed E forming the solid isolated region of the MOS transistor devices and
A groove forming step of forming the solid isolated area and groove self-aligned with the buried wiring in the support substrate,
And more Umakomye the writing sputum Me a Tankomi material that is silicon and the etching selectivity to the Tankomi wiring trench,
A gate electrode forming step of forming a gate electrode of said MOS transistor elements, wherein the Tankomi wiring forming step of forming a Tankomi wire, according to claim 1 and a substrate on the wiring forming step of forming the substrate wiring method of manufacturing a semi-conductor circuit apparatus.
[9] The Tankomi material manufacturing method of the semiconductor circuit device according to claim 8, characterized in that the material strength containing silicon and germanium.
[10] The Tankomi wiring forming step,
Removing the Tankomi material,
The method of manufacturing a semiconductor circuit device according to claim 8, characterized in that it comprises the step of writing the Tankomi sputum Me a metal material in the wiring groove.
[11] The metal material manufacturing method of the semiconductor circuits according to claim 10, wherein the wherein the tungsten (W).
[12] The Tankomi wiring forming step,
Forming an insulating layer on the embedding material of the Tankomi wiring groove,
A step of opening the contact Via to the embedding material in the insulating layer,
Depositing a metallic material on the insulating layer,
Semiconductor according to claim 8, wherein further comprising a step of the said embedding material Tankomi in the wiring trench in contact with the metallic material, thereby replacing the metallic material and the Tankomi material subjected to heat treatment method of manufacturing a circuit device.
[13] The method for producing a semiconductor circuit device according to claim 12 wherein the metallic material which comprises aluminum.
PCT/JP2005/002908 2005-02-23 2005-02-23 Semiconductor circuit device, and method for manufacturing the semiconductor circuit device WO2006090445A1 (en)

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