TWI615944B - Regions of semiconductor chip and methods of manufacturing the same - Google Patents

Abstract

A semiconductor device includes a substrate and a plurality of diffusion regions defined in the substrate, the diffusion regions being separated from each other by an inactive region of the substrate. The semiconductor device includes a plurality of linear gate tracks defined to extend above the substrate in a single common direction, each linear gate track being defined by one or more linear gate segments. Each linear gate track extending over both the diffusion region and the inactive region of the substrate is defined to minimize the separation distance between the ends of adjacent linear gate segments within the linear gate track, while Ensure proper electrical isolation between adjacent linear gate segments.

Description

Semiconductor wafer area and method of manufacturing same

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device, and more particularly to a semiconductor device having a dynamic array structure that improves the resolution of the lithography process.

The push for higher performance and smaller die sizes has forced the semiconductor industry to reduce circuit chip area by about 50% every two years, reducing wafer area to provide economic benefits for moving to newer technologies. Reducing the wafer area by 50% is achieved by reducing the feature size to between 25% and 30%, and the feature size can be reduced by improving the manufacturing equipment and materials. For example, the improved photolithography process has been able to A smaller feature size is achieved, and improved chemical mechanical polishing (CMP) has been able to increase the number of interconnect layers to some extent.

In the development of photolithography, when the minimum feature size is close to the wavelength of the light source used to expose the shape of the feature, unintended interactions occur between adjacent features. The smallest feature size is now approaching 45 nm (nano), while the wavelength of the source used in the photolithography process is still maintained at 193 nm. The difference between the minimum feature size and the wavelength of the source used in the photolithography process is defined as the photolithography gap. When the optical lithography gap increases, the resolution capability of the photolithography process will decrease.

When each shape on the mask interacts with light, an interference pattern is created; interference patterns from adjacent shapes can create constructive or destructive interference. In the case of constructive interference, unnecessary shapes may be inadvertently created; in the case of destructive interference, the desired shape may be inadvertently moved. shape. In either case, a particular shape is printed in a different manner than would be expected, which may cause device failure. Corrective methods such as optical proximity correction (OPC) attempt to predict and modify the mask from adjacent shapes so that the printed shape can be fabricated as desired. As the process geometry shrinks and the optical interaction becomes more complex, the quality of optical interaction prediction is declining.

In view of the above, as technology continues to evolve toward smaller semiconductor device feature sizes, we need a solution to address the lithography gap issue.

In one embodiment, a semiconductor device is disclosed. The device includes a substrate and a plurality of diffusion regions defined in the substrate. The diffusion regions are separated from each other by an inactive region of the substrate. The device also includes a plurality of linear gate tracks defined to extend across the substrate in a single common direction, each linear gate track being defined by one or more linear gate segments. Defining each linear gate track extending over the diffusion region and the inactive region of the substrate to minimize separation distance between ends of adjacent linear gate segments within the linear gate track while ensuring There is appropriate electrical insulation between adjacent linear gate segments; in addition, the linear gate segments are defined to have variable lengths to impart a logic gate function.

In another embodiment, a semiconductor device is disclosed that includes a substrate. Some diffusion regions are defined within the substrate to define the active regions used by the transistor device. The semiconductor device also includes a plurality of linear gate segments positioned above the substrate in a common direction, a plurality of linear gate segments disposed over the diffusion region, and each of the linear gate segments disposed above the diffusion region is defined by A necessary active portion above the diffusion region and a uniform extension portion defined to extend over the substrate except for the diffusion region; further, the linear gate segment is defined to have a variable length to impart a logic gate function. The semiconductor device further includes a plurality of linear conductor segments disposed within a height above the linear gate segment so as to be in a substantially vertical direction and a common direction of the linear gate segments Cross. The linear conductor segments are defined to minimize the end-to-end spacing between adjacent linear conductor segments within a common line above the substrate.

In another embodiment, a gate contact is disclosed, the gate contact comprising a linear conductive segment defined by a length and a substantially uniform cross-sectional shape along one of its lengths. Positioning the linear conductive segment such that its length extends in a direction substantially perpendicular to a gate on which the linear conductive segment is disposed, and the length of the linear conductive segment is defined to be greater than a width of the lower gate The linear conductive segment is overlapped with the lower gate.

In another embodiment, a contact layout is disclosed that includes contacts that are defined on a common gate that is mapped across the substrate. The contact layout also includes a number of sub-resolution contacts that are defined on the common gate to surround each contact. Each resolution contact is defined to avoid rendering in the lithography process while enhancing the resolution of the contacts.

Other aspects and advantages of the invention will be apparent from the description and appended claims.

101A~103C‧‧‧Linear Layout Features

103A~103C‧‧‧sinc function

201‧‧‧Substrate

203‧‧‧Diffusion zone

205‧‧‧Diffuse joints

207‧‧‧ gate feature

209‧‧ ‧ gate contact

211‧‧‧Metal 1

213‧‧‧through hole 1

215‧‧‧Metal 2

217‧‧‧through hole 2

219‧‧‧Metal 3

221‧‧‧through hole 3

223‧‧‧Metal 4

225‧‧‧Additional interconnect layer

301‧‧‧Linear features

303‧‧‧Width of linear features

305‧‧‧The length of the linear feature

307‧‧‧ Height of linear features

309‧‧‧ Height of linear features

311‧‧‧The length of the linear feature

313‧‧‧Linear features under the width

315‧‧‧ Wide line features above

317‧‧‧Linear features

401‧‧‧Diffusion zone

403‧‧‧Diffusion zone

405‧‧‧Diffusion Box

410‧‧‧p+ mask area

412‧‧‧n+ mask area

414‧‧‧p+ mask area

416‧‧‧n+ mask area

501‧‧‧gate feature

501A‧‧‧ gate features with greater width

503‧‧‧Diffuse joints

601‧‧ ‧ gate contact

701‧‧‧The extension of the gate contact outside the gate feature

703‧‧‧ vertical dimension

705‧‧‧ distance

707‧‧‧Enlarge the rectangular gate area

709‧‧‧gate contacts

711‧‧ ‧ gate line

801~821‧‧‧Metal 1 track

Grounding track of 801A‧‧‧Metal 1

821A‧‧‧Electrical track of metal 1

901‧‧‧through hole

1001‧‧‧Metal 2 track

1101‧‧‧ Conductor track

1201‧‧‧ conductor track

1301‧‧1 resolution contacts

1303‧‧‧Grid location

1305‧‧‧"X-shaped" secondary resolution contacts

1400‧‧‧Semiconductor wafer structure

1401‧‧‧Diffusion zone

1403A-1403G‧‧‧Wire

1405‧‧‧Substrate

1407‧‧‧Common direction

1409‧‧‧The width of the wire

1411‧‧‧Distance between wires

1413‧‧‧The length of the wire

1415‧‧‧ necessary active part of the conductor

1417‧‧‧A uniformity extension of the wire

1 shows several layout features and light intensity for generating each layout feature in accordance with an embodiment of the present invention; FIG. 2 shows a generalized stack for defining a dynamic array structure in accordance with an embodiment of the present invention; 3A shows an exemplary basic grid to be mapped to a dynamic array to aid in defining a restricted topology, in accordance with an embodiment of the present invention; FIG. 3B shows a separate region to be mapped to the entire die in accordance with an exemplary embodiment of the present invention. Independent basic grid; 3C illustrates an exemplary linear feature defined to be compatible with a dynamic array, in accordance with an embodiment of the present invention; FIG. 3D illustrates another exemplary linear feature defined as dynamic and dynamic in accordance with an embodiment of the present invention. Array compatible; FIG. 4 shows a diffusion layer layout of a dynamic array according to an embodiment of the invention; FIG. 5 shows a gate layer and a diffusion contact layer, which are located above the diffusion layer of FIG. 4, in accordance with an embodiment of the present invention; And adjacent to the diffusion layer; FIG. 6 shows a gate contact layer according to an embodiment of the present invention, which is defined above and adjacent to the gate layer of FIG. 5; FIG. 7A is shown for use with the gate A conventional method of contacting; FIG. 7B shows a gate contact as defined in accordance with an embodiment of the present invention; and FIG. 8A shows a metal layer 1 according to an embodiment of the present invention, which is defined by the gate contact of FIG. Above and adjacent to the layer; FIG. 8B shows the metal 1 layer of FIG. 8A; FIG. 9 shows a via 1 layer according to an embodiment of the present invention, which is defined above and adjacent to the metal 1 layer of FIG. 8A. Figure 10 shows a metal 2 layer, which is defined in accordance with an embodiment of the present invention. 9 is above and adjacent to the via 1 layer; FIG. 11 shows a conductor track along a first pair with respect to the first and second reference directions (x) and (y), in accordance with an embodiment of the present invention. The angular direction traverses the dynamic array; FIG. 12 shows a conductor track traversing the dynamic array along a second diagonal direction relative to the first and second reference directions (x) and (y), in accordance with an embodiment of the present invention; FIG. 13A illustrates an embodiment of a sub-resolution contact layout for enhancing a diffusion contact and a gate contact through a lithography method according to an embodiment of the invention; FIG. Figure 13B shows the sub-resolution joint layout of Figure 13A, which defines a sub-resolution joint to fill the grid to a possible extent, in accordance with an embodiment of the present invention; Figure 13C shows a second embodiment in accordance with an embodiment of the present invention. An embodiment of a resolution joint layout that utilizes sub-resolution contacts of various shapes; Figure 13D shows an exemplary completion of a converted phase shift mask (APSM) with sub-resolution contacts in accordance with an embodiment of the present invention. Figure 14 shows a semiconductor wafer structure in accordance with an embodiment of the present invention.

In the following description, numerous specific details are set forth to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without all or part of these specific details. In other instances, well-known process operations have not been described in detail in order to avoid unnecessarily obscuring the present invention.

In general, we have set up a dynamic array structure to account for semiconductor process variability associated with the ever-increasing lithography gap. In the field of semiconductor fabrication, the lithographic gap is defined as the difference between the minimum dimension of the feature to be defined and the wavelength of light used to create features in the lithography process, wherein the feature size is smaller than the wavelength of the light. At present, the lithography process utilizes a wavelength of 193 nm light; however, the current feature size is as small as 65 nm, and it is expected that the size as small as 45 nm will soon be approached. Although it is 65nm in size, the shape is still less than 3 times the wavelength of the light used to define the shape; in addition, considering that the radius of light interaction is about 5 wavelengths, we should understand that the shape exposed by the 193nm light source will affect the shape. The exposure is about 5*193nm (1965nm). When considering the feature size of 65nm, the feature size of 90nm should be clear: about twice as many as 65nm compared to the feature of 90nm size. The feature may be located within 1965 nm of the interaction radius of the 193 nm source.

As the number of features within the radius of interaction of the light source increases, the degree and complexity of light interference that affects the exposure of a particular feature is important; in addition, associated with features within the radius of interaction of the light source Special shapes have a major impact on the type of light interaction that occurs. Conventionally, as long as a set of design rules is met, the designer is allowed to essentially define a two-dimensional topology of any feature shape. For example, in a particular film layer of a wafer (i.e., in a particular mask), the designer may have defined two-dimensional varying features having bends that surround each other. When the positions of such two-dimensional varying features are in close proximity to one another, the light used to expose the features will interact in a complex and often unpredictable manner, as the feature size and relative spacing become smaller, optical interaction The more complicated and unpredictable.

Conventionally, if the designer follows the established set of design rules, a product that will produce a result of a particular probability associated with the design rule group can be created; otherwise, the result of the successful design of the design rule group is violated. The probability of the product is unknown. In focusing on successful product manufacturing, in order to illustrate the complex optical interaction between adjacent two-dimensional varying features, the design rule set is greatly expanded to properly account for possible combinations of two-dimensional varying features. This expanded set of design rules quickly becomes so complex and difficult to use that the application of this expanded set of design rules becomes too time consuming, expensive, and error prone. For example, the expanded design rule set requires complex verification; in addition, the expanded design rule set may not be applicable everywhere; in addition, manufacturing yields cannot be guaranteed even if all design rules are met.

It should be understood that accurately predicting all possible optical interactions when generating two-dimensional features of arbitrary shape is usually not possible; in addition, the design rule set can be adjusted to include the enlarged edges to illustrate the proximity of the two-dimensional variation features. The unpredictable light interaction between and acts as. Because the design rules are designed to attempt to cover the stochastic two-dimensional feature topology, the design rules can contain a large number of margins; although the marginal inclusion of the design rule group assists in the layout portion containing the adjacent two-dimensional variation features, The margin of joining such a global domain is such that the layout part that does not contain adjacent two-dimensional variation features is distributed. In the case of overdesign, this leads to poor optimization of wafer area utilization and power efficiency.

In view of the above, it should be understood that the semiconductor yield is reduced by parameter errors resulting from the variability of the design-dependent unconstrained feature topography (i.e., any two-dimensional variation features placed next to each other). For example, these parameter errors may result from inability to accurately print contacts and vias and variability in manufacturing processes; variability in manufacturing processes may include CMP dishing, photolithography, gate distortion, Oxide thickness variability, implant variability, and other manufacturing-related phenomena result in distortion of the layout feature. The dynamic array structure of the present invention is defined to account for the variability of the semiconductor fabrication process described above.

1 shows a number of layout features and a light intensity for generating each layout feature, in particular, the three adjacent linear layout features (101A-101C) are shown in a substantially parallel relationship, in accordance with an embodiment of the present invention. It is placed in a specific mask layer. The distribution of light intensities from the shape of a layout feature is represented by a sinc function, and the sinc function (103A-103C) represents the distribution of light intensities from each of the layout features (101A-101C, respectively), adjacent to the line shape. The layout features (101A-101C) are spaced apart at positions corresponding to the peaks of the sinc function (103A-103C) such that constructiveness between the light energies associated with adjacent linear layout features (101A-101C) Interference, i.e., at the peak of the sinc function (103A-103C), can enhance the exposure of adjacent shapes (101A-101C) of the illustrated layout feature spacing. Consistent with the foregoing, the optical interaction shown in Figure 1 represents a synchronized situation.

As shown in FIG. 1, when a person defines a linear layout feature with a regular repeating pattern and an appropriate spacing, constructive interference of light energy associated with various different layout features enhances exposure of each layout feature. The exposure of the enhanced layout features provided by the constructive optical interference can substantially reduce or even eliminate the need to use optical proximity correction (OPC) and/or priming mask enhancement techniques for adequately producing layout features.

When the adjacent layout features (101A-101C) are spaced apart such that the peaks of the sinc function associated with one layout feature are aligned with the valleys of the sinc function associated with another layout feature, a forbidden spacing is created (ie, Layout feature spacing is prohibited, which results in destructive interference of light energy. Destructive interference of light energy reduces the amount of light energy concentrated at a particular location. Therefore, in order to achieve favorable constructive light interference associated with adjacent layout features, it is necessary to predict where constructive overlap of the sinc function peaks will occur. Layout feature spacing. If the shape of the layout feature is rectangular, nearly the same size, and facing the same direction, as shown by the layout features (101A-101C) of FIG. 1, the predictive constructive overlap of the sinc function peaks and the corresponding ones can be achieved. The layout feature is enhanced in shape. In this way, the resonant light energy from the shape of the adjacent layout features can be utilized to enhance the exposure of the particular layout feature shape.

2 shows a generalized stack for defining a dynamic array structure in accordance with an embodiment of the present invention. It should be understood that we do not intend to fully represent the CMOS fabrication process with a generalized stack as defined in Figure 2 for defining a dynamic array structure; however, we will build a dynamic array based on standard CMOS fabrication procedures. In general, dynamic array structures include both the definition of the underlying structure of the dynamic array and the assembly techniques of the dynamic array to optimize the use of the region. Therefore, we design dynamic arrays to optimize semiconductor manufacturing capabilities.

Regarding the definition of the layer structure under the dynamic array, the dynamic array is disposed on the base substrate 201 in a layered manner, for example, on a germanium substrate or an insulating layer overlying (SOI) substrate. The diffusion region 203 is defined on the base substrate 201, and the diffusion region 203 represents a selected region of the base substrate 201, and impurities are introduced into the interior of the selected region for the purpose of adjusting the electrical properties of the base substrate 201. A diffusion contact 205 is defined over the diffusion region 203 to connect the diffusion region 203 with the conductor lines, for example, a diffusion junction 205 is defined to connect the source and drain diffusion regions 203 with its individual conductor mesh; again, the gate features 207 are Defined above the diffusion region 203 to form a transistor gate. Gate contact 209 is defined to connect gate feature 207 with conductor lines, such as gate contact 209 to connect the transistor gate to its individual conductor mesh.

The interconnect layer is defined above the diffusion contact 205 layer and the gate contact layer 209. The interconnect layer includes a first metal (metal 1) layer 211, a first via (via 1) layer 213, a second metal (metal 2) layer 215, a second via (via 2) layer 217, a three metal (metal 3) layer 219, a third via (via 3) layer 221, and a fourth metal (metal 4) layer 223, the metal and via layers can electrically connect various diffusion contacts 205 and gate connections Point 209 enables the logic function of the circuit to be implemented. It should be understood that the dynamic array structure is not limited to a specific number of interconnect layers (ie, metal and via layers). In one embodiment, in addition to the fourth metal (metal 4) layer 223, the dynamic array may include additional inter-layers. Wiring layer 225; or, in another embodiment, the dynamic array can include less than four metal layers.

The dynamic array is defined such that the film layer (other than the diffusion zone layer 203) is limited in shape with respect to layout features that may be defined therein. Specifically, in each layer other than the diffusion region layer 203, only the linear layout feature portion is allowed. The linear layout features in a particular film layer are characterized by having a uniform vertical cross-sectional shape and extending across the substrate in a single direction, and thus the linear layout features define a one-dimensionally varying structure. The diffusion zone 203 does not need to be a one-dimensional change, but it is allowed to be a one-dimensional change if necessary. In particular, the diffusion region 203 within the substrate can be defined to have any two-dimensional varying shape with respect to a plane that coincides with the top surface of the substrate. In one embodiment, the number of diffusion bend topologies is limited such that the interaction between the bend in the diffusion region and the conductive material forming the gate of the transistor (e.g., polysilicon) can be predicted and accurately modeled. The linear layout features in a particular film layer are disposed parallel to each other such that the linear layout features in a particular film layer extend above the substrate in a common direction and are parallel to the substrate. The particular structure and associated requirements of the linear layout features in the various layers 207-223 will be discussed further with reference to Figures 3-15C.

The dynamic array sublayer layout method utilizes constructive interference of light waves in a lithography process to enhance exposure of adjacent shapes in a particular film layer. Therefore, the spacing of the parallel, linear layout features in a particular film layer is designed to avoid constructive light interference of the optical standing wave, minimizing or eliminating lithography correction (eg, OPC/RET). Thus, compared to the conventional OPC/RET based lithography process, here The defined dynamic array utilizes optical interaction between adjacent features rather than attempting to compensate for optical interaction between adjacent features.

Since the optical standing wave of a particular linear layout feature can be accurately modeled, it can be predicted how the optical standing waves associated with adjacent linear layout features disposed in parallel in a particular film layer will interact with each other. It is predicted how the standing light of the light used to expose the linear features will contribute to the exposure of its adjacent linear features. Predicting the optical interaction between adjacent linear features can identify the spacing between the best features that will be used to create a particular shape of light that will enhance its adjacent shape, and the spacing between features in a particular film layer Defined as the feature spacing, where the spacing is the center-to-center separation distance between adjacent linear features in a particular film layer.

In order to provide the desired exposure enhancement between adjacent features, the linear layout features in a particular film layer are separated from each other to optimize constructive and destructive interference of light from adjacent features. To produce the best representation of all nearby features. The feature-to-feature spacing in a particular film layer is proportional to the wavelength used to expose the feature, and the light used to expose each feature within about five optical wavelength distances from a particular feature will be Enhance the exposure of this particular feature to some extent. Constructive interference to expose the standing waves of adjacent features can maximize the performance of the fabrication equipment and is not limited by the effects of light interaction during the lithography process.

As noted above, dynamic arrays include a restricted topology in which features within each film layer must be aligned in a parallel manner to traverse the linear features of the substrate in a common direction. The optical interaction in the photolithography process can be optimized using the restricted topology of the dynamic array so that the image printed on the mask is essentially the same as the shape drawn in the layout, ie the essence The above achieves a 100% accurate transfer of the layout onto the photoresist.

3A shows an exemplary base mesh to be mapped to a dynamic array to aid in defining a restricted topology, in accordance with an embodiment of the present invention. The basic grid can be used to assist, and the linear features are arranged in parallel in the layers of the dynamic array with appropriate optimized spacing. Although the physical grid definition is not physically Being part of a dynamic array, but it can be viewed as a mapping on layers of the dynamic array; in addition, it should be understood that the basic grid is mapped in a manner that is substantially consistent with respect to locations on the layers of the dynamic array, such Auxiliary precise feature stacking and alignment.

In the exemplary embodiment of FIG. 3A, the basic grid is defined as a rectangular grid (ie, a right angle basic grid) according to the first reference direction (x) and the second reference direction (y). The spacing of the grid points to the grid points in the first and second reference directions may be defined as needed to be able to define a linear feature having an optimum feature to the spacing of the features; further, in the first direction (x) The upper lattice spacing may be different from the second orientation (y). In one embodiment, a single basic grid is mapped throughout the die so that various different linear features in each layer can be placed throughout the die; however, in other embodiments, individual bases can be The grid maps over separate regions of the die to support different spacing requirements between features within separate regions of the die. 3B shows an independent basic grid to be mapped to separate regions of the entire die in accordance with an exemplary embodiment of the present invention.

The basic grid is defined in terms of the optical interaction function (ie, the sinc function and manufacturing performance), which is defined by the equipment and process to be used to fabricate the dynamic array. With regard to the light interaction function, the basic grid is defined such that the spacing between the grid points can arrange the peaks as a sinc function describing the light energy mapped to the adjacent grid points. Therefore, the linear feature optimized for lithography enhancement can be specifically specified by pulling the straight line from the first lattice point to the second lattice point, wherein the straight line represents a rectangular structure of a specific width. It should be understood that various linear features in each layer can be specified based on their position on the basic grid and its length.

3C shows an exemplary linear feature defined to be compatible with a dynamic array, in accordance with an embodiment of the present invention. The linear feature 301 has a substantially rectangular cross section defined by a width 303 and a height 307, and the linear feature 301 extends in a linear direction to a length 305. In one embodiment, the cross-section of the linear feature 301, as defined by its width 303 and height 307, is substantially uniform along its length; however, it should be understood that the lithographic effect may cause linear features. Circle at the end of 301 Chemical. The first and second reference directions (x) and (y) shown in FIG. 3A are used to illustrate the exemplary orientation of the linear features on the dynamic array, respectively, and it should be understood that the linear features 301 can be positioned such that they are 305 in length. Extending in a first reference direction (x), a second reference direction (y), or a diagonal direction relative to the first and second reference directions (x) and (y). Regardless of the particular orientation of the linear features with respect to the first and second reference directions (x) and (y), it should be understood that the linear features are defined on a plane substantially parallel to the top surface of the substrate on which the dynamic array is disposed. Again, it should be understood that the linear features have no curved portion (i.e., direction change) in the plane defined by the first and second reference directions.

FIG. 3D shows another exemplary linear feature 317 that is defined to be compatible with a dynamic array, in accordance with an embodiment of the present invention. The linear feature portion 317 has a trapezoidal cross-section defined by a lower width 313, an upper width 315, and a height 309, and the linear feature portion 317 extends in a linear direction to a length 311. In one embodiment, the cross-section of the linear feature 317 is substantially uniform in its length 311; however, it should be understood that the lithographic effect may cause rounding of the ends of the linear feature 317. The first and second reference directions (x) and (y) shown in FIG. 3A are used to illustrate the exemplary orientation of the linear features on the dynamic array, respectively, and it should be understood that the linear features 317 can be positioned such that their lengths are 311. Extending in a first reference direction (x), a second reference direction (y), or a diagonal direction relative to the first and second reference directions (x) and (y). Regardless of the particular orientation of the linear features 317 with respect to the first and second reference directions (x) and (y), it should be understood that the linear features 317 are defined to be substantially parallel to the plane of the top surface of the substrate on which the dynamic array is disposed. on. Also, it should be understood that the linear feature portion 317 has no curved portion (i.e., a change in direction) in a plane defined by the first and second reference directions.

Although the linear features having a rectangular and trapezoidal cross-section are clearly discussed in Figures 3C and 3D, respectively, it will be appreciated that linear features having other cross-sectional types may also be defined within the dynamic array. Thus, essentially any linear feature suitable for the cross-sectional shape can be used as long as the linear feature is defined to have a length extending in one direction and positioned such that its length is along the first reference direction (x), the second reference The direction (y) may extend in a diagonal direction with respect to the first and second reference directions (x) and (y).

The layout of the dynamic array follows the basic grid pattern. Therefore, lattice points can be used to represent where the change in direction occurs during diffusion, where the gate and metal features are placed, where the contacts are located, where the openings in the linear gates and metal features are located, etc. . The spacing between grid points (ie, the spacing of grid points to grid points) should be set for a particular feature line width (eg, width 303 in Figure 3C) to expose the adjacent line features of the particular feature line width. The ones will be reinforced with each other, wherein the linear features are concentrated on the grid points. In one embodiment, referring to the dynamic array stack of FIG. 2 and the exemplary grid of FIG. 3A, the grid spacing on the first reference direction (x) is set by the desired gate pitch. In this same embodiment, the grid spacing between the second reference direction (y) is set by the metal 1 and metal 3 pitch, for example, in the 90 nm process technology (ie, the minimum feature size is equal to 90 nm). The grid spacing between the two reference directions (y) is about 0.24 microns. In one embodiment, the metal 1 and metal 2 layers will have a common spacing and spacing, but different spacings and spacings may be used above the metal 2 layers.

A variety of different dynamic array layers are defined such that the linear features in adjacent layers extend in a manner that intersects each other. For example, the linear features of adjacent layers may extend in an orthogonal manner, that is, perpendicular to each other; further, the linear features of one layer may extend across the linear features of the adjacent layers at an angle (eg, about 45 degrees). For example, in one embodiment, the linear features of one layer extend along a first reference direction (x), while the linear features of adjacent layers are diagonal to the first (x) and second (y) reference directions. extend. It should be understood that in order to be designed in a dynamic array having linear features disposed in an intersecting manner on adjacent layers, openings may be defined in the linear features, while contacts and vias may be defined as desired.

The dynamic array minimizes the use of curved portions in the layout shape to eliminate unpredictable lithographic interactions. In particular, the dynamic array allows bending in the diffusion layer to control device size prior to performing OPC or other RET processing, but does not allow for curved portions in the film layer above the diffusion layer. The layout features in the layers above the diffusion layer are rectilinear (e.g., Figure 3C) and are disposed in parallel with each other. The linear shape and parallel arrangement of the layout features are performed with constructive light interference Predictability in each of the stacked dynamic arrays to ensure manufacturability. In one embodiment, the linear shape and parallel arrangement of the layout features are performed in a dynamic array of each of the layers above the diffusion through metal 2. Above the metal 2, the layout features may have sufficient dimensions and shape that do not require constructive light interference to ensure manufacturability; however, constructive light interference may be beneficial when patterning the layout features above the metal 2. .

An example of adding a dynamic array layer by diffusion through metal 2 is described with reference to FIGS. 4 through 14. It should be understood that the dynamic array illustrated with respect to Figures 4 through 14 is provided as an example only and should not be considered as limiting the dynamic array structure. Dynamic arrays can be used in accordance with the principles described herein to substantially define any integrated circuit design.

4 shows a diffusion layer layout illustrating a dynamic array in accordance with an embodiment of the present invention. The diffusion layer of Figure 4 shows a p-diffusion region 401 and an n-diffusion region 403. When the diffusion region is defined according to the underlying basic grid, the diffusion region is not limited by the linear features associated with the film layer above the diffusion layer. The diffusion regions 401 and 403 include a diffusion block 405 defined at which a diffusion junction is to be provided. The diffusion regions 401 and 403 do not include extraneous protrusions or corners, which improves the use of the lithography resolution and enables more accurate The device is taken out. In addition, the n+ mask regions (412 and 416) and the p+ mask regions (410 and 414) are defined as rectangles having no extraneous projections or notches on the (x), (y) grid. A larger diffusion region is used, OPC/RET is not required, and a lower resolution and less cost lithography system can be used, such as i-line illumination at 365 nm. It should be understood that the n+ mask region 416 and the p+ mask region 410 as shown in FIG. 4 are for embodiments that do not use well-biasing, while in another embodiment where sufficient bias is used, The n+ mask region 416 shown in Figure 4 will actually be defined as a p+ mask region. Moreover, in this alternative embodiment, the p+ mask region 410 shown in Figure 4 will actually be defined as an n+ mask region.

5 shows a gate layer and a diffusion contact layer, which are located above and adjacent to the diffusion layer of FIG. 4, in accordance with an embodiment of the present invention. As will be apparent to those skilled in the art of CMOS, the gate feature 501 defines a transistor gate, and we define the gate feature 501 as a parallel relationship along the second reference. The test direction (y) traverses the linear features of the dynamic array. In one embodiment, the gate features 501 are defined to have a common width; however, in another embodiment, one or more gate features can be defined to have different widths, such as shown in FIG. The gate feature 501A has a larger width than the other gate features 501. The distance between the gate features 501 (center-to-center spacing) is minimized while ensuring optimal lithography enhancement (i.e., resonant imaging) by adjacent gate features 501. For purposes of discussion, the gate feature 501 that extends across a dynamic array along a particular line is referred to as a gate track.

When the gate features 501 pass through the diffusion regions 403 and 401, n-channel and p-channel transistors are formed, respectively. The optimal gate feature 501 printing is achieved by plotting the gate feature 501 at each grid location, even though there may be no diffusion regions at the same grid location; in addition, within the dynamic array Medium, long continuous gate features 501 tend to improve the line end shortening effect at the ends of the gate features. Also, when all of the curved portions are removed from the gate features 501, the gate printing is significantly improved.

To provide the required electrical connections for the particular logic function to be performed, each gate track can be interrupted (i.e., interrupted) any number of times in a manner that traverses the dynamic array in a straight line. When it is desired to interrupt a particular gate track, the spacing between the ends of the gate track segments at the break point is minimized to the extent that manufacturing effects and electrical effects may be considered. In one embodiment, optimum manufacturability is achieved when a common end-to-end spacing is employed between features within a particular layer.

Minimizing the spacing between the ends of the gate track segments at the break point maximizes the lithography enhancement and uniformity provided by the adjacent gate tracks. In addition, in an embodiment, if adjacent gate tracks need to be interrupted, the adjacent gate tracks are interrupted in such a manner that the individual break points are offset from each other to avoid interruption of adjacent points as much as possible. More specifically, the break points in adjacent gate tracks are respectively set such that the line of sight does not exist at all break points, wherein the line of sight is considered to extend perpendicular to the direction in which the gate track extends above the substrate. In addition, in an embodiment, the gate can be extended This embodiment enables the neighboring cells to bridge beyond the boundary at the top or bottom of the grid (ie, the PMOS or NMOS grid).

Referring again to Figure 5, a diffusion joint 503 is defined at each diffusion block 405 to enhance the printing of the diffusion joint via resonance imaging. A diffusion block 405 is present adjacent each of the diffusion contacts 503 to enhance the printing of the power and ground connection polygons at the diffusion contacts 503.

The gate feature 501 and the diffusion contact 503 share a common grid pitch; more specifically, the gate feature 501 is offset from the diffusion junction 503 by a 1/2 grid pitch. For example, if the grid pitch of the gate feature portion 501 and the diffusion contact 503 is 0.36 μm, the diffusion contact is set such that the x coordinate of the center falls on an integral multiple of 0.36 μm, and each gate feature 501 The x coordinate of the center minus 0.18 μm should be an integer multiple of 0.36 μm. In the present embodiment, the x coordinate system is represented by the following formula: the x coordinate of the center of the diffusion joint = I * 0.36 μm, where I is the number of grids; the x coordinate of the center of the gate feature is 0.18 μm + I * 0.36 μm, where I is the number of grids.

The basic grid system of the dynamic array ensures that all contacts (diffusion and gate) will fall on a horizontal grid equal to a multiple of one-half of the diffusion joint grid and a vertical grid set by the metal 1 spacing. In the above embodiment, the gate feature and the diffusion contact grid are 0.36 μm, and the diffusion contact and the gate contact will fall on a horizontal grid that is a multiple of 0.18 μm; in addition, the vertical network of the 90 nm process technology The grid is about 0.24 μm.

6 shows a gate contact layer, as defined above and adjacent to the gate layer of FIG. 5, in accordance with an embodiment of the present invention. In the gate contact layer, the gate contact 601 is drawn such that the gate feature 501 can be connected to the overlying metal wire. In general, the design rule will specify the optimal configuration of the gate contact 601. In one embodiment, the gate contact is drawn on top of the transistor end capping area, when the design rule specifies the long shape. In the case of a crystal end sheath, this embodiment minimizes the white space in the dynamic array. In some process technologies, the white space can be minimized by placing a plurality of grid gate contacts in the center of the grid; in addition, it should be understood that in the present embodiment, the gate junction 601 It is oversized in a direction perpendicular to the gate feature 501 to ensure overlap between the gate contact 601 and the gate feature 501.

Figure 7A shows a conventional method for contacting a gate, such as a polysilicon feature. In the conventional structure of FIG. 7A, an enlarged rectangular gate region 707 in which a gate contact 709 is provided is defined. This enlarged rectangular gate region 707 introduces a bend of a distance 705 in the gate, and amplifies the rectangular gate. The curvature associated with region 707 creates an undesirable optical interaction and distort gate line 711. When the gate width is about the same as the length of the transistor, the distortion of the gate line is particularly problematic.

Figure 7B shows a gate contact 601 (e.g., a polysilicon contact) as defined in accordance with an embodiment of the present invention. The gate contact 601 is drawn to overlap the edge of the gate feature 501 and extends in a direction substantially perpendicular to the gate feature 501. In one embodiment, the gate contact 601 is drawn such that the vertical dimension 703 is the same as the vertical dimension for the diffusion joint 503. For example, if the opening of the diffusion contact 503 is set at 0.12 μm x 0.12 μm, the vertical dimension of the gate contact 601 is plotted at 0.12 μm. However, in other embodiments, the gate contact 601 can be drawn such that the vertical dimension 703 is different from the vertical dimension used for the diffusion joint 503.

In one embodiment, the extension 701 of the gate contact 601 other than the gate feature 501 is set such that the maximum overlap occurs between the gate contact 601 and the gate feature 501, and the extension 701 is It is defined to accommodate the line end shortening effect of the gate contact 601 and the misalignment between the gate contact layer and the gate feature layer. The length of the gate contact 601 is defined to ensure maximum surface area contact between the gate contact 601 and the gate feature 501, wherein the maximum surface area contact is defined by the width of the gate feature 501.

Figure 8A shows a metal 1 layer, as defined above and adjacent to the gate contact layer of Figure 6, in accordance with an embodiment of the present invention. The metal 1 layer comprises a plurality of metal 1 tracks 801-821, which are defined to include linear features that extend across the dynamic array in a parallel relationship. In the lower gate layer of FIG. 5, the metal 1 tracks 801-821 extend in a direction substantially perpendicular to the gate features 501, thus, in this example, The metal 1 rails 801-821 extend linearly across the dynamic array along the first reference direction (x), and the distance between the metal 1 rails 801-821 (center-to-center spacing) is minimized while ensuring that the adjacent metal 1 track 801-821 Optimized lithography enhancement (ie, resonance imaging). For example, in one embodiment, the metal 1 tracks 801-821 are concentrated on a vertical grid of about 0.24 μm for 90 nm process technology.

To provide the required electrical connections for the particular logic function to be performed, each metal 1 track 801-821 can be interrupted (i.e., interrupted) any number of times in a manner that traverses the dynamic array in a straight line. When it is desired to interrupt a particular metal 1 track 801-821, the spacing between the ends of the metal 1 track segments at the break point is minimized to the extent that manufacturing effects and electrical effects may be considered. Minimizing the spacing between the ends of the metal 1 track segments at the break point maximizes the lithography enhancement and uniformity provided by the adjacent metal 1 tracks. In addition, in an embodiment, if the adjacent metal 1 tracks need to be interrupted, the adjacent metal 1 tracks are interrupted in such a manner that the individual interruption points are offset from each other to avoid interruption of the adjacent points as much as possible. More specifically, the break points in the adjacent metal 1 tracks are respectively set such that the line of sight does not exist at all break points, wherein the line of sight is considered to extend perpendicular to the direction in which the metal 1 track extends above the substrate.

In the embodiment of Figure 8A, the metal 1 track 801 is connected to a ground supply and the metal 1 track 821 is connected to a power supply voltage. In the embodiment of FIG. 8A, the widths of the metal 1 rails 801 and 821 are the same as those of the other metal 1 rails 803-819; however, in another embodiment, the width of the metal 1 rails 801 and 821 is greater than that of the other metal 1 rails 803- 819 width. Figure 8B shows the metal 1 layer of Figure 8A with metal 1 ground and power rails (801A and 821A) having a larger track width relative to the other metal 1 tracks 803-819.

The metal 1 track pattern is optimally used to optimize the use of "white spaces" (spaces not occupied by the transistors). The embodiment of Figure 8A includes two shared metal 1 power rails 801, 821 and nine metal 1 signal rails 803-819. Metal 1 tracks 803, 809, 811 and 819 are defined as gate contact tracks to minimize white space; metal 1 tracks 813, 815 and 817 are defined to connect the p-channel source and drain; In addition, if no connection is required, any of the nine metal 1-signal tracks 803-809 can be utilized as a feedthrough, for example, metal 1 tracks 813 and 815 are used as feedthrough connections.

Figure 9 shows a via 1 layer, which is defined above and adjacent to the metal 1 layer of Figure 8A, in accordance with an embodiment of the present invention. A via 901 is defined in the via 1 layer to connect the metal 1 rails 801-821 to the higher height conductors.

Figure 10 shows a metal 2 layer, as defined above and adjacent to the via 1 layer of Figure 9, in accordance with an embodiment of the present invention. The metal 2 layer comprises a plurality of metal 2 tracks 1001 defined as extending in a horizontal direction across the linear features of the dynamic array, the metal 2 tracks 1001 being substantially perpendicular to the metal 1 track 801 in the lower metal layer 1 of Figure 8A. The direction of 821 extends substantially parallel to the direction of the gate track 501 in the lower gate layer of FIG. As such, in the present embodiment, the metal 2 track 1001 extends straight across the dynamic array in the second reference direction (y).

The distance between the metal 2 tracks 1001 (center-to-center spacing) is minimized while ensuring that the lithographic enhancement provided by the adjacent metal 2 tracks is optimized (ie, resonant imaging). It should be understood that the regularity can be maintained at a higher level of interconnect layers than in the gate and metal 1 layers. In one embodiment, the gate feature 501 pitch and the metal 2 track pitch are the same. In another embodiment, the contact gate pitch (e.g., polysilicon to polysilicon spacing with diffusion junctions therebetween) is greater than the metal 2 track pitch. In this embodiment, the metal 2 track pitch is arbitrarily set to 2/3 or 3/4 of the contact gate pitch, and thus, in this embodiment, the gate track and the metal 2 track are at every two gates. The track pitch is aligned with every three metal 2 track pitches. For example, in the 90 nm process technology, the optimum contact gate track pitch is 0.36 μm, and the optimum metal 2 track pitch is 0.24 μm. In another embodiment, the gate track and the metal 2 track are aligned at every three gate pitches and every four metal 2 pitches. For example, in the 90 nm process technology, the optimum contact gate track pitch is 0.36 μm, and the optimum metal 2 track pitch is 0.27 μm.

To provide the required electrical connections for the particular logic function to be performed, each metal 2 track 1001 can be interrupted (i.e., interrupted) any number of times in a manner that traverses the dynamic array in a straight line. When interrupts are needed When a particular metal 2 track 1001, the spacing between the ends of the metal 2 track segments at the break point is minimized to the extent that manufacturing effects and electrical effects may be considered. Minimizing the spacing between the ends of the metal 2 track segments at the break point maximizes the lithography enhancement and uniformity provided by the adjacent metal 2 tracks. In addition, in an embodiment, if the adjacent metal 2 tracks need to be interrupted, the adjacent metal 2 tracks are interrupted in such a manner that the individual interruption points are offset from each other to avoid interruption of adjacent points as much as possible. More specifically, the break points in the adjacent metal 2 tracks are respectively set such that the line of sight does not exist at all break points, wherein the line of sight is considered to extend perpendicular to the direction in which the metal 2 track extends above the substrate.

As described above, the wires in a particular metal layer above the gate layer may extend through the dynamic array in a direction that coincides with the first reference direction (x) or the second reference direction (y); it should be more clear: one according to the present invention In an embodiment, the wires in a particular metal layer above the gate layer may traverse the dynamic array relative to a first diagonal direction of the first reference direction (x) and the second reference direction (y). Figure 12 shows a conductor track 1201 traversing a dynamic array along a second diagonal direction relative to the first and second reference directions (x) and (y), in accordance with an embodiment of the present invention.

As discussed above with respect to the metal 1 and metal 2 tracks, to provide the desired electrical connections for the particular logic function to be performed, the cross-diagonal conductor tracks 1101 and 1201 of Figures 11 and 12 can be linearly traversed dynamically. The way the array is interrupted (ie interrupted) any number of times. When it is desired to interrupt a particular conductor track that traverses the diagonal, the spacing between the ends of the diagonal conductor tracks at the point of interruption is minimized to the extent that manufacturing effects and electrical effects may be considered. Minimizing the spacing between the ends of the diagonal conductor tracks at the break point maximizes the lithography enhancement and uniformity provided by adjacent diagonal conductor tracks.

The optimal layout density in the dynamic array is achieved by implementing the following design rules: setting at least two metal 1 tracks across the n channel device area; setting at least two metal 1 tracks across the p channel device area; setting at least two n channel devices Two gate tracks; At least two gate tracks are provided for the n-channel device.

From the point of view of lithography, the contacts and through holes become the most difficult masks, because the contacts and through holes are shrinking, closer, and more disorderly. The distance and density between the cuts (contacts or vias) makes it extremely difficult to reliably print the shape, for example the shape of the cut may be incorrectly due to destructive interference from adjacent shapes or lack of energy in a separate shape. Printed out. If the cut marks are printed correctly, the manufacturing yield of the relevant joints or through holes is extremely high. The secondary resolution contact can be set to enhance the exposure of the real contact, as long as the secondary resolution contact does not disintegrate; and the secondary resolution contact can have any shape as long as it is smaller than the resolution capability of the lithography process. .

FIG. 13A shows an embodiment of a secondary resolution contact layout for enhancing diffusion contacts and gate contacts by lithography, in accordance with an embodiment of the invention. FIG. The sub-resolution contact 1301 is formed such that it is below the resolution of the lithography system and will not be printed. The function of the sub-resolution contact 1301 is to increase the position of the desired contact through resonance imaging ( For example, 503, 601) light energy. In one embodiment, the sub-resolution contact 1301 is disposed on the grid such that both the gate contact 601 and the diffusion contact 503 are lithographically enhanced, for example, the sub-resolution contact 1301 is disposed at A grid equal to one-half the grid spacing of the diffusion joints 503 has a positive effect on both the gate contacts 601 and the diffusion contacts 503. In one embodiment, the vertical spacing of the secondary resolution contacts 1301 follows the vertical spacing of the gate contacts 601 and the diffusion contacts 503.

The grid position 1303 in Fig. 13A indicates the position between adjacent gate contacts 601. Depending on the lithography parameters in the manufacturing process, the secondary resolution contact 1301 at this grid location will likely establish an undesired bridge between two adjacent gate contacts 601. If a bridge is likely to occur, the secondary resolution contact 1301 at location 1303 can be omitted. Although FIG. 13A is an embodiment showing that the secondary resolution contact 1301 is disposed adjacent to the real feature to be resolved, it should be understood that another embodiment may set the secondary resolution contact to each available network. Position the grid to fill the grid.

Figure 13B shows the sub-resolution joint layout of Figure 13A, which defines the sub-resolution joints to fill the grid to the extent possible, in accordance with an embodiment of the present invention. It should be understood that although the embodiment of FIG. 13B fills the grid as much as possible with the sub-resolution contacts, the secondary resolution contacts are prevented from being placed in locations that are likely to cause undesired bridging between adjacent fully resolved features. At the office.

Figure 13C shows an embodiment of a sub-resolution joint layout in accordance with an embodiment of the invention, which utilizes sub-resolution contacts of various shapes. The other resolution contact shape can be utilized as long as the secondary resolution contact is below the resolution of the manufacturing program. Figure 13C shows the use of an "X-shaped" secondary resolution contact 1305 that concentrates light energy at the corners of adjacent contacts. In one embodiment, the ends of the "X-shaped" secondary resolution contacts 1305 are extended to more enhance the deposition of light energy at the corners of adjacent contacts.

Figure 13D shows an exemplary completion diagram of a converted phase shift mask (APSM) with sub-resolution contacts, in accordance with an embodiment of the present invention. As in FIG. 13A, the diffusion contact 503 and the gate contact 601 are reinforced by the lithography using the sub-resolution contact, and the APSM is used to improve the resolution when the adjacent shape produces a destructive interference pattern. The APSM technique modifies the mask such that the phase of the light traveling through the mask on the adjacent shape is 180 degrees out of phase, the function of this phase shifting to remove destructive interference and allow for a larger joint density. For example, the contact marked with a positive sign "+" in Fig. 13D represents the contact exposed by the light wave of the first phase, and the contact marked with the minus sign "-" represents a phase shift of 180 with respect to the first phase. The light wave of the degree is exposed to the contact. It should be understood that we use APSM technology to ensure that adjacent contacts are separated from one another.

As the feature size decreases, the semiconductor die can contain more gates; however, as more gates are included, the density of the interconnect layers begins to dominate the die size. This increasing demand on the interconnect layer forces a higher level of interconnect layer; however, the stack of interconnect layers is partially limited by the topology of the lower layer, such as when interconnecting layers are established. The islands, ridges, and trenches are created, and these islands, ridges, and trenches can cause interruptions in the interconnects that pass over them.

To reduce these islands and trenches, the semiconductor process utilizes a chemical mechanical polishing (CMP) process to mechanically and chemically polish the surface of the semiconductor wafer such that each subsequent interconnect layer is on a substantially planar surface. Like the photolithography program, the quality of the CMP program is related to the layout pattern; in particular, the uneven distribution of the layout features on the entire die or wafer may cause excessive material removal in some places and excessive removal of material in other places. This results in variations in interconnect thickness and unacceptable variations in the capacitance and resistance of the interconnect layers. Capacitance and resistance variations in the interconnect layers can change the timing of critical networks that cause design failure.

The CMP program requires the addition of a dummy fill to the area of the interconnectless shape so that a substantially uniform wafer topology can be set, avoiding dishing effects and improving center-to-edge uniformity. Conventionally, the virtual fill system is set in the post-design phase, so that in the conventional method, the designer does not know the virtual fill feature. Therefore, the virtual fill set in the post-design phase may adversely affect the design performance in a manner that has not been evaluated by the designer; in addition, since the conventional topology before virtual fill is unconstrained (ie, non-uniform) Therefore, the virtual fill will be uneven and unpredictable after design. Therefore, in the prior art, the capacitive coupling between the virtual filled area and the adjacent active network cannot be predicted by the designer.

As previously described, the dynamic array disclosed herein provides optimal regularity by maximizing the filling of all interconnect tracks from the gate layer. If multiple meshes are required in a single interconnect track, the interconnect track is separated with a minimum separation gap. For example, the track 809 representing the metal 1 wire in FIG. 8A represents three independent nets in the same track, each of which corresponds to a special track segment; more specifically, there are two multi-contact networks and a floating point network. To fill the track with the smallest spacing between the track segments. The substantially complete track fill maintains a regular pattern of resonant images produced throughout the dynamic array; in addition, the regular structure of the dynamic array with the largest filled interconnect track ensures that the virtual fill is placed in the entire crystal in a uniform manner In the grain. Thus, the regular structure of the dynamic array assists the CMP process to produce substantially uniform results across the die/wafer. Also, the regular structure of the dynamic array contributes to gate etching Uniformity (microloading); in addition, the regular structure of the dynamic array combined with the largest filled interconnect track allows the designer to analyze the capacitive coupling effects associated with the largest fill track during the design phase and before fabrication.

Because the dynamic array sets the size and spacing of the linear features (i.e., tracks and contacts) in each mask layer, the dynamic array can be optimized for maximum performance of the manufacturing equipment and program. In other words, since each layer above the diffusion layer limits the dynamic array to a regular structure, the manufacturer can optimize the manufacturing process for the specific features of the regular structure. It should be understood that with this dynamic array, the manufacturer does not need to be concerned with the manufacturing conditions of any shape layout feature combination that takes into account significant variations, as in conventional unconstrained layouts.

An example of how to optimize the performance of a manufacturing facility is provided below. Consider a 90 nm process with a metal 2 pitch of 280 nm. This 280 nm metal 2 pitch is not set with the maximum performance of the device; rather, it is set by the lithography of the via. The controversy over the removal of through-hole lithography, the maximum performance of the device allows for a metal 2 pitch of about 220 nm. Thus, the design rule for metal 2 pitch contains a tolerance of about 25% to account for the unpredictable optical interaction in the via lithography. Sex.

The regular structure performed within the dynamic array allows for the unpredictability of the optical interaction in the via lithography to be removed, thus reducing the tolerance of the metal 2 pitch. This reduction in the tolerance of the metal 2 pitch allows for a denser design, which allows for optimization of wafer area utilization; in addition, the design rules can be reduced by using the defined (ie, regular) topology provided by the dynamic array. The above tolerances; in addition, not only can the excess margin beyond program performance be reduced, but the limited topology provided by the dynamic array also substantially reduces the number of required design rules. For example, a typical set of design rules for an unconstrained topology may have more than 600 design rules, but a set of design rules required to use a dynamic array may have only about 45 design rules. Therefore, with the limited topology of the dynamic array, the effort required to analyze and validate the design against the design rules can be reduced by more than 10 times.

When dealing with line end-to-line end gaps (ie, track segments to track segment gaps) in a particular track of a mask layer of a dynamic array, there is a finite number of light intersections. Interaction. This limited number of optical interactions can be identified, predicted, and accurately compensated in advance, thus dramatically reducing or completely eliminating the need for OPC/RET. The compensation for the optical interaction at the line-to-line gap represents a lithographic correction of the features as shown, which is suitable for modeling based on interactions (associated with features as shown) The correction (eg OPC/RET) is reversed.

Furthermore, with dynamic arrays, changes to the layout as shown are only performed where necessary; conversely, OPC is implemented over the entire layout of the conventional design flow. In an embodiment, a modified model may be implemented as part of the layout of the dynamic array, for example, due to a limited number of possible line-end gap interactions, the router may be programmed to have the definition A line break characterized by a function of its environment (ie, a function of its special line-end gap interaction). It should be clearer that the regular structure of the dynamic array allows the line ends to be adjusted by changing the vertices instead of adding vertices. Thus, the dynamic array significantly reduces the cost and risk of mask production against the unconstrained topology of the OPC program. . Also, because the line-end gap interactions in the dynamic array can be accurately predicted in the design phase, the compensation for predicting line-end gap interactions during the design phase does not increase the risk of design failure.

In the conventional unconstrained topology, because of the design-dependent failure, the designer must have the physics knowledge associated with the manufacturing process; and with the basic grid system of the dynamic array disclosed herein, the logic design can be used. Separate from physical design. More specifically, using the regular structure of the dynamic array, the limited number of optical interactions to be evaluated in the dynamic array and the nature of the dynamic array independent of the design can be represented by a grid grid netlist. Designed, as opposed to a physical network connection table.

With dynamic arrays, the design does not need to be represented by physical information; moreover, the design can be represented by a symbolic layout. In this way, the designer can represent the design from a purely logical point of view without representing physical features (such as the size of the design). It should be understood that when the basic mesh network connection is translated into a physical network connection, it matches the optimal design rules that are actually used for the dynamic array platform. When the basic grid is dynamically moved When it comes to new technologies (ie, smaller technologies), basic mesh network connections can be moved directly to new technologies because there is no physical data in the design representation. In an embodiment, the basic grid dynamic array system includes a rule database, a basic grid (symbolic) network connection, and a dynamic array structure.

It should be understood that the basic grid dynamic array eliminates the topology-related errors associated with the conventional unconstrained structure; in addition, because the manufacturability of the basic grid dynamic array is not related to the design, the design performed on the dynamic array is good. The rate is also not about design. Therefore, since the correctness and yield of the dynamic array are confirmed in advance, the basic mesh network connection can be performed on the dynamic array by confirming the yield performance in advance.

Figure 14 shows a semiconductor wafer structure 1400 in accordance with an embodiment of the present invention. Semiconductor wafer structure 1400 represents an exemplary portion of a semiconductor wafer that includes a diffusion region 1401 having a plurality of conductors 1403A-1403G defined thereon. The diffusion zone 1401 is defined in the substrate 1405 to define an active region for at least one of the transistor devices. The diffusion region 1401 can be defined to cover any shape region relative to the surface of the substrate 1405.

The wires 1403A-1403G are disposed to extend over the substrate 1405 in a common direction 1407. It should also be understood that each of the plurality of wires 1403A-1403G is constrained to extend above the diffusion region 1401 in a common direction 1407. . In one embodiment, the wires 1403A-1403G directly defined above the substrate 1405 are polysilicon wires. In one embodiment, each of the wires 1403A-1403G is defined to have substantially the same width 1409 in a direction perpendicular to the common direction of extension 1407. In another embodiment, some of the wires 1403A-1403G are defined to have different widths relative to other wires. However, regardless of the width of the wires 1403A-1403G, each of the wires 1403A-1403G is separated from the adjacent wires by substantially the same center-to-center spacing 1411.

As shown in FIG. 14, some of the wires (1403B-1403E) extend over the diffusion region 1401, while other wires (1403A, 1403F, 1403G) extend over the non-diffused portion of the substrate 1405. It should be understood that whether or not the wires 1403A-1403G are defined above the diffusion region 1401, the wires 1403A-1403G maintain their Width 1409 and spacing 1411; in addition, it should be understood that whether or not the wires 1403A-1403G are defined above the diffusion region 1401, the wires 1403A-1403G substantially maintain the same length 1413, thereby making the wires 1403A-1403G on the entire substrate. The lithography enhancement between the two is maximized. In this manner, certain wires (e.g., 1403D) defined above the diffusion region 1401 include a necessary active portion 1415 and more than one uniformity extension portion 1417.

It will be appreciated that the semiconductor wafer structure 1400 represents a portion of the dynamic array described above with respect to Figures 2-13D, and therefore, it should be understood that there is a uniformity extension 1417 of the wires (1403B-1403E) to provide lithographic enhancement of adjacent wires 1403A-1403G. . Additionally, although it is not required for circuit operation, each of wires 1403A, 1403F, 1403G is present to provide lithographic enhancement of adjacent wires 1403A-1403G.

The necessary active portion 1415 and uniformity extension portion 1417 are also suitable for higher level interconnect layers. As previously described with respect to the dynamic array structure, adjacent interconnect layers traverse the substrate in a cross-sectional direction (eg, vertical or diagonal) to enable routing required by logic devices executing within the dynamic array (routing) ) / Connectivity is possible. As with wires 1403A-1403G, each wire within the interconnect layer may contain a necessary portion (required active portion) to enable routing/connectivity; and may include non-essential portions (uniform extension), Provide lithography enhancement to adjacent wires. Again, as with wires 1403A-1403G, the wires within the interconnect layer extend over the substrate in a common direction and have substantially the same width and are spaced apart from one another by a substantially fixed spacing.

In one embodiment, the wires in the interconnect layer substantially follow the same ratio between the line width and the line pitch, for example, at 90 nm, the metal pitch is 280 nm, and the line width and line pitch are both equal to 140 nm. If the line width is equal to the line spacing, the larger wire can be printed on a larger line spacing.

The invention described herein can be embodied in a computer readable medium in the form of a computer readable medium, which is a data storage device that can store data that can be read by a computer system, and a computer readable medium. Examples include hard drives, network attached storage (NAS), read-only memory, random Access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tape, and other optical or non-optical data storage devices. The computer readable medium can also be distributed over a network coupled to the computer system, so that the computer readable code can be stored and executed in a decentralized manner; in addition, it can be developed in the form of computer readable code for execution on a computer readable medium. A graphical user interface (GUI) to provide a user interface for performing any of the embodiments of the present invention.

While the invention has been described with respect to the embodiments of the embodiments illustrated embodiments Accordingly, the present invention is intended to embrace all such modifications, such

1400‧‧‧Semiconductor wafer structure

1401‧‧‧Diffusion zone

1403A-1403G‧‧‧Wire

1405‧‧‧Substrate

1407‧‧‧The direction of extension of the wire

1409‧‧‧The width of the wire

1411‧‧‧Distance between wires

1413‧‧‧The length of the wire

1415‧‧‧ necessary active part of the conductor

1417‧‧‧A uniformity extension of the wire

Claims (30)

A region of a semiconductor wafer comprising: at least twenty-five gate conductive structure tracks, wherein each gate conductive structure track extends along a respective line oriented in a first reference direction, wherein each gate The conductive structure track includes at least one gate conductive structure, wherein any two gate conductive structures adjacent to each other on the same gate conductive structure track are measured at a distance of less than 193 nm measured in the first reference direction Separating from each other, wherein each gate conductive structure track is separated from an adjacent gate conductive structure track by a distance of less than 193 nm measured in a second reference direction, the second The reference direction is oriented perpendicular to the first reference direction, wherein each gate conductive structure in the region has a substantial in a corresponding gate bisector plane consistent with the first reference direction and the second reference direction a rectangular cross section, the substantially rectangular cross section of a given gate conductive structure in the region being a respective length measured in the first reference direction and at the Defining a respective width measured by the second reference direction, the width of each of the gate conductive structures in the region is less than or substantially equal to 45 nm, wherein each gate conductive structure has the first reference direction Extending a longitudinal centerline, the longitudinal centerline of a given gate conductive structure extending through a midpoint of a width of the given gate conductive structure, the longitudinal centerline of each gate conductive structure being at the gate conductive a gate along which the gate conductive structure track extends, wherein some of the gate conductive structures are disposed in the same region as the diffusion region to form at least one transistor gate electrode; at least one conductive contact a structure formed to physically contact one or more of the gate conductive structures forming at least one of the transistor gate electrodes in the region such that each gate of the at least one transistor gate electrode is formed in the region The pole conductive structure has a respective top surface in physical contact with the at least one electrically conductive contact structure, wherein each electrically conductive contact structure in the region is produced as a separate a structure formed by any gate conductive structure physically in contact with the substrate, wherein the at least one conductive contact structure comprises at least one rectangular contact structure oriented parallel to the gate bisector plane a pair of coping planes having a substantially rectangular horizontal cross section, the substantially rectangular horizontal cross section of each of the at least one rectangular contact structures being greater than the rectangular contact structure by the second reference direction Defining a respective length of the width of the gate conductive structure physically contacting, and wherein the at least one rectangular contact structure is each on the gate conductive structure to which it is physically in contact with the second reference Substantially centered in the direction; at least twenty-fifth interconnecting conductive track formed in an interconnect layer, wherein the at least twenty-fifth interconnected conductive track is oriented along each other Extending a respective line of the second reference direction, wherein the at least twenty-fifth interconnect line conductive structure tracks each comprise at least one interconnect line conductive structure Wherein any two interconnected conductive structures adjacent to each other on the same interconnect conductive structure track are separated from each other by a distance measured in the second reference direction of less than 193 nm, wherein the at least Twenty-five interconnected conductive trackes each separated from an adjacent interconnect conductive track by a distance of less than 193 nm measured in the first reference direction, wherein Each of the interconnecting conductor conductive structures of at least twenty-fifth interconnecting conductive track has a substantially rectangular cross section in a pair of coping planes oriented parallel to the gate bisector plane, a given The substantially rectangular cross section of the interconnected interconnect structure is defined by a respective length measured in the second reference direction and a respective width measured in the first reference direction, wherein the at least twenty-five Each interconnecting wire conductive structure of the interconnecting conductor conductive track has a longitudinal centerline extending in the second reference direction through which the longitudinal centerline of a given interconnecting conductive structure extends a midpoint of a width of the interconnected conductive structure measured in the first reference direction, the longitudinal centerline of each interconnect conductive structure being located along an interconnecting conductive track of the interconnected conductive structure And the at least one dielectric material disposed on the portion of the gate conductive structure of the twenty-five gate conductive structure tracks and the at least twenty-two interconnected conductive structure tracks Between the overlying portions of the wiring conductive structures, wherein the at least one electrically conductive contact structure is each formed to extend through the at least one dielectric material and includes a top of the gate conductive structure formed to be physically opposite thereto a portion of the surface extending vertically, the twenty-five gate conductive structure tracks comprising at least seven gate conductive structures disposed according to a first pitch, the first pitch being in the second reference direction Measured between longitudinal centerlines of the pole conductive structure, the at least seven gate conductive structures comprise a first gate conductive structure, the first gate conductive structure comprising a first transistor a portion of a gate electrode of a first transistor having a first transistor type of any of the gate crystal electrodes formed by the first gate conductive structure, the at least seven gates being electrically conductive The structure includes a second gate conductive structure, the second gate conductive structure including a first portion of a gate electrode forming a second transistor of the first transistor type, the second gate conductive structure comprising the formation a second portion of a gate electrode of the first transistor of the second transistor type, wherein the longitudinal centerline of the first and second gate conductive structures is measured in the second reference direction The distance between the two is substantially equal to the first pitch, and the at least seven gate conductive structures comprise a third gate conductive structure, the third gate conductive structure comprising a second transistor forming the second transistor type a portion of a gate electrode having a second transistor type of any electro-crystalline system having a gate electrode formed by the third gate conductive structure, wherein the measured in the second reference direction The distance between the longitudinal centerlines of the first and third gate conductive structures is substantially equal to an integer multiple of the first pitch, and the at least seven gate conductive structures comprise a fourth gate conductive structure, the fourth gate The conductive structure includes a first portion of a gate electrode forming a third transistor of the first transistor type, the fourth gate conductive structure including a gate forming a third transistor of the second transistor type a second portion of the first electrode, the first transistor of the first transistor type includes a first diffusion region, and the second transistor of the second transistor type includes a first diffusion region, the first The first diffusion region of the first transistor of the transistor type is electrically connected to the first diffusion region of the second transistor of the second transistor type via a first electrical connection, the first The first diffusion region of the first transistor of the crystal type is also used as a diffusion of another transistor of the first transistor type having a gate electrode formed by one of the at least seven gate conductive structures Area, The first diffusion region of the second transistor of the second transistor type is also used as another transistor of the second transistor type having a gate electrode formed by one of the at least seven gate conductive structures a diffusion region of the crystal, wherein each of the first crystal type of the gate electrode having the gate electrode formed by any one of the at least seven gate conductive structures is included in one of the first transistor types Each of the electromorphic systems of the second transistor type of the set of transistors and having a gate electrode formed by any one of the at least seven gate conductive structures is included in one of the second transistor types In a collection of transistors, wherein the collection of transistors of the first transistor type and the collection of transistors of the second transistor type are separated by an internal sub-region of the region, wherein the internal sub-region does not include The source or drain of any transistor, wherein each transistor having a gate electrode formed by either of the at least seven gate conductive structures forms part of more than one logic function. The area of the semiconductor wafer of claim 1, wherein the first electrical connection comprises a plurality of interconnect line conductive structures formed in at least two interconnect layers, the at least two interconnect layers Separating from top surfaces of the gate conductive structures with at least one dielectric material, the interconnect conductive structures of the first electrical connections are each oriented parallel to the gate pair a pair of planar intersecting planes having a substantially rectangular cross section, wherein a first interconnect conductive structure of the first electrical line within one of the at least two interconnect layers The longitudinal centerline is oriented in the first reference direction, and wherein a second interconnect conductive structure of the first electrical line within one of the at least two interconnect layers The longitudinal centerline is oriented in the second reference direction, wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the second transistor type via a second electrical connection a gate electrode of the second transistor, the second electrical line comprising a shape One or more interconnected wire conductive structures within one or more interconnect layers, each of the interconnected wire conductive structures of the second electrical interconnect being each oriented in a direction parallel to the gate bisector plane There is a substantially rectangular horizontal cross section in the response sub-plane. The region of the semiconductor wafer of claim 2, wherein the interconnect layer in which the at least twenty-fifth interconnect conductive structure track is formed is a first interconnect layer, wherein The first interconnect layer is an interconnect layer layer closest to the top surface of the gate conductive structures, and the semiconductor wafer region includes a second interconnect layer layer, the second interconnect layer layer Include at least twenty-two interconnected conductive structure tracks, the at least twenty-two interconnected conductive structure tracks in the second interconnect layer layer being oriented along the first reference direction Extending a plurality of straight lines, the at least twenty-two interconnected conductive structure tracks in the second interconnect layer layer each comprising at least one interconnect line conductive structure, wherein in the second Any two interconnected conductive structures adjacent to each other on the same interconnect conductive structure track among the interconnect layers are spaced apart from each other, at least two of the second interconnect layers Each of the fifteen interconnected conductive structure tracks is in the second reference a distance of less than 193 nm measured in the direction of the test is separated from an adjacent interconnect conductive structure track, and the at least twenty-fifth interconnect line among the second interconnect layers Each interconnecting wire conductive structure of the conductive structure track has a substantially rectangular horizontal cross section in a pair of coping planes oriented parallel to the gate bisector plane, the one of the second interconnect layer layers The substantially rectangular horizontal cross section of each of the interconnecting conductor conductive structures of at least twenty-fifth interconnecting conductive track is measured by a respective length measured in the first reference direction and in the second reference direction Defining a respective width, each interconnecting wire conductive structure of the at least twenty-fifth interconnecting wire conductive structure track among the second interconnecting layers has a first reference direction a longitudinal centerline extending at a midpoint of the width, the longitudinal centerline of each of the at least twenty-fifth interconnecting conductor conductive tracks in the second interconnect layer being located The interconnection of the interconnect conductive structure is electrically conductive The longitudinal centerline of the interconnected conductive structures of the at least twenty-five interconnected conductive track in the second interconnect layer on the line along which the track is extended Configuring the first pitch measured in the second reference direction, the second interconnect layer being separated from the first interconnect layer by at least one dielectric material, the first The second interconnect layer is tied above the first interconnect layer, the second interconnect layer being closest to an interconnect layer of the first interconnect layer. The region of the semiconductor wafer of claim 3, wherein the at least two interconnect layers of the first electrical interconnect comprise the first interconnect layer and the second interconnect layer, and The one or more interconnect layers of the second electrical interconnect include one or both of the first interconnect layer and the second interconnect layer. The region of the semiconductor wafer of claim 4, wherein the interconnected conductive structures within the second interconnect layer within the region of the semiconductor wafer have substantially equal widths. The region of the semiconductor wafer of claim 5, wherein the lines extending along the gate conductive structure track within the region of the semiconductor wafer are based on the measured in the second reference direction The first spacing is configured. The region of the semiconductor wafer of claim 6 further comprising: a third interconnect layer layer comprising a plurality of interconnect line conductive structure tracks each along a respective line oriented in the second reference direction Extending, the plurality of interconnected-line conductive structure tracks in the third interconnect layer layer each comprising at least one interconnect line conductive structure, wherein the same interconnect level among the third interconnect line layers Any two interconnected wire conductive structures adjacent to each other on the wire conductive structure track are separated from each other by a distance measured in the second reference direction of less than 193 nm, at the third interconnect layer The plurality of interconnected conductive structure tracks are each separated from an adjacent interconnect conductive track by a distance of less than 193 nm measured in the first reference direction Wherein each of the plurality of interconnected conductive structures of the plurality of interconnected conductive structures in the third interconnect layer is in a pair of coplanar planes oriented parallel to the gate bisector plane Has a substantially rectangular horizontal cross section, at The substantially rectangular horizontal cross section of the interconnecting conductor conductive structures in the third interconnect layer layer is a respective length measured in the second reference direction and a measured in the first reference direction Each individual width defines each interconnected wire conductive structure having a substantially rectangular horizontal cross section among the third interconnect layers having a longitudinal direction extending through a midpoint of its width in the second reference direction a centerline, wherein the longitudinal centerline of each interconnect conductive structure having a substantially rectangular horizontal cross section among the third interconnect layers is located along an interconnecting conductive track of the interconnect conductive structure On the extended line, the third interconnect layer is separated from the second interconnect layer by at least one dielectric material, the third interconnect layer being tied to the Above the second interconnect layer, the third interconnect layer is closest to an interconnect layer of the second interconnect layer. The region of the semiconductor wafer of claim 6 wherein each of the diffusion regions forming at least one portion of the transistor in the region of the semiconductor wafer is oriented in a pair of coping planes oriented parallel to the gate bisector plane There is a substantially rectangular horizontal cross section inside. The area of the semiconductor wafer of claim 6 wherein the first interconnect layer comprises at least two interconnect line conductive structures having a first width, the first interconnecting direction being disposed with respect to the first reference direction Between two interconnected conductive structures of two widths, wherein the second width is greater than the first width. The region of the semiconductor wafer of claim 6 wherein the first interconnect layer comprises a non-functional interconnect conductive structure that does not form a portion of a functional circuit, the non-functional interconnect conductive structure being relatively The first reference direction is between two adjacent interconnect conductive structures, and wherein the first gate conductive structure has a length different from the third gate conductive structure. The region of the semiconductor wafer of claim 6 wherein the second interconnect layer comprises a non-functional interconnect conductive structure that does not form a portion of a functional circuit, the non-functional interconnect conductive structure being relatively The second reference direction is between two adjacent interconnect conductive structures. The region of the semiconductor wafer of claim 4, wherein the first interconnect layer comprises a plurality of interconnect line conductive structures having at least two different widths. The region of the semiconductor wafer of claim 12, wherein each of the interconnect conductive structures within the first interconnect layer has a first width or a second width. The region of the semiconductor wafer of claim 1, wherein the interconnect layer in which the at least twenty-fifth interconnect conductive structure track is formed is a first interconnect layer, wherein the The first interconnect layer is an interconnect layer layer closest to the top surface of the gate conductive structures, and the semiconductor wafer region includes a second interconnect layer layer, the second interconnect layer layer Include at least twenty-two interconnected conductive structure tracks, the at least twenty-two interconnected conductive structure tracks in the second interconnect layer layer being oriented along the first reference direction Extending a plurality of straight lines, the at least twenty-two interconnected conductive structure tracks in the second interconnect layer layer each comprising at least one interconnect line conductive structure, wherein in the second Any two interconnected conductive structures adjacent to each other on the same interconnect conductive structure track among the interconnect layers are spaced apart from each other, at least two of the second interconnect layers Each of the fifteen interconnected conductive structure tracks is in the second reference a distance of less than 193 nm measured in the direction of the test is separated from an adjacent interconnect conductive structure track, and the at least twenty-fifth interconnect line among the second interconnect layers Each interconnecting wire conductive structure of the conductive structure track has a substantially rectangular horizontal cross section in a pair of coping planes oriented parallel to the gate bisector plane, the one of the second interconnect layer layers The substantially rectangular horizontal cross section of each of the interconnecting conductor conductive structures of at least twenty-fifth interconnecting conductive track is measured by a respective length measured in the first reference direction and in the second reference direction Defining a respective width, each interconnecting wire conductive structure of the at least twenty-fifth interconnecting wire conductive structure track among the second interconnecting layers has a first reference direction a longitudinal centerline extending at a midpoint of the width, the longitudinal centerline of each of the at least twenty-fifth interconnecting conductor conductive tracks in the second interconnect layer being located The interconnection of the interconnect conductive structure is electrically conductive The longitudinal centerline of the interconnected conductive structures of the at least twenty-five interconnected conductive track in the second interconnect layer on the line along which the track is extended Configuring the first pitch measured in the second reference direction, the second interconnect layer being separated from the first interconnect layer by at least one dielectric material, the first The second interconnect layer is tied above the first interconnect layer, the second interconnect layer being closest to an interconnect layer of the first interconnect layer. The region of the semiconductor wafer of claim 14, wherein the at least one electrically conductive contact structure comprises a first electrically conductive contact structure, the first electrically conductive contact structure being at least one of a plurality of transistors forming the first transistor type One of the at least seven gate conductive structures of a gate electrode and a gate electrode of any transistor of the second transistor type is physically and electrically connected, the first conductive contact structure being configured The inner sub-region or a diffusion region is not vertically overlaid with respect to a reference direction perpendicular to the bisector plane of the gate, and wherein the at least one conductive contact structure comprises a second conductive contact structure, the second conductive The contact structure is one of the at least seven gate conductive structures of the gate electrode forming at least one gate electrode of the one or more transistors of the second transistor type and not forming any of the transistors of the first transistor type Physically and electrically connected, the second electrically conductive contact structure being configured to be aligned with respect to the reference plane perpendicular to the plane of the gate Overlying the inner sub-region or a diffusion region, and wherein each of the diffusion regions forming at least one portion of the transistor in the region of the semiconductor wafer is in a pair of coping planes oriented parallel to the gate bisector plane Has a substantially rectangular horizontal cross section. An area of a semiconductor wafer according to claim 15 wherein a portion of any of the first transistor types having a gate electrode formed by either of the at least seven gate conductive structures is formed. Each diffusion region is a portion of the first set of diffusion regions, wherein each diffusion region of the first set of diffusion regions is within a first rectangular region, the first rectangular region being in the first reference direction Defining a range of all diffusion regions that encompass the first set of diffusion regions, the first rectangular region being defined in the second reference direction by a range that encompasses all of the diffusion regions of the first set of diffusion regions Wherein at least two interconnect line conductive structures within the first interconnect layer layer comprise a plurality of portions extending over portions of the first rectangular region, wherein there will be any at least seven gate conductive structures Each of the diffusion regions formed by a portion of any of the second transistor types of the gate electrode formed by the gate electrode is a portion of the second group of diffusion regions, wherein the second group of diffusion regions Each of the diffusion regions is located within a second rectangular region, the second rectangular region being defined in the first reference direction by a range of all diffusion regions that directly encompass the second set of diffusion regions, the second The rectangular region is defined in the second reference direction by a range of all diffusion regions that encompass the second set of diffusion regions, wherein at least two interconnected conductive structures within the first interconnect layer layer comprise a plurality of portions extending above a portion of the second rectangular region. The area of the semiconductor wafer of claim 16 wherein only two interconnect line conductive structures within the first interconnect layer comprise a plurality of portions extending over portions of the first rectangular region. The region of the semiconductor wafer of claim 16 wherein only three interconnected conductive structures within the first interconnect layer comprise a plurality of portions extending over portions of the second rectangular region. The region of the semiconductor wafer of claim 15, wherein a top surface of the first gate conductive structure, a top surface of the second gate conductive structure, and a top surface of the third gate conductive structure The above is in physical and electrical contact with one of the at least one rectangular contact structure. The region of the semiconductor wafer of claim 19, wherein at least one of the first conductive contact structure and the second conductive contact structure is one of the at least one rectangular contact structures. The region of the semiconductor wafer of claim 1, wherein the interconnect layer in which the at least twenty-fifth interconnect conductive structure track is formed is a first interconnect layer, and wherein The region of the semiconductor wafer includes a second interconnect layer, the second interconnect layer comprising a plurality of interconnected conductive structures tracks each extending along a respective line oriented in the first reference direction, The plurality of interconnected wire conductive structure tracks in the second interconnect layer layer each comprising at least one interconnect line conductive structure, wherein the same interconnect line is among the second interconnect line layers Any two interconnecting wire conductive structures adjacent to each other on the conductive structure track are separated from each other by a distance measured in the first reference direction, the number among the second interconnect layer layers The interconnecting conductor conductive track each is separated from an adjacent interconnect conductive track by a distance of less than 193 nm measured in the second reference direction, wherein in the second The number of interconnects in the interconnect layer Each interconnecting wire conductive structure of the conductive structure track has a substantially rectangular horizontal cross section in a pair of coping planes oriented parallel to the gate bisector plane, the one of the second interconnect layer layers The substantially rectangular horizontal cross section of the interconnected conductive structure is defined by a respective length measured in the first reference direction and a respective width measured in the second reference direction, in the second mutual Each interconnect line conductive structure in the wiring layer has a longitudinal center line extending through a midpoint of its width in the first reference direction, each of the second interconnect layer layers The longitudinal centerline of the interconnect conductive structure is located on the line along which the interconnect conductive structure track of the interconnect conductive structure extends, the second interconnect layer being formed by at least one dielectric material Separating from a top surface of the gate conductive structures, the second interconnect layer is separated from the first interconnect layer by at least one dielectric material, wherein the first The interconnect layer is a set of four consecutive One of the interconnect layers of the set, the four consecutively configured interconnect layers of the set are above the top surface of the gate conductive structures and closest to the top surface of the gate conductive structures And wherein the second interconnect layer is layered over the top surface of the gate conductive structures and the four consecutively configured interconnect layers of the set closest to the top surface of the gate conductive structures The other of them. The area of the semiconductor wafer of claim 21, wherein a top surface of the first gate conductive structure, a top surface of the second gate conductive structure, and a top surface of the third gate conductive structure The above is in physical and electrical contact with one of the at least one rectangular contact structure. The region of the semiconductor wafer of claim 22, wherein at least two of the gate conductive structures in the region respectively form a gate electrode of a transistor of the first transistor type and the gate electrode is not formed Any gate electrode of any transistor of the second transistor type and being part of a first set of gate conductive structures, and wherein each gate conductive structure of the first set of gate conductive structures is comprised of the at least one rectangle Corresponding to one of the contact structures being physically and electrically contacted, and wherein at least two of the gate conductive structures in the region respectively form a gate electrode of a transistor of the second transistor type and Not forming any gate electrode of any transistor of the first transistor type and being part of a second set of gate conductive structures, and wherein each gate conductive structure of the second set of gate conductive structures is Correspondingly, at least one of the rectangular contact structures is physically and electrically contacted, wherein each of the diffusion regions forming at least one portion of the transistor in the region of the semiconductor wafer is A pair of coping planes oriented parallel to the gate bisector plane have a substantially rectangular horizontal cross section. The region of the semiconductor wafer of claim 1, wherein a top surface of the first gate conductive structure, a top surface of the second gate conductive structure, and a top surface of the third gate conductive structure The above is in physical and electrical contact with one of the at least one rectangular contact structure. The region of the semiconductor wafer of claim 24, wherein the at least one rectangular contact structure comprises a first rectangular contact structure in physical and electrical contact with the first gate conductive structure, and wherein the at least one rectangular contact The structure includes a second rectangular contact structure physically and electrically contacting the third gate conductive structure, the first gate conductive structure being electrically connected to the third gate conductive structure via a second electrical connection, The second electrical connection includes the first rectangular contact structure and the second rectangular contact structure, and the second electrical connection includes at least one interconnect conductive structure formed on the top surface of the gate conductive structures by at least Within one or more interconnect layers separated by a dielectric material, the interconnected conductive structures of the second electrical interconnect are each paired in a pair oriented parallel to the gate bisector plane The sub-plane has a substantially rectangular horizontal cross section. The region of the semiconductor wafer of claim 25, wherein the interconnect layer in which the at least twenty-fifth interconnect conductive structure track is formed is a first interconnect layer, wherein The first interconnect layer is an interconnect layer layer closest to the top surface of the gate conductive structures, and the semiconductor wafer region includes a second interconnect layer layer, the second interconnect layer layer Include at least twenty-two interconnected conductive structure tracks, the at least twenty-two interconnected conductive structure tracks in the second interconnect layer layer being oriented along the first reference direction Extending a plurality of straight lines, the at least twenty-two interconnected conductive structure tracks in the second interconnect layer layer each comprising at least one interconnect line conductive structure, wherein in the second Any two interconnected conductive structures adjacent to each other on the same interconnect conductive structure track among the interconnect layers are separated from each other by a distance measured in the first reference direction, The at least twenty-five of the second interconnect layer The wired conductive structure tracks are each separated from an adjacent interconnect conductive structure track by a distance of less than 193 nm measured in the second reference direction, the second interconnect being separated Each of the at least twenty-fifth interconnecting conductive track of the interconnecting layer has a substantially rectangular horizontal cross section in a pair of coping planes oriented parallel to the gate bisector plane The substantially rectangular horizontal cross section of each of the at least twenty-fifth interconnecting wire conductive structure tracks in the second interconnect layer is measured in the first reference direction a respective length and a respective width measured in the second reference direction, each of the at least twenty-fifth interconnected conductive track in the second interconnect layer The wired conductive structure has a longitudinal center line extending through a midpoint of its width in the first reference direction, and the at least twenty-five interconnected conductive track in the second interconnect layer In the longitudinal direction of each interconnected conductive structure a line on the line along which the interconnect line conductive structure track of the interconnect conductive structure extends, the at least twenty-fifth interconnect line conductive track in the second interconnect layer The longitudinal centerline of the interconnect conductive structure is configured according to the first pitch measured in the second reference direction, the second interconnect layer being bonded to the first via at least one dielectric material An interconnect layer is spaced apart, the second interconnect layer being tied above the first interconnect layer, the second interconnect layer being closest to the first interconnect layer Another layer of interconnects. The region of the semiconductor wafer of claim 26, wherein any interconnecting conductive structure forming part of the first electrical interconnect is located in the first interconnect layer or the second interconnect layer And wherein any interconnect conductive structure in which a portion of the second electrical interconnect is formed is within either the first interconnect layer layer or the second interconnect layer layer. The region of the semiconductor wafer of claim 27, wherein at least one of the at least seven gate conductive structures disposed according to the first pitch is composed of the at least one rectangular contact structure Physical and electrical contact. The area of the semiconductor wafer of claim 28, wherein at least six of the at least six gate conductive structures disposed according to the first pitch are each of the at least one rectangular contact structure Physical and electrical contact. A method of fabricating a region of a semiconductor wafer, comprising: forming at least twenty-five gate conductive structure tracks, wherein each gate conductive structure track extends along a respective straight line oriented in a first reference direction, wherein Each of the gate conductive structure tracks includes at least one gate conductive structure, wherein any two gate conductive structures adjacent to each other on the same gate conductive structure track are less than 193 nanometers measured in the first reference direction The distances of the meters are separated from each other, wherein each of the gate conductive structure tracks is separated from an adjacent gate conductive structure track by a distance of less than 193 nm measured in a second reference direction. The second reference direction is oriented perpendicular to the first reference direction, wherein each gate conductive structure in the region is in a corresponding gate opposite to the first reference direction and the second reference direction a substantially rectangular cross section in the plane, the substantially rectangular cross section of a given gate conductive structure in the region being measured by the first reference direction The respective lengths and a respective width measured in the second reference direction are defined, and the width of each of the gate conductive structures in the region is less than or substantially equal to 45 nm, wherein each gate conductive structure has a longitudinal centerline extending in the first reference direction, the longitudinal centerline of a given gate conductive structure extending through a midpoint of a width of the given gate conductive structure, the longitudinal center of each gate conductive structure The line is located on a line along which the gate conductive structure track of the gate conductive structure extends, wherein some of the gate conductive structures are disposed in the same region as the diffusion region to form at least one transistor gate Forming at least one electrically conductive contact structure in physical contact with one or more of the gate conductive structures forming at least one of the transistor gate electrodes in the region to form at least one transistor gate in the region Each gate conductive structure of the electrode has a respective top surface in physical contact with the at least one conductive contact structure, wherein each conductive contact junction in the region Generating a structure formed as a barrier structure independent of any physical contact thereof, wherein the at least one electrically conductive contact structure comprises at least one rectangular contact structure that is oriented parallel to the gate a pair of coping planes having a substantially rectangular horizontal cross section in a pair of coping planes, the substantially rectangular horizontal cross section of each of the at least one rectangular contact structures being greater than the measured in the second reference direction Defining a respective length of the width of the gate conductive structure physically contacting the rectangular contact structure, and wherein the at least one rectangular contact structure is each on the gate conductive structure to which the physical contact is physically The second reference direction is substantially centered; forming at least twenty-two interconnected conductive structure tracks in a first interconnect layer, wherein the at least twenty-five interconnect conductive traces each Extending along a respective straight line oriented in the second reference direction, wherein the at least twenty-five interconnected conductive structure tracks each comprise at least one a conductive structure in which any two interconnected conductive structures adjacent to each other on the same interconnect conductive structure track are separated from each other by a distance of less than 193 nm measured in the second reference direction Open, wherein the at least twenty-two interconnected conductive structure tracks are each separated from an adjacent interconnect conductive structure track by a distance of less than 193 nm measured in the first reference direction Separating, wherein each of the interconnecting wire conductive structures of the at least twenty-five interconnecting conductive track has a substantially rectangular cross section in a pair of coping planes oriented parallel to the gate bisector plane, The substantially rectangular cross-section of a given interconnect conductive structure within the region is defined by a respective length measured in the second reference direction and a respective width measured in the first reference direction, wherein Each of the interconnecting wire conductive structures of the at least twenty-five interconnecting conductive track has a longitudinal centerline extending in the second reference direction, the longitudinal centerline of a given interconnecting conductive structure Extending through a midpoint of a width of the given interconnect conductive structure measured in the first reference direction, the longitudinal centerline of each interconnect conductive structure is located at an interconnect conductive structure of the interconnect conductive structure a line along which the track extends; and a portion of the gate conductive structure forming at least one dielectric material on the twenty-five gate conductive structure tracks and the at least the first interconnect layer Twenty-five interconnecting portions of the interconnecting conductive structures of the interconnecting conductive tracks, wherein the at least one electrically conductive contact structure is each formed to extend through the at least one dielectric material and is formed to a portion of the twenty-five gate conductive structure tracks including at least seven gate conductive structures disposed according to a first pitch, facing a portion extending perpendicularly from a top surface of the gate conductive structure of the physical contact The first spacing is measured between the longitudinal centerlines of the gate conductive structures in the second reference direction, and the at least seven gate conductive structures comprise a first gate conductive structure, the first gate The electrically conductive structure includes a portion of a gate electrode forming a first transistor of a first transistor type, wherein the first transistor type has any electro-crystalline system formed by the gate electrode formed by the first gate conductive structure The at least seven gate conductive structures comprise a second gate conductive structure, the second gate conductive structure comprising a first portion of a gate electrode forming a second transistor of the first transistor type, The second gate conductive structure includes a second portion of a gate electrode forming a first transistor of a second transistor type, wherein the first and the second are measured in the second reference direction The distance between the longitudinal centerlines of the two gate conductive structures is substantially equal to the first pitch, the at least seven gate conductive structures comprise a third gate conductive structure, and the third gate conductive structure comprises forming the second a portion of a gate electrode of a second transistor of the type of transistor, wherein any of the electromorphic systems of the gate electrode formed by the third gate conductive structure is of the second transistor type, The distance between the longitudinal centerlines of the first and third gate conductive structures measured in the second reference direction is substantially equal to an integer multiple of the first pitch, the at least seven gate conductive structures comprising a fourth gate conductive structure, the fourth gate conductive structure comprising a first portion of a gate electrode forming a third transistor of the first transistor type, the fourth gate conductive structure comprising forming the first a second portion of a gate electrode of the third transistor of the second transistor type, the first transistor of the first transistor type includes a first diffusion region, and the second transistor type The second transistor includes a first diffusion region, and the first diffusion region of the first transistor of the first transistor type is electrically connected to the second of the second transistor type via a first electrical connection The first diffusion region of the transistor, the first diffusion region of the first transistor of the first transistor type is also used as a gate electrode formed by one of the at least seven gate conductive structures The first transistor a diffusion region of another transistor of the type, the first diffusion region of the second transistor of the second transistor type also serving as a gate electrode having one of the at least seven gate conductive structures a diffusion region of another transistor of the second transistor type, wherein each of the first transistor types having a gate electrode formed by any of the at least seven gate conductive structures The system is included in a set of transistors of the first transistor type, and wherein each of the second transistor types having a gate electrode formed by any one of the at least seven gate conductive structures The system is included in a set of transistors of the second transistor type, wherein the set of transistors of the first transistor type and the set of transistors of the second transistor type are provided by an internal sub-region of the region Separating, wherein the inner sub-region does not contain the source or drain of any transistor, wherein each transistor is formed by a gate electrode formed by any of the at least seven gate conductive structures a portion of one or more logic functions; forming a second interconnect layer layer, the second interconnect layer layer comprising a plurality of interconnect line conductive structure tracks each along a respective line oriented in the first reference direction Extending, the plurality of interconnected-line conductive structure tracks in the second interconnect layer layer each comprising at least one interconnect line conductive structure, wherein the same interconnect level among the second interconnect line layers Any two interconnecting wire conductive structures adjacent to each other on the interconnecting conductive track are separated from each other by a distance measured in the first reference direction, among the second interconnect layers The plurality of interconnected conductive structure tracks are each separated from an adjacent interconnect conductive track by a distance of less than 193 nm measured in the second reference direction, wherein Each of the plurality of interconnection line conductive structure tracks of the second interconnect layer has a substantially rectangular level in a pair of coping planes oriented parallel to the gate bisector plane Cross section, at the second interconnect The substantially rectangular horizontal cross-section of the interconnected conductive structures in the layers is defined by a respective length measured in the first reference direction and a respective width measured in the second reference direction Each interconnect line conductive structure in the second interconnect layer layer has a longitudinal center line extending through a midpoint of its width in the first reference direction, at the second interconnect layer The longitudinal centerline of each interconnect conductive structure is located on the line along which the interconnect conductive structure track of the interconnect conductive structure extends, the second interconnect layer being Separating at least one dielectric material from a top surface of the gate conductive structures, the second interconnect layer layer being separated from the first interconnect layer by at least one dielectric material Open, wherein the first interconnect layer is one of a group of four consecutively configured interconnect layers, and the four consecutively configured interconnect layers of the set are tied to the gate a top surface of the conductive structure and closest to the top surface of the gate conductive structures And wherein the second interconnect layer is layered over the top surface of the gate conductive structures and the four consecutively configured interconnect layers of the set closest to the top surface of the gate conductive structures And the other one of the top surface of the first gate conductive structure and the top surface of the second gate conductive structure and the top surface of the third gate conductive structure are associated with the at least one One of the rectangular contact structures is physically and electrically in contact, wherein at least two of the gate conductive structures in the region respectively form a gate electrode of a transistor of the first transistor type and are not formed Any gate electrode of any transistor of the second transistor type and being part of a first set of gate conductive structures, and wherein each gate conductive structure of the first set of gate conductive structures is comprised of the at least one Corresponding one of the rectangular contact structures is physically and electrically contacted, and wherein at least two of the gate conductive structures in the region respectively form a gate electrode of a transistor of the second transistor type And not forming any gate electrode of any transistor of the first transistor type and being part of a second set of gate conductive structures, and wherein each gate conductive structure of the second set of gate conductive structures is The at least one rectangular contact structure is in physical and electrical contact with one of the corresponding ones, wherein each of the diffusion regions forming at least one portion of the transistor in the region of the semiconductor wafer is oriented parallel to the gate bisector plane The pair of coping planes have a substantially rectangular horizontal cross section.