TW201214670A - Dynamic array architecture - Google Patents

Abstract

A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a dynamic array structure with a variable resolution. 13 shirts [prior art] With regard to higher performance and smaller grain size, the semi-conducting year is forced to reduce the area of the circuit by about 50%, reducing the "area for the movement to the surgery provides economic benefits. Reduce the 5G% The wafer area is achieved by reducing the size to between 25% and 30%, and can reduce the feature size and white manufacturing equipment and materials. For example, the improved photolithography process can be achieved. = Good chemical mechanical grinding - . In the development of lithography - when the minimum feature size is close to the wavelength of the light source that the feature is exposed to, the non-pre-action between adjacent features occurs. Today's minimum feature size It is close to 45nm (nano), and in the light lithography = = m green is still used to turn to 193ηιη. The wavelength of the light source used in the minimum characteristic 光 光 光 镰 镰 镰 镰 镰^距。^ When the optical lithography gap increases, the resolution capability of the photolithography process will decrease. When each shape on the Tiandang mask interacts with light, an interference pattern is generated; interference patterns from adjacent shapes can be generated. Constructive or destructive interference. In the case of the case, an unnecessary shape may be inadvertently produced; in the case of 'theft may be inadvertently moving the shape of the slit. In any case, the intended one prints a special shape in a different manner, which may cause malfunction of the device. ^ Positive methods such as optical near-track positive method (OTC) attempt to predict and modify the mask by _ miscellaneous, so that the printed shape can be made according to the requirements. With the geometrical contraction of the process, the interaction is miscellaneous. In view of the above, when technology continues to move toward smaller semiconductor device features, we need a solution to deal with the lithography gap issue 201214670. [Invention] A semiconductor device is disclosed in an embodiment. The device includes a substrate and a diffusion region defined by the substrate (4), the diffusion region is separated from the movable substrate and separated from each other. The device also includes some line-cutting lanes, which are along a single-common direction And extending over the substrate, each track is defined by - or a plurality of linear gate segments. Each of the linear interpole tracks extending over the region is defined to minimize the ^= The ends of adjacent linear gate segments are separated by a distance, and are electrically insulated; in addition, the linear gate segments are sizable to have variable lengths to impart a logic gate function. In another embodiment Disclosed is a semiconductor device comprising: a diffusion region positioned in the substrate to define a transistor device for use; the second body device also includes - some are positioned above the substrate in a common direction. 'Several line-off segments are disposed above the diffusion region, and each-line paste segment above the κ-scatter region is defined as being defined in the active portion and defined above the substrate except for the diffusion region 'Defining a linear gate segment to have a variable length. The semiconductor device further includes a plurality of linear conductor segments disposed in the south of the line and above, so that a real slice can be used. The common direction intersects the adjacent linear conductor segments in the common line of the L-line _. The other is a thin gate. The gate contact includes a λ ί Η The linear guide defined by the cross-sectional shape of the upper average sentence positions the linear conductive segment such that its length extends in a direction substantially perpendicular to the gate of the lower layer of the conductive segment, and the linear guide segment is larger than the lower layer The width of the poles causes the linear conductivity to be disclosed in another embodiment - a contact layout comprising a number of contacts defined by 201214670 over a common grid mapped across the substrate. The contact layout also includes a number of sub-resolution contacts that are defined on the common grid to surround each contact. Each & resolution point is defined to avoid rendering in the lithography process while enhancing the resolution of the contacts. Other aspects and advantages of the invention will be apparent from the description and appended claims appended claims [Embodiment] A number of specific details are set forth in the following description in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without all or a particular portion of these particular details. In other instances, the invention has been unnecessarily obscured and the well-known process operations have not been described in detail. In general, we set up a dynamic array structure to cope with the ever-increasing micro-information. In the field of semiconductor manufacturing, it is the gap between the minimum size of the iteration and the level of the component used in the lithography process, wherein the feature size is smaller than the light=lithography process using a fine wavelength of light; However, the current feature size is as small as nm' and is expected to approach as small as 45nm in the near future. 3 times the wavelength of the light of the fresh ^ ^ ί" test = exposure about = part size is (10), _ 9〇mn size The characteristic part, about the number of 丄ϋ , 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The sentiment is increased by 201214670 ΐ i! , that is, in the specific mask, the designer may have determined. The second metamorphosis is usually unpredictable and the interaction occurs _, with the special = = complex and variable / 1 ,·#################################################################################################### Smaller 'light interactions are more complex and unpredictable. 'If the designer follows the established There is a specific probability associated with the design rule group kL fruit production 1 3 out will be in the design of the anti-design rule group, successful manufacturing sister = two otherwise, it is against the successful product manufacturing aspect, to illustrate the proximity of two-dimensional ^ 1 The interaction will greatly expand the design rule group and the possible combination of the department. The design of the ship is quick and easy to make mistakes. For example, the design rule group of the expansion needs her _ test interest and the application of the second place; In addition, even if all the design ^, biliary. In the creation of arbitrarily shaped two-dimensional features, the light interaction of the dust can not be carried out; in addition, can also be. Unconditional between the two-dimensional variation features The s Park's predecessor Wei Cai contains a large number of Weng (cafe _; axis Γ: ί2ΐί ΐ ΐ 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含The deuteration may include CMP dishing effect, photolithography, inter-polar distortion, oxygen 201214670 compound thickness variability, implant variability, and other manufacturing-related phenomena resulting in layout distortion. Dynamic The column structure is defined to account for the variability of the semiconductor fabrication process described above. - Figure 1 shows a number of layout features and light intensity for generating a mother layout feature, in particular three adjacent lines, in accordance with an embodiment of the present invention. The layout features (ΙΟΙΑ-lOic) are disposed in a specific mask layer in a substantially parallel relationship. The distribution of light intensity from the shape of a layout feature is represented by a sinc function, shc function (103A-103C) Representing the distribution of light intensities from each of the layout features (==1010, respectively, and the positions of the peaks of the adjacent linear layout features (1〇1Α_1〇ι function (ig3a-ig3c) are separated), thus, The illustrated cloth-like light can be enhanced at the peak of the constructive two function °3A_1G3C) between the light energy associated with the phase spring = layout feature portion (1〇1A_1〇lc). With the foregoing - in the figure ^ H jin ^ when we have a regular repeating pattern and an appropriate spacing to define the exposure of a layout feature. Provided by fine-grained light interference, "specially reduce or even eliminate the use of sufficient real estate ^ first learning proximity correction (opc) and / or priming mask enhancement technology associated with the two degrees to make j-layout characteristics Too many considerations must be predicted that the sine function peak will occur in the same direction as the opposite side of the board == then the sine function peak can be achieved J Ji:, W〇lA_101C), top test The 5th aspect overlap and the corresponding layout feature 201214670 shape enhancement. In this way, the resonant light energy from the shape of the adjacent layout feature can be used to enhance the exposure of the special layout feature shape. " , 2 shows according to An embodiment of the present invention is used to define a dynamic array structure. It should be understood that we do not intend to fully represent CM〇S as shown in Figure 2 for defining a generalized stack of dynamic array structures. Manufacturing Process; however, we will build dynamic arrays based on standard CMOS fabrication procedures. In general, dynamic array structures include the definition of the underlying structure of the dynamic array and the assembly technique of the dynamic array to optimize the use of the region. Therefore, we design a dynamic array to optimize the semiconductor manufacturing capability. ^About the definition of the underlying structure of the dynamic array, the dynamic array is placed on the base substrate 201 in a layered manner, for example, in Shi Xi The substrate or the insulating layer is overlaid on the substrate (s〇I). The diffusion region 203 is defined on the base substrate 201, and the diffusion region 203 represents the selected region of the base substrate 201 for the purpose of adjusting the electrical properties of the base substrate 2〇1. The impurity is introduced into the selected region. The diffusion contact 2〇5 is defined above the diffusion region 203 to connect the diffusion region 203 with the conductor line, for example, the diffusion junction 205 is defined to connect the source and the non-polar diffusion region 203 with each other. a conductor mesh; again, a gate feature 2〇7 is defined over the diffusion region 203 to form a transistor gate. The gate contact 2〇9 is defined to connect the interpole feature 207 with the conductor line 'eg, define a gate junction Point 209 is connected to the transistor gate and its individual conductor mesh. The interconnect layer is defined above the diffusion contact 205 layer and the gate contact layer 209. The wiring layer comprises a first metal (metal 1) layer 211, a through hole (through hole 1) layer 213, a second metal (metal 2) layer 215, a second via (via 2) layer 217, a third metal (metal 3) layer 219, a third via (via 3) layer 22, and a fourth metal (metal 4) Layer 223, metal and via layers can electrically connect various diffusion contacts 2〇5 and gate contacts 209' to enable the logic function of the circuit. It should be understood that the dynamic array structure is not limited to a specific number of interconnects Layers (ie, metal and via layers), in one embodiment, the dynamic array may include additional interconnect layers 225 in addition to the fourth metal (metal 4) layer 223; or 'in another embodiment' The dynamic array may comprise less than four metal layers.Defining the dynamic array 'describes the film layer (other than the diffusion region layer 203) in relation to the shape of the layout feature in which Z-8201214670 is defined. In the layers other than the + layer 203, only the linear cloth is allowed. "The linear layout feature except the diffusion region is characterized by having a structure in a specific film layer. The diffusion region 203 does not need to be a dimensional change dimension. The top surface of the changing substrate - any of the planes that are related to the number of diffusion curved topologies, the shape of your sister in a consistent application, limited conductive material (such as polycrystalline eve) Transistor gate

Force:, the line in a specific film layer: J phase thousand order, so 'in a specific film sound into each other above and with the base; ί ^ ^ ^ 2 〇 7 ^ 223 involved in the film process The exposure of the light wave's constructive dry sound hr to the adjacent shape. Therefore, the Department will make a specific Zhao Yu Wang especially ten steps, so that the lithography correction (such as op and political migration and more than the conventional accompaniment based on orc bribe, this):: This, the phase of the light station How the waves will interact, because the light interaction between the relevant departments of the j-department can identify the redundancy = then, the interval between the adjacent lines defines the lining and distance, and - 'day in the middle The center-to-heart separation between the linear features of the feature;;1 is adjacent to the adjacent layer of 201214670 in a special film layer; the linear light enhancement will be in-special and destructive to her t, two The light of each of the features ===== will be enhanced by the specific temple ===length j is determined by the internal strictness, and the dynamic array contains the restricted topology, which is arranged in parallel It is essentially achieved that the layout map is to be mapped to the dynamic array to show the basic grid according to an embodiment of the present invention. The basic grid can be used to assist, and the 2 temples are appropriately The optimized pitch is arranged in parallel in each layer of the dynamic array. The sub-array does not define the basic mesh as part of __, but it can be Mapping on each layer; in addition, it should be understood that the basic grid is mapped in a real red-language manner on the layers of the dynamic_, thus assisting in the precise feature stacking and arrangement. The basic grid is defined as a rectangular grid (ie, a right-angled basic grid) according to the first reference direction (χ) and the second reference direction (^). According to the definition, the first and second are defined. The spacing between the grid points and the grid points in the reference direction so as to define a line-shaped feature having the interval from the best feature to the feature; in addition, the grid spacing in the first direction (X) may be in the second The direction (y) is different. In a practical example, a single basic mesh is mapped throughout the die so that various linear features in each die can be placed throughout the die; however, In other embodiments, individual basic grids may be mapped throughout separate regions of the die to support the non-distance requirements between features within the 201214670 domain. Figure 3β shows the root map to be mapped to the entire die. Separate basis for independent areas Function (also known as sine function and manufacturing performance) and praised 'The manufacturing performance is stored in the manufacturing dynamic array's design. The interaction function is defined as the r end position and its layer= The substantially rectangular cross-section defined by 307 = ^ degrees ^ to - length. In the embodiment, the line == 〇〇 == extension two and high r. 7 defined by the rounding along its length An example of the linear feature on the dynamic array of the second a temple sign is 2 and is positioned such that its length 305 is along the first reference direction with respect to the first and second reference directions. (8) and the test direction (y) or the feature portion extends about the first and second reference directions ^2 J. Regardless of the linear portion is substantially parallel to the set moving plate s;:: the upper two should be bent = Figure 3D shows that the array is compatible with the dynamic array in accordance with an embodiment of the present invention. Line shape 317, see 315, and the trapezoidal cross section defined by Gao Qing, the line shape ^^ 201214670 line direction extends to length 311. In one embodiment, the length 311* is substantially uniform, and the cross section of γΐ7 can cause rounding of the end of the linear feature 317. The lithography effect can refer to the direction (X) and (Zhe _ _ lang _ _ on ^ the first - and second direction, should be clear: can be lined with the Ministry of 319 to determine ^ ^ Temple ^ ^ position test direction (8), second reference direction (y) or relative In the first, === first parameter = pair = direction extension. Regardless of the _ temple sign 317 is parallel to the plane of the top surface of the substrate on which the dynamic array is disposed, the linear feature portion 317 is in the - and the following: the reference direction, the curved part (that is, the direction change). (There is no such thing as a kink ΪΞ Γ 3H3D clearly discusses the understanding of a rectangular and trapezoidal cross section, and may have other cross sections. The linear feature of the type is assisted. Therefore, the linear feature of the cross-section of the fourth (four) cross-section can be used as long as the ship is compared with the in-direction and the hybrid is made to have its length along the first-reference direction (8). The second reference direction (7) or the diagonal direction of the second and second reference directions (8) and ω may be extended. The layout of the array follows the basic grid pattern. Therefore, grid points can be used to represent where the change in direction occurs during diffusion, where the gate and metal features are placed, where the contacts are located, the line gates and Where is the opening in the metal feature, etc. The spacing between the grid points (ie, the grid-to-lattice spacing) should be set for a particular feature line width (eg, width 303 in Figure 3C) to make the particular feature The exposure of adjacent linear features of the line widths will be enhanced to each other, wherein the linear features are concentrated on the grid points. In a consistent embodiment, reference is made to the dynamic array stack of Figure 2 and the exemplary network of Figure 3A, ' The grid spacing on the first reference direction (X) is set by the required gate pitch. In this same embodiment, the second reference direction is set by the metal and metal 3 pitch (y). The spacing between the grid points, for example, in the 90 nm process technique (ie, the minimum feature size is equal to 90 nm), the lattice spacing between the second reference directions (y) is about 0.24 microns. In one embodiment, 'metal 1 and Metal 2 layers will have a common spacing and between 12 20121 Different spacings and spacings can be used for the 4670 layers above the 2 layer. Different dynamic array layers are defined such that the adjacent ones extend in a manner that overlaps each other. For example, the feature lines are extended, that is, perpendicular to each other. ; material, ^ God can be about 45 degrees) to extend over the line of the adjacent layer: Example: 邛: to;! In the example, the linear feature of the layer along the first - reference j, for example, in an implementation feature The line of the -(x) and the second near layer is clear: in order to extend in the direction of the intersection, the angle of the line should be in the dynamic array, and the line of the linear feature on the film layer can be The hole can be defined as needed in the _Wei section, and the contact and the I method are completely minimized to eliminate the -if parent interaction. Specifically, in the implementation of OTC $ other S, the dynamic array allows the bending of the diffusion layer to be able to make += the curved portion above the diffusion layer; the second portion is linear (for example, Figure 3C), and Set each other flat. Cloth ^ In the embodiment, the layout features are linear and parallel. Above the metal layer _si〇nthrou fine taJ2 above the layer f, the layout feature may have 0, ^ 1 . The shape of gold, the size and the case of the surface interference interference, there is a constructive light-drying g can be above the layout of the feature part of the picture Μ ί ,, ί 图 Figure 4 to 14 to illustrate the extension of the diffusion through metal 2 Move away from the array of sounds ί4 ^14; _ _ qualitatively ambiguous any integrated circuit design. Bureau. Figure 44 is a schematic diagram of the embodiment of the dynamic array of the diffusion layer of the lower layer 1 of the 絪 t 二 二 p p diffusion region 401 and n diffusion region 403, when according to the bauxite, 'Zhou Cailai 疋 扩散 diffusion zone The diffusion region is not limited by the linear features associated with the 13 201214670 film layer above the diffusion layer. The diffusion regions 4〇1 and 403 include diffusion blocks 4〇5 defined at which diffusion contacts are to be provided, and the diffusion regions 401 and 403 do not include extraneous protrusions or corners. This improves the use of lithography resolution and Enable more accurate device removal. In addition, the n+ mask regions (412 and 416) and the p+ mask regions (410 and 414) are defined as rectangles having no extraneous projections or notches on the (8), (y) grid. Large diffusion regions, no need for 〇]PC/RET, and the ability to use lower resolution and less cost lithography systems, such as i_line illumination at 365 nm. It should be understood that the mask area 416 and the p+ mask area 410 as shown in FIG. 4 are used for the embodiment of the well-biasing, and in another embodiment using sufficient bias, FIG. The 2n+ mask region 416 shown in the figure will actually be defined as a p+ mask region. Moreover, in this alternative embodiment, the P+ mask region 410 shown in Figure 4 will actually be defined as an n+ mask region. Figure 5 shows a gate layer and a diffusion contact layer, which are above and adjacent to the diffusion layer of Figure 4, in accordance with an embodiment of the present invention. If the familiarity of the human pole feature 5G1 defines the transistor gate, and we traverse the gate of the dynamic array along the second reference direction (y) in the second reference direction (y), the gate feature 501 is defined. In the case of the other embodiment, for example, FIG. 5 shows a gate feature 501 宽 with respect to the other interpole features 5 〇 1 . The distance between the gate features 501 is minimized (the center is minimized, while ensuring that the closed pole features 5 〇 1 provided by the adjacent interpole features 501 are better than the linear extension over the dynamic gate The feature portion 501 passes through the diffusion region 4〇3 and the 4〇1 channel and the channel transistor. The optimal gate feature 5〇=, the edge feature is formed at the position of the η grid. The mother-net, the pole feature 5〇1 is easy to be in the gate feature=^^^^(sh)sh---, and when the thin part 14 201214670 501 is removed, the gate printing is obviously improved. On behalf of the f-special ship, the number of gates and the number of two gates are interrupted (that is, the Ding is broken) any time. The separation of the gate track piece is minimized to a process that may consider manufacturing effects and electrical effects. In the case of -, when the features in a particular layer are just after the common end to the end spacing, The best manufacturability is achieved. The minimization of the spacing between the ends of the gate track segments maximizes the provided lithography enhancement and uniformity. In addition, in the other side: the low eve will need to be interrupted 'that is, to make the individual break point break mode to __ polar track' to try to avoid the neighboring points in the vicinity of the adjacent 'defective ten break points are set to Making the cup, the cloth too; the break point, wherein the line of sight is considered to extend perpendicular to the direction in which the gate track extends above the substrate. In addition, in one embodiment, the ΐ 子 (also known as pmqs or touch s The boundary at the top or bottom of the grid 'This example will enable the neighboring cells to bridge. (4) The diffusion joint 503 is defined at each square block punch, - the printing of the scattered 2 strong diffusion joints. Diffusion block 405 Exist in each line?:== nearby to enhance the power and ground connection at the diffusion contact 503 and ^^501 and the diffusion contact 5〇3 share a common grid spacing; more grid ^ f The arrangement of 5〇1 is offset by 1/2 相对 with respect to the diffusion contact 5〇3, and the grid pitch of the interpole feature portion 501 and the diffusion contact 503 is several times r, so that the center coordinate of the center falls on 〇.36清的〇〇&々敫;々敫♦ Secret feature 501 center X coordinate minus 〇.18μιη should In the present embodiment, the χ coordinate system is represented by the following formula: ::: Χ coordinate of the center = Ρ〇.36μΐη, where 1 is the number of grids; χ coordinates of the center of the number of gate features = 〇18μπι + Ρα36μιη, where χ is the grid 15 201214670 〇3em, on the water; again, the vertical grid of the 90· technique is about ^ 崎 俾 can connect the closed-pole feature 5〇1 = pole g; ==== , the white space is minimized in the center of the grid; in addition, the two gate contacts 601 are super-large in the direction perpendicular to the gate feature 501: to ensure the gate contact Between the 601 and the gate feature, there is a method known in the figure, such as the polycrystalline temple. In the case of the closed-cell 707, when the distance 705 & === is introduced in the gate, the distortion of the gate line is particularly problematic. Further, the length of the H body is opposite to that of FIG. 7; according to the present invention, a solid Ϊ crystal point _ is made ^^ S $ ' and is perpendicular to the gate characteristic 5 〇 1 $ = 03 the same. For example, if the diffusion joint is 5. 3 and the vertical dimension of the _ 6G1 is made to the melon. ί 八 中' can make the gate contact 6〇1 I be made such that the vertical dimension 703 & 16 601 201214670 is different from the vertical dimension for the diffusion joint 503. In one embodiment, the contact of the gate contact 6〇1 at the gate gate contact 6G1 with the interpole feature 501 is where the maximum surface area is connected by the gate feature 501 FIG. A metal layer of one embodiment of the invention is connected over and adjacent to the gate of the gate. Metal i layer = = 2 义 成 可 can be included in the parallel boat to stretch over the ‘ 歹丄 歹丄 特 特 淖. In the lower gate layer of Fig. 5, the metal gate 8〇1_821 extends perpendicularly to the gate feature 501, so that in this example, the tracks 801-821 extend linearly along the first reference direction (χ) Over the dynamic array, the I-to-one track 80=21 spacing (center-to-center spacing) is minimized while ensuring the optimization of lithography enhancement provided by adjacent metal 1 rails 801-821 (ie, a total of The embodiment towel, the metal 1 obedient 8G1·821 towel on the vertical grid of about 0·24μιη for 90 Cong private technology. To provide the required electrical connection for the special logic function to be performed, each A metalworker 8〇1_821 can be interrupted in a straight line across the dynamic array, that is, any number of times. When it is necessary to interrupt a particular metal [track 8〇1_821, make the gold in the middle, the end of the 1 track segment The interval between them is minimized to the extent that it is possible to consider the effect of manufacturing and electricity. It will be between the ends of the metal 2 orbital segments at the point of interest, and the minimization can make the (four) near-metal shackles Shadow enhancement and its uniformity. In addition, in an embodiment, if adjacent metal The orbital track needs to be broken, that is, the adjacent metal points are interrupted in such a way that the individual interruption points are more than one another, so as to avoid the occurrence of neighboring points as much as possible. More specifically, the breaking point in the adjacent metal i is They are respectively arranged such that the line of sight does not exist at all break points, wherein the line is extended as if the read metal 1 track is perpendicular to the direction in which the substrate extends. 17 201214670 In the embodiment of FIG. 8A, the metal 1 is connected to the 801 system. To the ground supply, and the metal 1 is connected to the power supply voltage. In the embodiment of FIG. 8A, the widths of the metal 1 tracks 801 and 821 are the same as the other metal 1 tracks 803-819; however, in another In the embodiment, the width of the metal 1 lanes 801 and 821 is greater than the width of the other metal 1 lanes 803-819. Figure 8B shows the metal 1 layer of Figure 8A, the metal 1 grounding and power rails (801A and 821A) relative to the other The metal 1 track 803-819 has a larger track width. The metal 1 track pattern is optimally used to optimize the use of "white space" (the space not occupied by the transistor). Example of Figure 8A Contains two shared metal 1 power Commanding 801, 821 and nine metal 1 signals 803_819. Metal 1 is 8 〇 3, 8 〇 9, 811 and 819 are defined as gate contact tracks to minimize white space; define metal 1 track 813, 815 and 817 are connected to the p-channel source and drain; in addition, if no connection is required, any of the nine metal .1 signal tracks 803-8〇9 can be used as the feedthrough, for example, metal 1 Lanes 813 and 815 are used as feedthrough connections. Figure 9 shows a via 1 layer, which is defined above and adjacent to the metal 1 layer of Figure 8A, in accordance with an embodiment of the present invention. In the via 1 layer, the metal 1 tracks 801-821 are connected to the higher height wires. The θ diagram shows a metal 2 layer according to an embodiment of the present invention, which is defined in Figure 9 and is in harmony with it. The metal 2 layer contains a number of metals that are similar to the horizontal direction Ut across the moving tree line. The metal is obedient == upper vertical, and the lower metal layer of Fig. 8A is 1 敕 敕, first sni, direction and shellfish It is parallel to the lower part of the gate layer in Figure 5 and is extended in the t- moxibustion. Thus, in the present embodiment, the metal 2 extends straight across the dynamic array in the direction (y). Guaranteed by = 1] 2 lanes 2 = spacing heart to center interval) most like). Ku Mingmu. The lithography enhancement of the jinji can be optimized (that is, the resonance is the same as the one in the first layer, = 5〇1 spacing and metal 又 又 = fn^. In the example, the gate feature has the same k-distance. In another embodiment, the contact gate spacing 201214670 diffusion junction polycrystalline light polycrystalline egg compartment is larger than the metal 2 orbital embodiment, the metal 2 is obsessed The pitch is arbitrarily set to the contact gate ί ί or 3/4, and thus, in this embodiment, the gate trajectory and the 母 丨 极 轨道 轨道 轨道 及 及 及 及 及 及 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 For example, 最佳 the optimal contact gate distance is g.36 pottery, the best gold road, the distance is 〇.24pm. In another embodiment, the gate track and the metal 2 track pitch are aligned with every four metal 2 pitches. For example, at 90 触 _ 执 Α 3% 3% 3% " 'Best Metal 2 trajectory, providing the required logic for the special logic function to be performed The spacing between the gold and the ends is minimized to the point where it is possible to consider the manufacturing effect and the electrical enthalpy. The spacing between the ends of the metal 2 orbital segments at the point of interruption is greater than that provided by the adjacent metal 2 orbitals. The lithography enhancement and its uniformity are most such that in the embodiment, if the adjacent metal 2 is required to be interrupted, the breakpoints are offset from each other to interrupt the adjacent metal 2 to perform. More specifically, the adjacent metal 2 tracks are considered to be absent from all break points, where the line of sight is like! The road, +, and the way of extending in a direction extending above the substrate extend perpendicularly. Above the reference direction gate 1 - the wire in the specific metal layer can be parallel to the dynamic array in the direction that the new 撼 苓 苓 苓 苓 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Above the layer - the specific directional kinetic energy of the mid-line direction of the specific metal layer - the reference direction (8) and the first diagonal 12 of the second reference direction (y) 12 show that the conductor track is transversely traversed according to the present invention -; Applying 1 and metal 2 to the second diagonal direction of the second reference directions (x) and (7) to provide the required electrical connection for the bait force, and the diagonal lines of FIGS. 11 and 12 19 201214670 The conductors 1101 and · can be interrupted by being interrupted in a straight line across the dynamic array. When necessary, the conductors across the diagonal are also minimized to minimize the spacing between the ends of the diagonal conductors at the point of interruption to the extent that manufacturing effects and electrical effects can be considered. Minimizing the separation between the ends of the diagonal line at the break point allows the (4) near-pair conductor track to be lithographically enhanced and uniform. w /, . The optimal layout density in the array of grievances is achieved by implementing the following design rules. · Setting at least two metal 1 tracks across the n-channel device area; Setting at least two metal 1 tracks across the channel device area; The n-channel device is provided with at least two gates; at least two gates are disposed for the n-channel device. From the point of view of lithography, the contacts and through holes become the most difficult to cover and the through holes are shrinking, closer, and more disorderly. The spacing and density of the vias make it difficult to reliably print out the shape. The shape may be printed incorrectly due to destructive interference from adjacent shapes or alone. If the cut marks are printed correctly, the manufacturing yield of the relevant joints is extremely high. You can set the secondary resolution contact (4) to the real contact ^ light 'as long as the secondary resolution contact does not disintegrate; χ, the secondary resolution contact can be any shape, as long as it is smaller than the resolution capability of the lithography process. ’, =3Α shows the implementation of the layout of the secondary resolution joint according to the (4)-embodiment of the embodiment, and the layout is entangled by the township mode. The resolution contact 1301 seems to be in the resolution of the secret and will form a 'subsidiary contact'. 3, 6 () 1) light energy. In the implementation of ^ ίΪίίΪί Ζ set on the grid, so that the gate contact 6〇1 and the diffusion contact 5Q3 are both lithographically enhanced, for example, the secondary resolution contact 13〇1 =5〇3= On the grid of one-and-a-half of the pitch, it has a positive effect on both the gate contact tear and the expansion & point 503. In one embodiment, the 201214670 vertical spacing of the sub-resolution contacts ^(1) follows the vertical spacing of the gate contacts 601 and the diffusion contacts 503. The grid position 丨3〇3 in Fig. 13A indicates the position between adjacent gate contacts 6〇丨. Depending on the lithography parameters in the manufacturing process, the secondary resolution contact 1301 at this grid location will likely establish an undesired bridge between two adjacent gate contacts 6〇1. = The bridge resolution 13〇1 at position 1303 can be omitted if a bridge is possible. Although FIG. 13A is an embodiment showing that the sub-resolution contact 13 〇 1 is disposed adjacent to the real feature to be analyzed, it should be understood that another embodiment may set the sub-resolution contact to each available. The grid position is to fill the grid. Figure 13B shows the sub-resolution joint layout of Figure 13A, which defines the sub-resolution joints as being fillable to the extent possible, in accordance with an embodiment of the invention. It should be understood that although the embodiment of Figure 13B The sub-resolution joint fills the grid as much as possible, and still avoids setting the sub-resolution joint to a position where it is highly likely to bridge between adjacent full-resolution features. . . ^ Figure HC shows according to the invention An embodiment of the sub-resolution contact layout of an embodiment utilizes sub-resolution contacts of various shapes. Additional resolution contact shapes may be utilized, as long as the resolution of the sub-resolution contacts in the manufacturing process is The following can be done. Figure 13C shows the use of the "X-shaped sub-resolution contact 1305" that concentrates the light energy on the corners of adjacent contacts. In one embodiment, the Γχ-shaped 次 ^ contact is used. The end of 1305 extends to more enhance the deposition of light energy at the corners of adjacent contacts.

Figure 13D shows an exemplary completion diagram of a phase shift mask (APSM) with sub-resolution contacts, in accordance with an embodiment of the present invention. As shown in FIG. 13A, the lithography is used to enhance the diffusion joint 503 and the gate contact 6〇1 by using the sub-resolution, and the APSM is used to improve the resolution modification when the adjacent shape produces a destructive interference pattern. The mask causes the phase of the light traveling through the mask on the adjacent shape to be 丨 (10) degrees inverted, the function of this phase shifting to remove destructive interference and to allow for a larger 1 degree of contact. For example, the contact marked with a positive sign "+" in Fig. 13D represents the contact exposed by the light wave of the first phase, and the contact marked with the minus sign "·" represents a phase shift of 180 with respect to the first phase. The light wave of the degree is exposed to the contact. It should be clear that we use APSM

21 201214670 Technology to ensure that adjacent contacts are separated from each other. As the size of the ΐίΐΐ is reduced, the semiconductor Hercules contains more gates. However, the density of the 't' interconnect layer begins to dominate the grain size. This is mutually enchanting her high-level interconnect layer; however, the extension of the time layer is partially limited, for example, when interconnecting layers are established. , ridges, and trenches, these islands, ridges, and trenches cause cross-over Hi and trenches, semiconductor process chemical mechanical polishing (CMP), and inspection of the surface of the rotating wafer, so that each A follow-up on the surface of each other. Like the photolithography program, the CMP program is concerned; specifically, the layout characteristics of the entire die or wafer are such that some places remove excess material and other places remove the resistance of the if-wiring thickness and the interconnection line. The capacitance of the layer and the inability to shoot change, the capacitance and electricity in the interconnect layer, the timing of the key network that caused the design failure. The program requires a virtual fill (dUmniy added to the no-interconnect shape = in the middle: to enable a substantially uniform wafer topology to be set, avoiding the dishing effect and the uniformity of the edges. Conventionally, virtual The secret is set in the design stage. 如此St_design) 'So, in the knowledge of the formula, the designer does not know the virtual fill. Therefore, the virtual fill set in the design Wei section may not be designed. In addition, the conventional knowledge of =^ is unconstrained (also (four) uniform #, so ^ can not, f this 'in the conventional technology, the virtual filling area and the neighboring active. It cannot be predicted by the designer. As mentioned earlier, the __ disclosed here provides the best regulation by filling all the interconnected lans up to the maximum. If the single-interconnect ^ requires multiple networks' The interconnect track is then separated by a minimum separation gap. For example, in Figure 8a, the wire of the metal 1 wire is represented - that is, the three independent nets in the same track towel are each connected to the wire segment; more specifically , there are two more contacts S, 22 201214670 and a floating point network With the minimum spacing between the segments of the ^L track, the entire image of the resonance image is generated in the entire dynamic array. The second rule is that the rule structure of the maximum filled interconnect line is S_ It is a coincidence that the dummy fill is placed in the entire die in a uniform manner. Therefore, the regular structure of the array assists the CMP process to produce gj, sentence results in the entire die/wafer. Moreover, the regular structure of the dynamic array Contribute to the uniformity of the gate money (micro-two social two-b' combined with the most Α Α 互连 互连 互连 互连 互连 互连 互连 互连 互连 互连 规则 互连 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则 规则The feature _ 部 ϊ ϊ ϊ ϊ ϊ ϊ ϊ 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可In the rule structure, the manufacturer can optimize the manufacturing process for the rules. It should be understood: using this dynamic array, ΐίί=° unconstrained layout - the same as the arbitrarily shaped layout of the feature set Condition. How can I provide An example of the optimization of the performance of the equipment is as follows: The nm process has a metal 2 pitch of 280 nm, and the metal of the thin metal can be set by a large amount; in particular, it is made by the lithography of the through hole. Removal of the pass: the controversy of the film, the maximum performance of the device allows for gold of about 22 〇 nm = 2, the distance, so, the design rule of the metal 2 pitch contains about 25% of the tolerance to say the moon in the voicing The unpredictability of the interaction. The compensation structure implemented by your field in the transfer assistance allows the unpredictability of the light interaction of the through-hole diaper to be removed, thus reducing the tolerance of the metal 2 pitch. The reduction in the tolerance of f allows a denser design, that is, allows the wafer surface to be better used; and 'utilizes the tolerance of the defined (ie, regular) material rule provided by the dynamic array; Not only can the program performance be reduced, but the mosquito topology provided by the array also allows the required design to be purchased and reduced. For example, the typical design rule set for unconstrained topologies 23 201214670 can have more than 600 design rules, but use the design rules required for dynamic arrays, and there are only about 45 design rules for monthly b. Therefore, using the limited topology of the dynamic array, the effort required to analyze and compare the design can be reduced by more than 1 time. When dealing with the end-to-line end gap in the specific way of the mask layer of the moving_column (that is, the end of the segment to the end of the segment), there are 3 5 氕. This limited number of optical interactions can be compensated in advance so that the pair can be dramatically reduced or eliminated altogether. For online end-to-line 嶋: compensation for the interaction of the difference = representative of the lithography correction of the feature as shown, suitable for the model based on the interaction (as shown in the figure) Modifications (eg 〇pc/R£=reverse. The domain _, the change to the layout as shown in ® is only necessary, otherwise the 'OPC is implemented on the difficult layout in the custom design flow. == ===Risk. Also 'because the dynamic array s period: predicting the line-end gap's use of the lost stitches in the: ten-phase dynamic array learning; and using the body disclosed here" iifti can be logical design Separate from the physical design. Even more limited to the light in the dynamic array to evaluate with the grid point network connection; 'unrelated nature, can be countered. ·) to represent 5, and physical network Line form phase. With dynamic arrays, the design does not need to be represented by physical Wei; moreover, design 24 201214670 can be symbolically laid out. In this way, the designer can continue to move directly to the new technology. In the -real_, the basic grid dynamics, the =3 regular poor database, the basic grid (symbolic) network connection, and the dynamic array community. ^: The basic grid moves _ riding in addition to the conventional unconstrained structure. Associated with the topology-related errors; in addition, because of the manufacturability of the silk grid __ design = the design of the performance on the dynamic array is not related to the design. Therefore, due to the pre-confirmation of the secret P car shape and yield, the basic mesh network connection can be applied to the dynamic array by pre-confirming the yield performance. Figure 14 illustrates a semiconductor wafer structure 14A in accordance with an embodiment of the present invention. The bulk wafer structure 1400 represents an exemplary portion of a semiconductor wafer that includes a diffusion region 14 〇ι having a plurality of conductors 1403A-1403G defined thereon. The diffusion zone 1401 is defined in the substrate 1405 to define an active region 'descriptive diffusion region 14' for at least one of the transistor devices to cover any shape region relative to the surface of the substrate 1405. The core sets the wires 1403A-1403G' to extend over the substrate 1405 along a common direction 14〇7'. It should also be understood that we have restricted each of the plurality of wires 14〇3A_14〇3G to extend in the common direction 1407. Above the diffusion zone 1401. In one embodiment, the wires 1403A-1403G that are directly defined above the substrate 1405 are polycrystalline. In one embodiment, each of the wires 1403A-1403G' is defined to have substantially the same width 1409 in a direction perpendicular to the common extension direction 1407. In another embodiment, it is defined that some of the wires 1403A-1403G have different widths relative to the other wires. However, regardless of the width of the conductors 14〇3A-14〇3G, each of the conductors 1403A-1403G is separated from the adjacent conductors by substantially the same center-to-center spacing 1411. As shown in FIG. 14, some of the wires (1403B-1403E) extend over the diffusion region 1401 by 25 201214670, while the other wires (1403A, 1403F, 1403G) extend over the non-diffused portion of the substrate 1405. It should be understood that whether or not the wires 1403A-1403G are defined above the diffusion region 1401, the wires 1403A_1403G maintain their widths 14〇9 and spacing; in addition, it should be understood that whether or not the wires 1403A-1403G are defined in the diffusion region 14〇1 The upper 'wires 1403A-1403G remain substantially the same length 1413, thereby maximizing the lithographic enhancement between the entire on-board conductors 1403A-1403G. Certain conductors (e.g., 14 〇 3D) defined above diffusion region 1401 in this manner include a necessary active portion 1415 and more than one uniformity extension portion 1417. It will be appreciated that the semiconductor wafer structure 14A represents a portion of the dynamic array described above with respect to Figures 2-13D, and therefore, it should be understood that there is a uniform & extension portion 1417 of the conductors (14〇3B_14〇3E) to provide adjacent conductors 14〇 3A_14〇3G lithography enhancement. In addition, although it is not required for electrical pick-up, it is evaded (10) from each of 1ZK)3F, 14.3〇 to provide lithography enhancement of adjacent conductors 1403A-1403G. The J active portion 1415 and the uniformity extending portion 1417 are also applicable to the upper high layer. As described in the previous secret array structure, the nanowire layer = ϋ direction (for example, straight or diagonal, line direction) traverses the substrate so that the routing required for the logic device (_ing) is performed. / New (_ on the office) ^ can &. For example, _line 1403A-14G3G - 'in each of the interconnect layers Ϊ t ί points (uniformity extension)' to provide lithography for adjacent wires to extend #W 14〇3A_14G3G, The conductors of the interconnect have substantially the same width along the common square r, and substantially follow the line width and line spacing between the wires in the interconnect layer of t2 substantially ί i '/Γ1 as in In the case of 9Gmn, the metal spacing is 28〇nm, and the line 11111 ° ^ can be used to specify the form of the readable computer readable code described here. 26 201214670 CD-Rs woven. It can also be used on a computer that is coupled to the computer and the system, so that the computer readable code can be applied to the brain in the form of a brain-readable code. The present invention is described by way of example, but all such changes, additions, changes, and equivalents thereof are known to the skilled art. [Simple description of the schema] Each ====, _ dry layout_lang to produce generalization = display according to the invention - the rib definition __ structure defines one of the structures to assist independent - the exemplary embodiment Mapping to the entire die can be an exemplary linear feature of an embodiment of the invention, which is defined to define another embodiment of the age line transition, which is illustrated in FIG. 4 by an exemplary dynamic array in accordance with an embodiment of the present invention. The diffusion layer is located in the layer and diffuses. FIG. 6 shows a gate contact layer according to an embodiment of the present invention, which is defined in the upper layer of the layer of FIG. 5 201214670. FIG. 7A shows the contact with the interpole. a conventional method; a gate contact defined in accordance with the present invention - an embodiment; Θ ', ', a member of a metal chip according to an embodiment of the present invention, and a gate electrode layer of the second Adjacent to; FIG. 8B shows the metal 1 layer of FIG. 8A; showing a layer of through holes according to an embodiment of the present invention, which is above the metal layer 1 of the shame 8 And adjacent thereto; FIG. 1G shows gold in accordance with the present invention - an embodiment 9 is above and adjacent to the 1st layer of the through hole; /, the system is in the picture - and the invention - the real thing depends on the other, relative to the third test (χ) and (7) the first - the direction of the secret _ _;, - fen π shows a guide track according to the present invention - the traverse of the dynamic array along the second diagonal direction relative to the first and first reference directions (χ) and ω; An example of a sub-resolution contact layout according to an embodiment of the present invention is shown. The layout is configured to enhance the expansion point and the idle contact; FIG. 13A shows the second analysis of the image m according to an embodiment of the present invention. Degree joint layout, which defines a secondary resolution joint to fill the grid to the extent possible; Figure UC shows an embodiment of a secondary resolution joint layout in accordance with an embodiment of the invention, which utilizes various shapes FIG. 13D shows an exemplary completion diagram of a converted phase shift mask (APSM) having a sub-resolution contact; FIG. 14 shows a semiconductor wafer structure in accordance with an embodiment of the present invention. . [Main component symbol description] 101Α~103C Linear layout feature 103A to 103C sine Function 201 Substrate 203 diffusion region: S. 28 201214670 205 Diffusion contact 207 Gate feature 209 Gate contact 211 Metal 1 213 Through hole 1 215 metal 2 217 through hole 2 219 metal 3 221 through hole 3 223 metal 4 225 extra interconnect layer 301 linear feature 303 width of linear feature 305 length of linear feature 307 height of linear feature 309 linear feature Height 311 Linear feature length 313 Linear feature lower width 315 Linear feature upper width 317 Linear feature 401 Diffusion zone 403 Diffusion zone 405 Diffusion block 410 P+ Mask zone 412 n+ Mask zone 414 p+ Mask zone 416 n+ mask region 501 gate feature portion 501A has a greater width gate feature portion 29 201214670 503 diffusion contact 601 gate contact... 701 gate contact is extended at portion 703 outside the gate feature 703 vertical dimension 705 The distance 707 enlarges the rectangular gate region 709 gate contact 711 the gate line 801~821 metal 1 the 801A metal 1 grounding road ' 821A metal 1 electric Track 901 Through Hole 1001 Metal 2 Track 1101 Conductor Track 1201 Conductor Pass 1301 Resolution Point 1303 Grid Position 1305 "X Shape" Secondary Resolution Contact 1400 Semiconductor Wafer Structure 1401 Diffusion Region 1403A-1403G Conductor 1405 Substrate 1407 Extension direction of the wire 1409 Width of the wire 1411 Between the wires 1413 The length of the wire 1415 The necessary active portion of the wire 1417 The uniformity of the wire extension portion 30

Claims (1)

201214670 VII. Patent application scope: 1. A semiconductor device comprising a substrate portion; a plurality of diffusion regions defined by the limitation of the wire-striped f--(four) kawasaki, = and wireless features; and γ into plural The gate layer of the diffusion region is fixed above the substrate portion, and the gate layer only bites a plurality of linear gates U ^ a plurality of linear gate segments in the common direction of the substrate portion In addition, at least one of the bungee layer segments does not include a gate device that forms a crystal device, such as a semiconductor device that applies for a special fiber, and the towel product contains at least a P diffusion region and at least -n Diffusion zone, suspension s electricity _ eye _, sigh pin knot 1 expansion and 3. such as the 半 凊 patent scope of the second half of the semi-conducting semiconductor device (four) unit, and the needle substrate portion corresponds to the The sum of the MMOS transistor devices in the cell is equal. A semiconductor device in which the number of 曰 装置 装置 装置 , , , , , , 基板 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且Each of the semi-conducting fault layer segments is defined as a linear gate gate along the - corresponding linear gate track - a single direction extending in the direction of the line. Each of the - 201214670 6. If the application for the scope of the search for the fifth item The unit of the semiconductor device, and the middle portion, wherein the substrate portion corresponds to the wire-shaped closed-pole layer, and the segment/early layer comprises at least four linear gates, 7. There is a uniform_straight interval between the tracks of item 5. Difficult to set 'the towel in the adjacent linear gate 8. As in the fifth part of the patent scope, Si: between the linear gate segments defined by the touch = the semi-conductor of the first range of the range _门脑 y 10· The amount of the plurality of linear gate plies, the core 2 is end-to-end as defined by the semi-guided method of claim 9th paragraph; the segment is a fine layer and is - the measurement in the direction perpendicular to the common direction is parallel to the substrate portion. 12. The semiconductor segment of the third paragraph of the patent application is defined by the width of the substantially uniform sentence, and the parent-line gate layer is Measured in a direction perpendicular to the single-common direction, the width is flat from the substrate portion. 13. The semiconductor device according to the scope of the patent application, further comprising: S 32 201214670 The wire tie i is placed for contact - a predetermined linear gate layer segment and perpendicular to the single-common = length ^ from the parallel to the substrate length is greater than the predetermined green shape i segment 2 3 复 complex = the gate contact of the slave and the substrate portion Parallel two single == M. The semiconductor device of the first item of the range includes: Above the electrical interconnect, the interconnect layer comprises a plurality of linear interconnect layers, and a plurality of the interconnects are electrically connected to the 15. The plurality of interconnected structures in the 14th connection structure are linear. The enthalpy of the item is extended by the plurality of linear gate layer segments in the plurality of conductive mutual threshold gate layers. 17. The linear conductive interconnect structure adjacent to the semiconductor of claim π of the patent range is located adjacent to the linear interrogation layer segment in the middle layer of the layer, if the interpole, 33 201214670 is substantially perpendicular to the The plurality of linear gate layer segments in the layer extend. 2〇·1st semi-conductive 11 device, further comprising: 社媸兮绿二道=系疋 meaning above the gate layer to include a linear conductive interconnect: the system is positioned along the single-common direction And 单; the single-common direction is extended to be parallel to the substrate portion and perpendicular to any layer defined to be positioned above the gate layer in a single-common direction and a flat (b) basis = system defined in position In the first mutual green exhibition gentleman = and for the interconnection layer, its ί, or the connection layer of the line direction of the structure of the interconnect structure, the extension includes, the shape is defined in the gate Any layer above the pole layer for the substrate portion and perpendicular to the single-common direction ^ ^ ^ ^ ^ Ϊ Ϊ 定义 定义 定义 任何 任何 任何 任何 任何 任何 任何 且 且 且 且 且 且 且 且Hanging, ϊ ϊΐΐ ϊΐΐ 结构 定位 定位 定位 定位 定位 ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ ϊ 21. 21. 21. 21. 21. 21. 21. 21. 21. The semiconductor device of the present invention, wherein each segment is parallel to the substrate portion and perpendicular to the single-common square (in the middle of the interlayer layer), the light micro-shadow is used in the county; In the shadow manufacturing process, the semiconductor device of the §. 34 201214670 gas profit range item 21, wherein the wavelength of the light lithography line is less than or equal to 193 nm, and wherein the light lithography interaction + Zuo Lin Lin Yu Yu + the wire wavelength of the jade times. 23. A semiconductor device comprising: a substrate portion; a St. 纽 定 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Several of the layer segments - or multiple parts " ί = r layer segments of each of the 'series' each have 2 defined on it, 宕 green is Ming Quan, fen, ... / 夕 1 solid line a gate layer segment in which a plurality of line shapes are separated along a slice-shaped gate of the I-pole layer. τ: You place it by: Adding a team------- The end portion is "between the ends of the line 24" as claimed in the patent scope, the illusion includes at least - the diffusion region is associated with at least one of the plurality of diffusion regions and the PMOS transistor, and the region thereof, and at least a P-diffusion region is associated, and wherein the n-diffusion region and the NMOS transistor-unit M NMOS transistor 妓 in the first cell are recorded and numbered in the phantom layer segment of the 25. Or more than not formed, its t difficult number of linear gates 35 201214670 26.i=Lead ^^ semi-guided _, more package : The single common direction extends, or contains;: Γ Γ - 4; ί ^ rr, the line of the connection layer is reversed ^ the substrate 敎 extends perpendicular to the single-co-finance, i electric contains linear = straight The linear conductive interconnect structure of the first interconnect layer: = 27. The semiconductor region of the semiconductor device is as claimed in claim 23, and there is a middle in the Wei domain _^^ ^ The first diffusion shape size is different from that of his 28. semiconductor device, comprising: the substrate portion; 5· 36 201214670 The outer edge formed by the relevant right-angle side; and the solid system has more than four-common directions In this layer, only the corresponding gates defined as the two or more of the linear gate layer segments, wherein the linear gate layer is placed, are included. The latter does not include the portion of the gate forming the transistor device. 29. If the half-pole segment of the 28th article of the patent application is applied, the device is connected to the substrate and corresponds to the unit of the turn-over. The gate and one of the linear gates are in the way, and the line-shaped coffee section X is defined on the early side 3 by at least four 30. The semiconductor segment according to the scope of claim 28 is parallel to the substrate portion and is directly to the gate layer. The width of the quantity is defined 'and wherein the width dimension of the linear gate layer segment in the gate layer = measured is less than the wavelength of light used to fabricate the linear gate layer segment. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Parallel structure 'the linear conductive interconnect structure is defined to extend in the substrate portion, or to be in the direction of the common and flat; ^ interconnect layer" is defined above the gate layer to include a line shape a first interconnect layer defined as any of the 37 201214670 3 having a linear conductive interconnect structure positioned above the _ layer, the line being defined in the early-common direction and parallel to the wire portion along the line The linear input of the rr_interconnect layer above the first interconnect layer contains .=:2=5:3⁄4 in the substrate portion straight to the fresh-common ff,,. Constructing a parallel layer' is defined as being in the first mutual mutual; ^ upward ^ conductive interconnect structure, the linear conductive interconnect structure: comprising a line shape directly to the first interconnect layer The line pattern S. 38 "