CN102074582A - Integrated circuit structure and formation method thereof - Google Patents
Integrated circuit structure and formation method thereof Download PDFInfo
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- CN102074582A CN102074582A CN2010105539640A CN201010553964A CN102074582A CN 102074582 A CN102074582 A CN 102074582A CN 2010105539640 A CN2010105539640 A CN 2010105539640A CN 201010553964 A CN201010553964 A CN 201010553964A CN 102074582 A CN102074582 A CN 102074582A
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Abstract
The invention provides an integrated circuit structure and a formation method thereof, and the structure comprises a first portion in which a semiconductor substrate is contained in a first element region, and a second portion in which a semiconductor substrate is contained in a second element region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height. The invention has a positive effect on the reduction of the current crowding at the source electrode and the drain electrode regions. Because of the volume increase of the stress source electrode and the drain electrode regions, the tension and the compression strain on the channel region of a fin-type field effect transistor are increased.
Description
Technical field
The present invention relates to integrated circuit, and relate in particular to a kind of semiconductor fin keel and fin formula field effect transistor (Fin field-effect transistor; FinFet) and forming method thereof.
Background technology
Along with the increase that integrated circuit continues microminiaturization (down-scaling) and the high speed of integrated circuit is required, along with the ever-reduced while of size, transistor must have higher drive current.In order to cooperate the demand, thereby develop and fin formula field effect transistor.Because the raceway groove of fin formula field effect transistor also has extra sidewall sections except the top surface that comprises fin keel, so channel width increases.Because transistorized drive current and raceway groove are wide proportional, the drive current of fin formula field effect transistor thereby greater than planar transistor.
Summary of the invention
For overcoming the defective of above-mentioned prior art, according to one embodiment of the invention, integrated circuit structure comprises that semiconductor substrate comprises that semiconductor substrate is included in the first of first element region, and at the second portion of second element region.The first semiconductor fin keel and has the first fin keel height on semiconductor substrate.The second semiconductor fin keel and has the second fin keel height on semiconductor substrate.The first fin keel height is greater than the second fin keel height.
According to one embodiment of the invention, the formation method of integrated circuit structure comprises: the semiconductor substrate is provided, is included in a first of one first element region, and at a second portion of one second element region; On this semiconductor substrate, form one first semiconductor fin keel, and have one first fin keel height; And on this semiconductor substrate, form one second semiconductor fin keel, and have one second fin keel height, wherein this first fin keel height is greater than this second fin keel height.
The present invention also comprises other embodiment.
The present invention has positive influences for the current crowding that reduces source electrode and drain region.Because the volume of stress source electrode and drain region increases, tension force and compression stress on the channel region of fin formula field effect transistor have also been increased.In addition, also reduced the current-crowding effect of silicide area.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below:
Description of drawings
Fig. 1-Figure 10 is according to an embodiment, makes the profile in the interstage of the semiconductor fin keel with different fin keel height.
Figure 11 A, Figure 11 B, Figure 12, Figure 13, Figure 14 A, Figure 14 B, Figure 15 A-Figure 15 C, Figure 16 A and Figure 16 B are according to another embodiment, make the profile and the perspective view in the interstage of fin formula field effect transistor.
Figure 17 is presented at the element region in the semiconductor wafer.
Figure 18 shows that static RAM comprises two fin formula field effect transistors of the fin keel with different fin keel height.
Wherein, description of reference numerals is as follows:
20～substrate
100,200～element region
22～bed course
24,317～mask layer
30,30_1,30_2～shallow channel isolation area
134,234～photoresist
136,236～depression
138,238,310～fin keel
H
Fin1, H
Fin2, H
Fin'～fin keel height
160,260～fin formula field effect transistor
150,250,314～gate dielectric
152,252,316～gate electrode
318～areolar thing
320～grid separation material
324～epitaxial semiconductor layer
T～thickness
328～dotted line
327,329～line
330,332～silicide area
Embodiment
Because of different characteristic of the present invention provides several different embodiment.Specific element and arrangement are in order to simplify among the present invention, but the present invention is not exceeded with these embodiment.For example, the description that forms first element on second element can comprise the embodiment that first element and second element directly contact, and also comprises having the embodiment that extra element is formed between first element and second element, win element and second element are not directly contacted.
The method that the invention provides a kind of novelty has the semiconductor fin keel and the fin formula field effect transistor of different fin keel height degree with formation.The present invention illustrates the intermediate steps of making embodiment, and various embodiment are discussed.In the diagram and explanation of each embodiment, with similar elements symbolic representation similar elements.
With reference to Fig. 1, provide semiconductor substrate 20.In one embodiment, semiconductor substrate 20 comprises silicon.In semiconductor substrate, also can comprise material such as carbon, germanium, gallium, arsenic, indium and/or phosphorus etc. that other are commonly used.
On semiconductor substrate 20, can form bed course 22 and mask layer 24.Bed course 22 can be film and comprises and for example utilize the formed silica of thermal oxidation technology.Bed course 22 can be used as the adhesion coating of 24 of semiconductor substrate 20 and mask layers.Bed course 22 also can be used as the etching stopping layer of etching mask layer 24.In one embodiment, mask layer 24 is formed by silicon nitride, for example utilizes low-pressure chemical vapor deposition (LPCVD).In another embodiment, the formation of mask layer 24 is the hot nitrogenize (thermal nitridation of silicon) of borrowing silicon, or plasma anodic nitridation (plasma anodic nitridation).The hard mask of mask layer 24 conduct in the subsequent optical lithography process.
In substrate 20, form shallow channel isolation area 30 (being denoted as 30_1 and 30_2).The degree of depth of shallow channel isolation area 30 can be between about 100 nanometers to about 250 nanometers, but also can use other different depths.Yet, should be appreciated that size of the present invention only is usefulness for example, it can change according to employed formation technology difference.Can utilize known method to form shallow channel isolation area 30, so its process detail does not describe in detail at this.
With reference to Fig. 2, element region 100 is a mask with photoresist 134, and exposes element region 200.The shallow channel isolation area 30_2 that then exposes forms depression in etching step, and obtains the depression 236 in the substrate 20.Resulting structures as shown in Figure 3.Semiconductor substrate 20 is at the part thereby the formation fin keel 238 of 236 of depressions, and its fin keel altimeter is shown H
Fin2In one embodiment, fin keel height H
Fin2To about 30 nanometers, but it also can be greater or lesser between 15 nanometers.Then remove photoresist 134.
With reference to Fig. 4, element region 200 is a mask with photoresist 234, and exposes element region 100.The shallow channel isolation area 30_1 that exposes forms depression in etching step, and obtains caving in 136, as shown in Figure 5.Semiconductor substrate 20 is at the part thereby the formation fin keel 138 of 136 of depressions, and its fin keel altimeter is shown H
Fin1In one embodiment, fin keel height H
Fin1To about 40 nanometers, but it also can be greater or lesser between 25 nanometers.The fin keel height H
Fin1And H
Fin2Differ from one another.Difference (the H of fin keel height
Fin1-H
Fin2) absolute value can be greater than about 5 nanometers, more or greater than about 10 nanometers.And, H
Fin1/ H
Fin2Ratio can be greater than about 1.25, more or greater than about 1.33.
Then, as shown in Figure 6, remove mask layer 24 and bed course 22.If mask layer 24 is formed with silicon nitride, then can utilize hot phosphoric acid wet etch to remove, and, then can utilize diluted hydrofluoric acid to remove if bed course 22 is to form with silica.Should notice that as shown in Figure 6 the part of the substrate 20 under shallow channel isolation area 30 bottoms can be considered semiconductor substrate, and fin keel 138 and 238 can be considered on semiconductor substrate.
Fig. 7 explanation forms fin formula field effect transistor 160 and 260 respectively in element region 100 and element region 200.At first, in the mode of for example injecting, good admixture (well dopants) is imported in the fin keel 138 and 238 that exposes.In one embodiment, element region 100 is p shape fin formula field effect transistor district, element region 200 is n shape fin formula field effect transistor district, carries out n type impurity and inject with Doped n-type impurity such as phosphorus in fin keel 138, and carry out p type impurity and inject with doped p type impurity such as boron in fin keel 238.Form gate dielectric 150 and 250 respectively to cover the top surface and the sidewall of fin keel 138 and 238.Can form gate dielectric 150 and 250 by thermal oxidation, therefore can comprise thermal oxidation silicon (thermal silicon oxidation).Then on gate dielectric 150 and 250, form gate electrode 152 and 252 respectively.In one embodiment, each gate electrode 152 and 252 fin keels 138 and 238 that cover more than make resulting each fin formula field effect transistor 160 and 260 comprise the fin keel 138 and 238 more than respectively.In another embodiment, each fin keel 138 and 238 can be in order to form a fin formula field effect transistor.Then form the remaining element of fin formula field effect transistor, comprise source electrode and drain region and source electrode and drain silicide (not shown).The technology that forms these elements is known, so at this repeated description not.
Fig. 8 to Figure 10 shows another embodiment.Similar among initial configuration in this embodiment and Fig. 1.Then, with reference to Fig. 8, after element region 200 forms photoresist 234, carry out first with first dosage and inject with first impurity that mixes at shallow channel isolation area 30_1.The gained shallow channel isolation area has the first impurity concentration.Next, as shown in Figure 9, remove photoresist 234, and form photoresist 134.Carrying out second with second dosage injects with second impurity that mixes at shallow channel isolation area 30_2.The gained shallow channel isolation area has the second impurity concentration.In one embodiment, first impurity comprises phosphorus, and second impurity comprises boron.
Then, as shown in figure 10, remove photoresist 134, and for example utilize wet etching or additive method to make shallow channel isolation area 30 form depression.Owing to the doping content difference of shallow channel isolation area 30_1 and 30_2, cause the etch-rate difference of shallow channel isolation area 30_1 and 30_2, therefore formed fin keel height H
Fin1And H
Fin2Different.Different to import pattern load effect (pattern loading effect) by the patterning density that makes shallow channel isolation area 30_1 with the patterning density of shallow channel isolation area 30_2, can increase the fin keel height H
Fin1And H
Fin2Difference, make the difference of shallow channel isolation area 30_1 and 30_2 etch-rate more increase.In another embodiment, do not carry out as Fig. 8 and shallow trench isolation shown in Figure 9 from doping.Yet the patterning density of shallow channel isolation area 30_1 is different with the patterning density of shallow channel isolation area 30_2, and utilizes the pattern load effect to cause the difference of fin keel height.
In subsequent step, remove hard mask 24 and bed course 22, and form structure as shown in Figure 6.As shown in Figure 7, continue technology to form fin formula field effect transistor 160 and 260.
By the different fin keel height in different elements district, can increase knot allowance (junction window) increases, that is no longer is considered as one (tied together) at the fin keel height of the fin formula field effect transistor in different elements district.Have different fin keel height in the different elements district, can make the performance regulation and control of element region more easy.In addition, in one embodiment, fin formula field effect transistor 160 (Fig. 7) is a p type fin formula field effect transistor at element region 100, and fin formula field effect transistor 260 is a n type fin formula field effect transistor at element region 200, and the fin keel height of the p type fin formula field effect transistor 160 that is formed on is greater than the fin keel height at n type fin formula field effect transistor 260.In view of the above, p type fin formula field effect transistor 160 and n type fin formula field effect transistor 260 can be applicable to same static RAM component (Figure 18).For example, p type fin formula field effect transistor 160 can be and draws (pull-up) transistor, and n type fin formula field effect transistor 260 can be drop-down (pull-down) transistor.Compared to the n type fin formula field effect transistor 260 with higher electronics flowability, p type fin formula field effect transistor 160 bigger fin keel height can remedy its lower electric hole flowability.The performance of the performance of p type fin formula field effect transistor 160 and n type fin formula field effect transistor 260 can thereby balance.
Figure 11 A to Figure 16 B shows the interstage of making fin formula field effect transistor according to another embodiment, and wherein shallow channel isolation area 30 has different cup depths in single fin formula field effect transistor.At first, with reference to Figure 11 A and Figure 11 B, form semiconductor fin keel 310, it can be and the formed silicon fin plate of lower substrate 20 same materials.The formation of semiconductor fin keel 310 is can be substantially identical with fin keel 138 and 238 formation among Fig. 2 to Fig. 6.Figure 11 A shows longitudinal sectional drawing, and wherein dotted line represents that fin keel 310 is connected by semiconductor tape (semiconductor strip) with substrate 20.Figure 11 B shows transverse cross-sectional view.The fin keel height of semiconductor fin keel 310 is H
Fin, the fin keel of fin keel 310 is wide to be W
Fin
Then, perspective view forms gate dielectric 314 and gate electrode 316 as shown in figure 12.Gate dielectric 314 is formed on the top surface and the sidewall of fin keel 310.Gate electrode is formed on the gate dielectric 314.Then can inject, and form shallow doped source and drain electrode (LDD) district semiconductor fin keel 310.In one embodiment, as shown in figure 13, can form areolar thing 318 at the sidewall of gate dielectric 314 and gate electrode 316, the formation of wherein shallow doped source and drain region can be before or after the formation of areolar thing 318.Can optionally form mask layer 317, it can be nitride.Figure 13 also shows mask layer 317.
Then, shown in Figure 14 A, form grid separation material 320.The areolar thing 318 that forms before grid separation material 320 can comprise.Should be appreciated that grid separation material 320 can have many different variations.For example, shown in Figure 14 A, each grid separation material 320 can have nitride-oxide-nitride thing-oxide (NONO structure).In another embodiment, each grid separation material 320 can only contain one deck nitride layer and (be called the NO structure) on oxide skin(coating).The part that comes out at the shallow channel isolation area 30 of the opposing sidewalls of semiconductor fin keel 310 forms depression, and this part is not covered by gate electrode 316.The perspective view of the structure of Figure 14 A as shown in Figure 14B.The height and the grid separation material 320 that do not show fin keel 310 for clearer explanation.The fin keel 310 of resulting structures has two height.The part that fin keel 310 (channel region that also comprises the fin formula field effect transistor that forms) is covered by grid separation material 320 and gate electrode 316 has the fin keel height H
Fin, this fin keel height is with identical shown in Figure 11 B.Because the depression of shallow channel isolation area 30, the part that semiconductor fin keel 310 is not capped has the fin keel height H of increase
Fin'.In one embodiment, H
Fin' than the fin keel height H
FinAbout 2 nanometers are more or greater than about 10 nanometers.Perhaps, H
Fin'/H
FinRatio can be greater than about 1.05, more or can be, or between about 1.05 to about 1.5 greater than about 1.08.
Then, shown in Figure 15 A, form epitaxial semiconductor layer 324 at semiconductor fin keel 310 expose portion epitaxial growths.Epitaxial semiconductor layer 324 can comprise silicon, germanium, carbon and/or other known semiconductor materials.In one embodiment, the gained fin formula field effect transistor is the p type, and epitaxial semiconductor layer 324 can comprise silicon and can also comprise germanium.In another embodiment, wherein the gained fin formula field effect transistor is the n type, and epitaxial semiconductor layer 234 can comprise silicon and can also comprise carbon.The thickness T of epitaxial growth semiconductor layer can be greater than about 10 nanometers.
Another profile of structure shown in Figure 15 B displayed map 15A, wherein this profile is that the ruler 15B-15B by vertical plane gets in Figure 15 A.The fin keel height H
FinBe shown among Figure 15 B.Another profile of Figure 15 C displayed map 15A structure, wherein this profile is that the ruler 15C-15C by vertical plane gets in Figure 15 A.The fin keel height H
Fin' be shown among Figure 15 C.Compared to Figure 15 B and 15C figure, can find because the fin keel height H
FinIncrease, the volume of epitaxial semiconductor layer 234 increases.If the fin keel height of semiconductor fin keel is not by H
FinValue increases to H
Fin' value, then epitaxial semiconductor layer 234 is only limited to interregional at dotted line 328.At Figure 15 B and 15C figure, though there is not obvious visible bottom, semiconductor fin keel 310 is regarded as its bottom and upper surface flush at fin keel 310 relative edges' shallow channel isolation area.In view of the above, shown in Figure 15 B, the bottom of semiconductor fin keel 310 is directly under gate electrode 316, shown in line 327.And in Figure 15 C, the bottom of semiconductor fin keel 310 is not covered by gate electrode 316 and grid separation material 320, shown in line 329.Line (bottom) 329 is lower than line (bottom) 327.
With reference to Figure 16 A, inject to form source electrode and drain region at semiconductor fin keel 310 and epitaxial semiconductor layer 324.Remove mask layer (hard mask) 317, and form source/drain suicide areas 330 and gate silicide district 332 in epitaxial semiconductor layer 324.The formation in source/drain suicide areas and gate silicide district 332 can utilize known method.After forming silicide area 330 and 332, can consume epitaxial semiconductor layer 324 wholly or in part.In formed structure, silicide area 330 is separated with semiconductor fin keel 310 by the epitaxial semiconductor layer rest parts, or directly contacts with fin keel 310.
Another profile of structure shown in Figure 16 B displayed map 16A, wherein this profile is that the ruler 16B-16B by vertical plane gets in Figure 16 A.By depression shallow channel isolation area 30 before extension formation epitaxial semiconductor layer 324, and the volume of increase source electrode and drain region.This is for the positive influences of the current crowding (current crowding) that reduces source electrode and drain region.Because the volume of stress source electrode and drain region increases, tension force and compression stress on the channel region of fin formula field effect transistor have also been increased.In addition, because the sidewall area increase of epitaxial semiconductor layer 324 causes silicide area 330 sizes to increase, also reduced the current-crowding effect of silicide area 330.
Though the present invention discloses as above with several preferred embodiments; yet it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can changing arbitrarily and retouching, so protection scope of the present invention is as the criterion when looking the scope that claim defined of enclosing.
Claims (10)
1. integrated circuit structure comprises:
The semiconductor substrate is included in a first of one first element region, and at a second portion of one second element region;
One first semiconductor fin keel on this semiconductor substrate, and has one first fin keel height; And
One second semiconductor fin keel on this semiconductor substrate, and has one second fin keel height, and wherein this first fin keel height is greater than this second fin keel height.
2. integrated circuit structure as claimed in claim 1, wherein a top surface of a top surface of this first semiconductor fin keel and this second semiconductor fin keel is contour.
3. integrated circuit structure as claimed in claim 1 also comprises:
One first shallow channel isolation area and one second shallow channel isolation area are positioned at the relative edge of this first semiconductor fin keel, and wherein this first shallow channel isolation area and this second shallow channel isolation area have first top surface and flush with a basal surface of this first semiconductor fin keel; And
One the 3rd shallow channel isolation area and one the 4th shallow channel isolation area, wherein the 3rd shallow channel isolation area and the 4th shallow channel isolation area have second top surface and flush with a basal surface of this second semiconductor fin keel, and wherein this first top surface is lower than this second top surface.
4. integrated circuit structure as claimed in claim 1 also comprises:
One first fin formula field effect transistor comprises:
One first grid dielectric medium is on this top surface and sidewall of this first semiconductor fin keel; And
One first grid electrode is on this first grid dielectric medium; And
One second fin formula field effect transistor comprises:
One second grid dielectric medium is on this top surface and sidewall of this second semiconductor fin keel; And
One second grid electrode is on this second grid dielectric medium.
5. integrated circuit structure as claimed in claim 1, wherein this first fin formula field effect transistor is a p type fin formula field effect transistor, and this second fin formula field effect transistor is a n type fin formula field effect transistor, and wherein this first fin formula field effect transistor and this second fin formula field effect transistor are fin formula field effect transistor at same SRAM cell.
6. integrated circuit structure as claimed in claim 1, wherein this first fin keel height to the ratio of this second fin keel height greater than about 1.25.
7. the formation method of an integrated circuit structure comprises:
The semiconductor substrate is provided, is included in a first of one first element region, and at a second portion of one second element region;
On this semiconductor substrate, form one first semiconductor fin keel, and have one first fin keel height; And
Form one second semiconductor fin keel on this semiconductor substrate, and have one second fin keel height, wherein this first fin keel height is greater than this second fin keel height.
8. the formation method of integrated circuit structure as claimed in claim 7, the formation step that wherein forms this first semiconductor fin keel and this second semiconductor fin keel comprises:
Form one first shallow channel isolation area and one second shallow channel isolation area in this semiconductor substrate, wherein this first shallow channel isolation area reaches this second shallow channel isolation area at this second element region at this first element region;
Form one first mask and cover this second element region, wherein this first element region is not covered by this first mask;
Make this first shallow channel isolation area be recessed to one first degree of depth, wherein the part of this semiconductor substrate removes partly in abutting connection with one of this first shallow channel isolation area, and forms this first semiconductor fin keel;
Remove this first mask;
Form one second mask and cover this first element region, wherein this second element region is not covered by this second mask;
Make this second shallow channel isolation area be recessed to one second degree of depth, wherein the part of this semiconductor substrate removes partly in abutting connection with one of this second shallow channel isolation area, and forms this second semiconductor fin keel.
9. the formation method of integrated circuit structure as claimed in claim 7, wherein the formation step of this first semiconductor fin keel and this second semiconductor fin keel also comprises:
Form one first shallow channel isolation area and one second shallow channel isolation area in this semiconductor substrate, wherein this first shallow channel isolation area is in this first element region, and this second shallow channel isolation area is in this second element region;
With one first impurity this first shallow channel isolation area to, the first impurity concentration of mixing;
Mix this second shallow channel isolation area to the one second impurity concentration that is different from this first impurity concentration with one second impurity; And
This first shallow channel isolation area and this second shallow channel isolation area simultaneously cave in.
10. the formation method of integrated circuit structure as claimed in claim 7 also comprises:
Forming one first fin formula field effect transistor comprises:
On top surface of this first semiconductor fin keel and sidewall, form a first grid dielectric medium; And
On this first grid dielectric medium, form a first grid electrode; And
Forming one second fin formula field effect transistor comprises:
On this top surface of this second semiconductor fin keel and sidewall, form a second grid dielectric medium; And
On this second grid dielectric medium, form a second grid electrode.
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| Application Number | Priority Date | Filing Date | Title |
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| US26316409P | 2009-11-20 | 2009-11-20 | |
| US61/263,164 | 2009-11-20 | ||
| US12/871,655 US8941153B2 (en) | 2009-11-20 | 2010-08-30 | FinFETs with different fin heights |
| US12/871,655 | 2010-08-30 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6855605B2 (en) * | 2001-11-26 | 2005-02-15 | Interuniversitair Microelektronica Centrum (Imec) | Semiconductor device with selectable gate thickness and method of manufacturing such devices |
| US20050199964A1 (en) * | 2004-03-11 | 2005-09-15 | National Institute Of Advanced Industrial Science And Technology | CMOS circuit including double-insulated-gate field-effect transistors |
| US20050215014A1 (en) * | 2004-03-23 | 2005-09-29 | Young-Joon Ahn | Complementary metal oxide semiconductor (CMOS) transistors having three-dimensional channel regions and methods of forming same |
| US20060081895A1 (en) * | 2004-10-19 | 2006-04-20 | Deok-Huyng Lee | Semiconductor device having fin transistor and planar transistor and associated methods of manufacture |
| US20080105898A1 (en) * | 2003-07-21 | 2008-05-08 | International Business Machines Corporation | FET Channel Having a Strained Lattice Structure Along Multiple Surfaces |
| US20080157225A1 (en) * | 2006-12-29 | 2008-07-03 | Suman Datta | SRAM and logic transistors with variable height multi-gate transistor architecture |
| CN102088036A (en) * | 2009-12-03 | 2011-06-08 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
-
2010
- 2010-11-19 CN CN 201010553964 patent/CN102074582B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6855605B2 (en) * | 2001-11-26 | 2005-02-15 | Interuniversitair Microelektronica Centrum (Imec) | Semiconductor device with selectable gate thickness and method of manufacturing such devices |
| US20080105898A1 (en) * | 2003-07-21 | 2008-05-08 | International Business Machines Corporation | FET Channel Having a Strained Lattice Structure Along Multiple Surfaces |
| US20050199964A1 (en) * | 2004-03-11 | 2005-09-15 | National Institute Of Advanced Industrial Science And Technology | CMOS circuit including double-insulated-gate field-effect transistors |
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