TW201803084A - A cell circuit of a semiconductor device - Google Patents

Abstract

A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.

Description

Element circuit of semiconductor device

The present invention relates to a semiconductor device.

I know that the optical lithography immersion system has reached the end of its capability at a light wavelength of 193 nm and a numerical aperture (NA) of 1.35. The minimum linear resolution capability of this device is about 40 nm and about 80 nm pitch between features. The requirement for pitch between features below about 80 nm requires multiple patterning steps for a given structure type within a given wafer level. In addition, as lithography is pushed to the limit of its resolution, line-end resolution becomes more challenging. In the layout of semiconductor devices, the typical metal line pitch at a critical size of 32 nm is about 100 nm. To achieve cost-effective feature scaling, a scaling factor of 0.7 to 0.75 is expected. To achieve a zoom factor of approximately 0.75 at a critical size of 22 nm, a metal wire pitch of approximately 75 nm will be required, which is lower than the capabilities of current single exposure lithography systems and technologies. The present invention was made against this background.

In one embodiment, a semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor has a source region and a drain region within a first diffusion fin. The first diffusion fin is configured to protrude from a surface of the substrate. The first diffusion fin is constructed to extend longitudinally in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The second transistor has a source region and a drain region within a second diffusion fin. The second diffusion fin is configured to protrude from the surface of the substrate. The second diffusion fin is constructed to extend longitudinally in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin. The second diffusion fin is configured to be adjacent to the first diffusion fin and to be spaced apart from the first diffusion fin. In addition, at least one of the first end or the second end of the second diffusion fin is disposed in the first direction between the first end of the first diffusion fin and the second Between the ends.

In one embodiment, a method of manufacturing a semiconductor device is disclosed. The method includes providing a substrate. The method also includes forming a first transistor on the substrate such that the first transistor has a source region and a drain region within a first diffusion fin, and the first diffusion fin The structure is configured to protrude from a surface of the substrate, and the first diffusion fin is configured to form a first end from a first end of the first diffusion fin to a second end of the first diffusion fin Extend longitudinally in the direction. The method also includes forming a second transistor on the substrate, such that the second transistor has a source region and a drain region within a second diffusion fin, and the second diffusion fin It is constructed to protrude from the surface of the substrate, and the second diffusion fin is constructed from a first end of the second diffusion fin to a second end of the second diffusion fin at the first It extends longitudinally in the direction such that the second diffusion fin is formed immediately adjacent to the first diffusion fin and spaced apart from the first diffusion fin. In addition, the first and second transistor systems are formed such that at least one of the first end or the second end of the second diffusion fin is interposed between the first diffusion fin in the first direction The portion is formed at a position between the first end and the second end.

In one embodiment, a data storage device has computer executable program instructions for providing a layout of a semiconductor device stored thereon. The data storage device includes computer program instructions that define a first crystal formed on a substrate so that the first transistor is defined as having a source region and a drain region within a first diffusion fin, And the first diffusion fin is defined as protruding from a surface of the substrate, and the first diffusion fin is defined as a first end of the first diffusion fin to the first diffusion fin The second end extends longitudinally in a first direction. The data storage device also includes computer program instructions that define a second crystal formed on the substrate so that the second transistor is defined as having a source region and a drain region within a second diffusion fin And the second diffusion fin is defined to protrude from the surface of the substrate, and the second diffusion fin is defined to extend from a first end of the second diffusion fin to the second diffusion fin A second end portion extends longitudinally in the first direction, and the second diffusion fin is defined to be disposed adjacent to and spaced apart from the first diffusion fin, and the second diffusion fin is defined as At least one of the first end or the second end is disposed between the first end and the second end of the first diffusion fin in the first direction.

In the following description, a number of specific details are described to provide a complete understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without some or all of these specific details. In other respects, well-known process operations are not described in detail so as not to unnecessarily obscure the present invention. In addition, it should be understood that the various circuit and / or layout features depicted in a particular illustration shown here may be different from other circuit and / or layout features depicted in other drawings shown here Department combination.

"Fin field effect transistors" are transistors constructed from vertical silicon islands (ie fins). Fin-type field effect transistors can also be called three-gate transistors. The term "fin field effect transistor" as used herein refers to any transistor structure including a diffusion structure protruding upward from the underlying substrate. 1A and 1B show an exemplary layout view of a fin field effect transistor 100 according to several embodiments of the present invention. The fin field effect transistor 100 is composed of a diffused fin portion 102 and a gate electrode layer 104. The diffusion fin 102 protrudes vertically upward from the substrate 105, as shown in FIG. 1B. The gate oxide layer 106 is disposed between the diffusion fin 102 and the gate electrode layer 104. The diffusion fin 102 may be doped to form a p-type transistor or an n-type transistor. The portion of the gate electrode layer 104 covering the diffusion fin 102 forms the gate electrode of the fin field effect transistor 100. Therefore, relative to the control provided by one side in a non-fin field effect transistor, the gate electrode of the fin field effect transistor 100 may exist on more than three sides of the diffusion fin 102, thereby providing three The control of the fin field effect transistor channel on the above side. In addition, in some embodiments, the fin-type field effect transistor is formed as a “wrap-around” transistor, in which the gate oxide layer 106 and the gate electrode layer 104 also extend under the diffusion fin 102.

It should be understood that the exemplary fin field effect transistor 100 depicted in FIGS. 1A and 1B is provided for the purpose of illustration, and does not represent the design and / or manufacturing method of the fin field effect transistor referred to herein. Any restrictions. Specifically, in several embodiments, the diffusion fins (such as 102) may be formed as a layer of different materials, including but not limited to Si (silicon), SiGe (silicon germanium), Ge (germanium), InP (phosphorus Indium), CNT (carbon nanotube), SiNT (silicon nanotube), or any combination thereof. The gate oxide layer 106 can be formed from many different types of dielectric materials. For example, in some embodiments, the gate oxide layer 106 may be formed as a hafnium oxide layer on a silicon dioxide layer. In other embodiments, the gate oxide layer 106 can be formed from more than one other dielectric material. In some embodiments, the gate electrode layer 104 may be formed of any number of conductive materials. For example, in some embodiments, the gate electrode layer 104 may be formed as a TiN (titanium nitride) film or a TaN (tantalum nitride) film covered with polysilicon. However, it should be understood that in other embodiments, the gate electrode layer 104 may be formed of other materials.

In addition, although the exemplary diffusion fin 102 of FIG. 1B is shown in this vertical cross-sectional view AA as having a substantially vertically projecting rectangular structure with respect to the substrate 105, it should be understood that on a semiconductor wafer The diffused fin 102 in the "fabricated" state may or may not have a rectangular structure that protrudes substantially vertically with respect to the substrate 105. For example, in some embodiments, the diffusion fin 102 in its "as-fabricated" state may have a more triangular or pyramidal shape in the vertical cross-sectional view A-A. FIG. 1C shows a variation of the fin-type field effect transistor 100 in which the diffusion fin 102 is more pyramidal in the vertical cross-sectional view A-A. As depicted in FIG. 1C, in some embodiments, the side of the diffusion fin 102 extending upward from the substrate 105 may extend upward from the substrate at an angle relative to the substrate 105 so as not to be perpendicular to the substrate 105. In addition, it should be understood that this non-vertical relationship between the substrate 105 and the side of the diffusion fin 102 extending upward from the substrate 105 may be the result of design or manufacturing.

In addition, in some embodiments, the vertical protrusion distance of the diffusion fin 102 above the substrate 105 is substantially equal within a region of the semiconductor wafer. However, in other embodiments, several diffusion fins 102 may be designed and manufactured to have a plurality of different vertical protrusion distances above the substrate 105 within one or more regions of the semiconductor wafer. Because the channel area of the fin field effect transistor 100 is a function of the vertical protrusion distance of the diffusion fin 102 above the substrate 105, this change in the vertical protrusion distance of the diffusion fin 102 above the substrate 105 can be used to adjust the selected fin field effect transistor 100 relative to the semiconductor The driving strength of others on the wafer. In one example, the selective change in the height of the diffusion fin 102 may be provided by selectively etching / over-etching the diffusion fin 102 structure during manufacturing.

FIG. 1D shows a simplified vertical cross-sectional view of a substrate 105 having a plurality of fin-type field effect transistors 100 formed thereon according to some embodiments of the present invention. During the manufacture of the fin field effect transistor 100, a series of cores 107 are formed to facilitate the formation of the side spacers 109 of each of the cores 107. The side spacer 109 is used as a mask feature to promote the formation of the lower fin field effect transistor 100. It should be understood that the core 107, the side spacer 109, and the fin field effect transistor 100 extend longitudinally in a parallel manner, that is, extend into the page direction as shown in FIG. 1D. It should be understood that the core 107 and the side spacer 109 are finally removed and do not exist in the as-fabricated semiconductor wafer / device. The relative spacing of the fin-type field effect transistor 100 to each other is a function of the size and spacing of the core 107 and the side spacer 109.

FIG. 1D shows the core 107 as having a width Wb and a pitch Pb. In addition, FIG. 1D shows the side spacer 109 as having a width Ws. In this way, the fin-type field effect transistor 100 can be characterized as having a pair of alternating fin pitches Ps1, Ps2, where Ps1 is the average centerline-to-centerline pitch between the side spacers 109 of a given core 107 (Ps1 is called the inner fin pitch), and Ps2 is the average centerline-to-centerline pitch between adjacent side spacers 109 of the adjacently arranged cores 107 (Ps2 is called the outer fin pitch distance). Assuming that the width Wb of each core 107, the pitch Pb of the core 107, and the width Ws of the side spacer 109 are the same, the inner fin pitch Ps1 is equal to the sum of the width Wb of the core 107 and the width Ws of the side spacer 109. In addition, the outer fin pitch Ps2 is equal to the sum of the pitch Pb of the core 107 minus the width Wb of the core 107 and the width Ws of the side spacer 109. Therefore, both the inner fin pitch Ps1 and the outer fin pitch Ps2 will change as each of the core 107 pitch Pb, the core 107 width Wb, and / or the side spacer 109 width Ws changes. Therefore, it should be understood that referring to a specific "fin pitch" refers to the average of a specific fin pitch, that is, the fin pitch Ps_ave is equal to the inner fin pitch Ps1 and the outer fin pitch The average of the pitch Ps2, wherein each of the inner fin pitch Ps1 and the outer fin pitch Ps2 is itself an average value. The relationship between width and pitch in Figure 1D is as follows: Ps1 = Wb + Ws Ps2 = Pb – Wb – Ws Pb = Ps1 + Ps2 If Ps1 = Ps2 (that is, an equal fin pitch), then: Wb + Ws = Pb – Wb – Ws → Pb = 2 (Wb + Ws) Ps1 and Ps2 can change as Pb, Wb, and / or Ws changes. Therefore, referring to a specific "fin pitch" refers to the average of a specific fin pitch, that is, Ps_ave is equal to the average Ps1 and the average Ps2.

FIG. 1E shows a diagram of fin pitch relationships according to several embodiments of the present invention, where the inner fin pitch Ps1 is substantially equal to the outer fin pitch Ps2. The element height Hc is equal to the average fin pitch multiplied by a rational number, which is multiplied by the ratio of integers x and y, where x is the numerator of the rational number and y is the denominator of the rational number. In the example of FIG. 1E, where the inner fin pitch Ps1 and the outer fin pitch Ps2 are equal, the average fin pitch is equal to each of Ps1 and Ps2. Therefore, the element height Hc is equal to either the inner fin pitch Ps1 or the outer fin pitch Ps2 multiplied by the rational number. It should be understood that the denominator (y) of the rational number represents the number of an element. When the number of elements is arranged in the direction of the element height Hc (ie, the direction perpendicular to the longitudinal direction of the fin) in an abutting manner, the number of elements is required to obtain Repeat the distance from the part to the component boundary. In addition, when the numerator (x) of the rational number is divisible by the rational denominator (y), the top and bottom element boundaries are aligned at the inner fin pitch Ps1 and / or outer fin pitch Ps2 (indexed to) The device boundary may have the same fin-to-device boundary spacing. The relationship between height and pitch in Figure 1E is as follows: Hc = (x / y) (Ps1) or Hc = (x / y) (Ps2), where x and y are integers in the example of Figure 1E, Ps1 = Ps2 → Pb = 2 (Wb + Ws) x = 9, y = 1 → Hc = (9/1) (Ps1) or Hc = (9/1) (Ps2) Because y = 1, the distance from the fin to the device boundary is every The element height is repeated once, and since x is divided by y, when at least one fin pitch (Ps1 or Ps2) is aligned with an element boundary, the top and bottom element boundaries may have the same fin-to-element boundary spacing.

FIG. 1F shows a variation of the relationship diagram of the fin pitch of FIG. 1E according to several embodiments of the present invention, in which the denominator (y) of the rational number is two. Therefore, in FIG. 1F, the pitch from the fin to the element boundary repeats every two element heights Hc. In addition, in the example of FIG. 1F, the rational number numerator (x) is not divisible by the rational number denominator (y). Therefore, when the inner fin pitch Ps1 and / or the outer fin pitch Ps2 are aligned (indexed to) at the element boundary, the top and bottom fin to element boundary spacing will be different. The relationship between height and pitch in Figure 1F is as follows: Hc = (x / y) (Ps1) or Hc = (x / y) (Ps2), where x and y are integers in the example of Figure 1F, Ps1 = Ps2 → Pb = 2 (Wb + Ws) x = 17, y = 2 → Hc = (17/2) (Ps1) or Hc = (17/2) (Ps2) Because y = 2, the distance from the fin to the device boundary is every two The element height is repeated once, and because x is not divisible by y, when at least one fin pitch (Ps1 or Ps2) is aligned with an element boundary, the top and bottom element boundaries will have different fin-to-element boundary spacing.

FIG. 1G shows a change in the diagram of the pitch relationship of the fin of FIG. 1E according to several embodiments of the present invention, in which the denominator (y) of the rational number is three. Therefore, in FIG. 1G, the pitch from the fin to the element boundary repeats every three element heights Hc. In addition, in the example of FIG. 1G, the rational number numerator (x) is not divisible by the rational number denominator (y). Therefore, when the inner fin pitch Ps1 and / or the outer fin pitch Ps2 are aligned (indexed to) at the element boundary, the top and bottom fin to element boundary spacing will be different. It should be understood that the rational number can be defined in any way necessary to obtain any desired fin-to-device boundary pitch repetition frequency and / or any desired fin-to-device boundary pitch specification in the device height Hc direction.

1H shows a more generalized version of the fin pitch relationship diagram of FIG. 1E according to several embodiments of the present invention, where the inner fin pitch Ps1 and the outer fin pitch Ps2 are different. In this example, the outer fin pitch Ps2 is greater than the inner fin pitch Ps1. It should be understood that the element height Hc is equal to the average fin pitch Ps_ave times the rational number (x / y), where x and y are integers. In addition, it should be understood that the integer y represents the repetition frequency of the pitch from the fin to the element boundary in the element height Hc direction. In addition, it should be understood that when the rational number (x / y) is reduced to an integer value (that is, when x is divided by y), the top and bottom fins to the element boundary spacing may be equal to each other. If the rational number (x / y) cannot be reduced to an integer value, the phase change of different fins of a specific device can be defined in the device library, where the phase change of each fin corresponds to the different possible fin-to-device boundary spacing of the specific device relationship. In addition, the number of possible fin phase changes for a particular element will be equal to the denominator (y) of the mathematically simplest rational number (x / y). The relationship between height and pitch in Figure 1G is as follows: Hc = (x / y) (Ps1) or Hc = (x / y) (Ps2), where x and y are integers. In the example of Figure 1G, Ps1 = Ps2 → Pb = 2 (Wb + Ws) x = 25, y = 3 → Hc = (25/3) (Ps1) or Hc = (25/3) (Ps2) Because y = 3, the fin-to-component boundary spacing is every three The element height is repeated once, and because x cannot be divided by y, when at least one fin pitch (Ps1 or Ps2) is aligned with a device boundary, the top and bottom device boundaries will have different fin-to-device boundary spacing.

As discussed above, FIG. 1H shows the use of two different diffusion fin pitches Ps1 and Ps2 according to several embodiments of the present invention. More specifically, in FIG. 1H, every other pair of adjacently arranged diffusion fin structures are arranged according to a smaller pitch Ps1. In several embodiments, the larger diffusion fin pitch Ps2 is about 80 nanometers (nm) and the smaller diffusion fin pitch Ps1 is about 60 nm. However, it should be understood that in other embodiments, the smaller diffusion fin pitch Ps1 may be any size, and the larger diffusion fin Ps2 may be any size. It should be understood that several embodiments may utilize more than two diffusion fin pitches within a particular element or block. Furthermore, several embodiments may utilize a single diffused fin pitch within a specific device or block. In addition, it should be understood that any layer or part of the semiconductor device may be formed in a manner similar to the diffusion fin pitch described herein. For example, a local interconnect layer or a high-level interconnect layer of a semiconductor device, or a portion thereof, may be formed by more than one corresponding pitch in a manner similar to that described herein regarding the pitch of the diffusion fins The internal conductive structure. The relationship between height and pitch in Figure 1H is as follows: Hc = (x / y) (Ps_ave), where x and y are integers, and Ps_ave is the average fin pitch, for example [(Ps1 + Ps2) / 2] in Figure 1H In the example, Ps2> Ps1 x = 10, y = 1 → Hc = (10/1) (Ps_ave) Because y = 1, the distance from the fin to the device boundary is repeated once for each device height, and because x is divided by y When at least one fin pitch (Ps1 or Ps2) is aligned with an element boundary, the top and bottom element boundaries may have the same fin-to-element boundary spacing.

Due to gate oxide limitations and / or source / drain leakage current ratio issues, transistor scaling has slowed below the critical size of 45 nanometers (nm). Fin field effect transistors alleviate these problems by controlling the channels of the fin field effect transistors from three sides. The increased electric field in the channel of the fin field effect transistor improves the relationship between I-on (on drive current) and I-off (subcritical leakage current). Fin-type field effect transistors can be applied to critical dimensions of 22 nm and below. However, due to its vertical protrusion, the fin field effect transistor may have a limited configuration in various circuit layouts. For example, there may be a necessary minimum spacing between fin field effect transistors, and / or a necessary minimum pitch between fin field effect transistors, etc. The embodiment of the device layout disclosed herein uses fin field effect transistors in a manner that improves layout scaling.

The cell mentioned here represents the abstract name of the logic function (abstraction) and includes the lower-order integrated circuit layout used to implement this logic function. It should be understood that a specific logic function can be represented by multiple device variants, where the multiple device variants can be distinguished by feature size, performance, and process compensation technique (PCT) processing. For example, multiple device variants for specific logic functions can be distinguished by power consumption, signal timing, leakage current, chip area, OPC (optical proximity correction), RET (reticle enhancement technology), etc. In addition, multiple component changes can be distinguished by the sub-layout sequence combination described herein. It should also be understood that the description of each element is included in the layout of the element in each level (or layer) of the chip within the associated vertical column of the chip, which is required to perform the logic function of the element. More specifically, the description of the device includes the layout of the device in each chip level that extends from the substrate level through a specific interconnect level.

2A shows an exemplary device layout including fin field effect transistors according to several embodiments of the invention. The device layout includes a diffusion hierarchy in which a plurality of diffusion fins 201A / 201B are defined, which are used for the subsequent formation of fin field effect transistors and related connecting lines. In several embodiments, in the as-drawn layout state, the diffusion fins 201A / 201B are linear. The diffusion fins 201A / 201B are oriented parallel to each other so that their length extends in a first direction (x) and their width extends in a second direction (y) perpendicular to the first direction (x) .

In some embodiments, such as shown in FIG. 2A, the diffuser fins 201A / 201B are configured according to a fixed longitudinal centerline to longitudinal centerline pitch 203, which is in the second direction (y) Measured. In this embodiment, the pitch 203 of the diffusion fins 201A / 201B may be related to the element height measured in the second direction (y) so that the diffusion fin pitch 203 can continue across the element boundary. In FIG. 2A, the element adjacent edge represents the element boundary parallel to the diffusion fins 201A / 201B. In several embodiments, the diffusion fins of multiple adjacent elements will be configured according to a common global diffusion fin pitch, thereby assisting wafer level fabrication of the diffusion fins in multiple elements.

It should be understood that other embodiments may use multiple diffusion fin pitches within a particular element or between a group of elements. For example, FIG. 2H shows a variation of the element of FIG. 2A according to several embodiments of the present invention, in which two different diffusion fin pitches 203 and 205 are used. It should be understood that in several embodiments, the diffusion fins 201A / 201B may be configured according to more than one longitudinal centerline to longitudinal centerline pitch, or may be configured in an unlimited manner with respect to the longitudinal centerline to longitudinal centerline spacing Configuration. In addition, in some embodiments, the diffusion fins 201A / 201B may be configured according to a specific pitch, and several pitch positions may be unused with respect to the diffusion fin configuration. In addition, in some embodiments, the diffuser fins may be separated and arranged end-to-end at specific diffuser fin pitch positions within an element.

In each pattern shown here, each diffusion fin (for example, diffusion fin 201A / 201B in FIG. 2A) is an n-type diffusion material or a p-type diffusion material. In addition, depending on the specific device implementation, the material types of the diffusion fins can be exchanged to achieve different device logic functions. Therefore, the type 1 diffusion fin and type 2 diffusion fin designations are used in the illustration to indicate the different material types of the diffusion fin. For example, if the type 1 diffusion fin material is an n-type material, the type 2 diffusion fin material is a p-type material, and vice versa.

The device layout also includes several linear gate electrode structures 207. The linear gate electrode structure 207 extends in a direction substantially perpendicular to the diffusion fins 201A / 201B, that is, in the second direction (y). When manufacturing, the linear gate electrode structure 207 covers the diffusion fins 201A / 201B to form the gate electrode of the fin field effect transistor. It should be understood that a suitable gate oxide material is arranged (ie, configured / deposited) between the diffusion fins 201A / 201B and the gate electrode structure 207 formed thereon.

In some embodiments, the linear gate electrode structure 207 is added according to a fixed gate pitch 209 measured between the longitudinal centerlines of the gate electrode structures 207 adjacently arranged in the first direction (x) Configuration. In several embodiments, the gate pitch 209 is related to the element width measured in the first direction (x), so that the gate pitch can continue across the element boundary. Therefore, in some embodiments, the gate electrode structures 207 of a plurality of adjacent elements can be configured according to a common global gate pitch, thereby assisting the chip of the linear gate electrode structure 207 among the multiple elements Class manufacturing.

It should be understood that several gate pitch positions in a particular element can be occupied by the gate electrode structure 207, while other gate pitch positions in the particular element remain unoccupied. Therefore, it should be understood that the plurality of gate electrode structures 207 may be arranged along any gate electrode pitch position within a specific element in a separated, end-to-end manner. It should be further understood that in several embodiments, the gate electrode structure 207 may be configured according to more than one gate pitch, or may be configured in an unlimited manner with respect to the gate pitch.

The device layout may also include several linear horizontal local interconnect structures (lih) 211, and / or several linear vertical local interconnect structures (liv) 213. The vertical partial interconnect structure 213 is oriented parallel to the gate electrode structure 207. The horizontal partial interconnect structure 211 is oriented parallel to the diffusion fins 201A / 201B. In some embodiments, the configuration of the vertical partial interconnect structure 213 is defined to be out of phase with the configuration of the gate electrode structure 207 at a half-gate pitch. Therefore, in this embodiment, when the adjacent gate electrode structures 207 of each vertical partial interconnection structure 213 are arranged on the gate pitch, the vertical partial interconnection structure 213 is located on its adjacent gate structure Center between 207. Therefore, in this embodiment, the adjacently arranged vertical local interconnect structures 213 will have a center-to-center spacing equal to a local gate pitch or a global gate pitch, where the local gate pitch is applicable Within a specific element, the global gate pitch is applicable over a range of elements.

In some embodiments, the configuration of the horizontal local interconnect structure 211 is defined to be out of phase with the configuration of the diffusion fins 201A / 201B at half the pitch of the diffusion fins. Therefore, in this embodiment, when the adjacent diffusion fins 201A / 201B of the horizontal partial interconnection structure 211 are disposed on the pitch of the diffusion fins, the horizontal partial interconnection structure 211 may be located on the adjacent diffusion fins The center between 201A / 201B. Therefore, in this embodiment, adjacently arranged horizontal local interconnect structures 211 will have a center-to-center spacing equal to a local diffusion fin pitch or a global diffusion fin pitch, where the local diffusion fin sections The pitch is suitable for a specific element, and the global diffusion fin pitch is suitable for a range of multiple elements.

In some embodiments, the device layout also includes several linear metal layer 1 (met1) interconnect structures 215. The met1 interconnect structure 215 is oriented parallel to the diffusion fins 201A / 201B and perpendicular to the gate electrode structure 207. In some embodiments, the configuration of the met1 interconnect structure 215 is defined to be out of phase with the configuration of the diffusion fins 201A / 201B at half the pitch of the diffusion fins. Therefore, in this embodiment, although at a higher wafer level, when the adjacent diffusion fins of each met1 interconnect structure 215 are arranged on the diffusion fin pitch, the met1 interconnect structure 215 is located at The center between its adjacent diffusion fins. Therefore, in this embodiment, the adjacently configured met1 interconnect structure 215 will have a center-to-center spacing equal to a local diffusion fin pitch or a global diffusion fin pitch, where the local diffusion fin pitch It is suitable for a specific element, and the global diffusion fin pitch is suitable for a range of multiple elements. In some embodiments, the 215 pitch of the met1 interconnect structure, and thus the diffusion track pitch, is set at a single exposure lithography limit, such as 80 nm for 1.35 NA and 193 nm wavelength light. In this embodiment, double exposure lithography, that is, multiple patterning is not required to fabricate the met1 interconnect structure 215. It should be understood that other embodiments may use the met1 interconnect structure 215 oriented perpendicular to the diffusion fins 201A / 201B and parallel to the gate electrode structure 207.

The device layout also includes a number of contact windows 217, which are used to connect various met1 interconnect structures 215 to various local interconnect structures 211/213 and gate electrode structures 207, thereby providing various functions required to implement the logic function of the device The electrical connection between fin field effect transistors. In several embodiments, the contact window 217 is defined to satisfy the single exposure lithography limit. For example, in several embodiments, the layout features required for the contact window 217 to be connected are separated enough for single exposure manufacturing of the contact window 217. For example, the met1 interconnect structure 215 is defined as its line end for receiving the contact window 217, and is sufficiently separated from the line end of the adjacent met1 interconnect structure 215 which also accepts the contact window 217, so that The spatial distance between the contact windows 217 is large enough to perform the single exposure lithography process of the contact windows 217. In several embodiments, adjacent contact windows 217 are separated from each other by at least 1.5 times the gate pitch. It should be understood that by sufficiently separating the opposite line ends of the met1 interconnect structure 215, the line end cutting of the double exposure lithography process and the associated increased costs can be eliminated. It should be understood that, depending on the selection in the manufacturing process, the contact window spacing and the wire end spacing on the metal layer may be independent of each other in several embodiments.

In some embodiments, the device layout also includes several linear metal layer 2 (met2) interconnect structures 219. The met2 interconnect structure 219 is oriented parallel to the gate electrode 207 and perpendicular to the diffusion fins 201A / 201B. The met2 interconnect structure 219 can be physically connected to the met1 interconnect structure 215 through the via structure (v1) 221 according to the needs of implementing the logic function of the device. Although the example device of FIG. 2A shows a met1 interconnect structure 215 extending vertically to the gate electrode structure 207 in a longitudinal manner and a met2 interconnect structure 219 extending parallel to the gate electrode structure 207 in a longitudinal manner, it should be understood that In other embodiments, the met1 interconnect structure 215 and the met2 interconnect structure 219 may be defined to extend in any direction relative to the gate electrode structure 207. It should be understood that other embodiments may use the met2 interconnect structure 219 oriented perpendicular to the gate electrode 207 and parallel to the diffusion fins 201A / 201B.

The element of FIG. 2A represents a multi-input logic gate having substantially aligned input gate electrodes, that is, three gate electrode structures 207 centered together in the direction (y). Depending on the type of diffusion material assigned to Type 1 and Type 2 diffusion fins, the elements of FIG. 2A may have different logic functions. For example, FIG. 2D shows the layout of FIG. 2A, where the diffusion fin 201A is formed of n-type diffusion material and the diffusion fin 201B is formed of p-type diffusion material. The layout of FIG. 2D is the layout of the 2-input NAND gate. FIG. 2B shows a circuit diagram corresponding to the 2-input NAND structure of FIG. 2D. 2E shows the layout of FIG. 2A, in which the diffusion fin 201A is formed of p-type diffusion material, and the diffusion fin 201B is formed of n-type diffusion material. The layout of FIG. 2E is the layout of the 2-input NOR gate. FIG. 2C shows a circuit diagram corresponding to the 2-input NOR configuration of FIG. 2E. In Figures 2B-2E, P1 and P2 each indicate their respective p-type transistors (such as PMOS transistors), N1 and N2 each indicate their respective n-type transistors (such as NMOS transistors), A and B Each is marked with its own input node, and Q is marked with an output node. It should be understood that similar symbols for p-type transistors, n-type transistors, input nodes, and output nodes are also used in other illustrations here.

Based on the foregoing, it should be understood that the logic function of a specific device layout can be changed by swapping the material types of the diffusion fins. Therefore, for the various element layouts described herein, it should be understood that the n-type and p-type materials that may be assigned to the diffusion fins represent multiple logic functions.

Figures 3 to 7 and 11 to 29 show variations of the layout of Figure 2A according to several embodiments of the invention. Therefore, each of the elements depicted in FIGS. 3 to 7 and 11 to 29 depends on the n-type and p-type materials assigned to the type 1 diffusion fins and type 2 diffusion fins to represent 2 Input NAND gate or 2 input NOR gate. Each of the device layouts shown in FIGS. 2A to 7 and 11 to 19 has the following characteristics: l a multi-input logic gate, all of its input electrodes are substantially aligned, l a local diffusion fin layer power supply, l a global comparison High-level interconnect power, a horizontal interconnect for connecting the gate electrode to a vertical local interconnect, and for improving the manufacturability of the contact layer by providing greater flexibility in the configuration of the contact window .

It should be understood that the layouts in FIGS. 2A to 7 and 11 to 29 each show different implementations of the same logic function. The layout of FIG. 2A shows the following features: l two or more gate electrodes for input, the gate electrodes are substantially aligned, l the end line spacing of the gate electrode between diffusion fins of the same diffusion type, l Gate electrode contact window between diffusion fins of the same diffusion type, l Type 1 and type 2 diffusion fins for local power supply (that is, local interconnects to components), of which met1 is used for higher Hierarchical interconnection (global) power supply, both local and global power supplies are shared by adjacent components. L Type 1 and type 2 diffusion fins supply current to components on a local hierarchy and can be connected to Higher-level interconnects, such as met1, to support multiple chip power countermeasures, l use horizontal local interconnects to connect to the gate electrode, l connect the vertical local interconnect layer to the gate electrode layer The upper horizontal local interconnect can be used to translate the position of the gate electrode contact window, thereby increasing the flexibility on the contact window mask pattern, which can alleviate possible lithography problems.

According to several embodiments of the present invention, FIG. 2F shows a variation of the layout of FIG. 2A in which the gate electrode structure ends are substantially aligned at the top of the element (as indicated by ellipse 250) and at the bottom of the element (as indicated by ellipse 251).

According to several embodiments of the present invention, FIG. 2G shows a variation of the layout of FIG. 2A, in which a contact window is formed so that the power supply The lower part of the power rail extends from the met1 interconnection structure to the horizontal partial interconnection structure.

As previously mentioned, according to several embodiments of the present invention, FIG. 2H shows a variation of the element of FIG. 2A, in which two different diffusion fin pitches 203 and 205 are used.

It should be understood that in the various layouts described here, the diffusion fins and the horizontal local interconnect structure at the top and bottom of the element under the power rails continuously extend in the horizontal direction (x) to apply Multiple elements, which are arranged in one row and possibly in adjacent rows. To illustrate this, according to several embodiments of the present invention, FIG. 2I shows a variation of the layout of FIG. 2A, in which the diffused fins and the horizontal local interconnect structure under the power rails at the top and bottom of the device are extended to extend the interconnect structure of met1 The full width of 215A / 215B, met1 interconnect structure 215A / 215B is used as a power rail. It should be understood that the diffusion fins and the horizontal local interconnect structure under the 215A / 215B as the power rail, and the 215A / 215B itself as the power rail continue to extend in the (x) direction, as shown by arrow 270 .

3 shows a variation of the layout of FIG. 2A according to several embodiments of the present invention, in which the met1 power rail is connected to a vertical local interconnect so that the met1 power rail serves as a local power source. It should be understood that the met1 power rail can have a variable width based on the needs of the component library. Like the layout of FIG. 2A, the layout of FIG. 3 uses multiple input logic gates with input electrodes substantially aligned.

FIG. 4 shows a variation of the layout of FIG. 2A according to several embodiments of the present invention, in which a two-dimensionally changed met1 interconnect structure is used inside the device for internal wire routing. As in the layout of FIG. 2A, the layout of FIG. 4 uses a multi-input logic gate whose input electrodes are substantially aligned and share local and global power supplies. In several embodiments, the bending in met1, that is, the two-dimensional change in the direction of met1, occurs in a fixed grid. In some embodiments, this fixed grid of met1 may include horizontal grid lines, which are arranged between the diffusion fins and extend parallel to the diffusion fins, and have the same pitch as the diffusion fins To be configured. In addition, in some embodiments, the met1 fixed grid may include vertical grid lines that extend perpendicular to the diffusion fins and are configured to be located in the center of the vertical local interconnect.

FIG. 5 shows a variation of the layout of FIG. 2A according to several embodiments of the present invention, in which the met1 power rails are connected to vertical local interconnects, so that the met1 power rails are used as local power supplies, and in which two-dimensional changes are met1 The wire structure is used for winding inside the element. Like the layout of FIG. 2A, the layout of FIG. 5 uses multiple input logic gates with input electrodes substantially aligned.

FIG. 6 shows a variation of the layout of FIG. 2A according to several embodiments of the present invention, in which a fixed, minimum width, common local met1 power supply is used, and a two-dimensional variation met1 interconnect structure used for in-device winding within the device. As with the layout of FIG. 2A, the layout of FIG. 6 uses multiple input logic gates with input electrodes substantially aligned.

7 shows a variation of the layout of FIG. 2A according to several embodiments of the present invention, which has a shared local and global power supply with hard wiring in the device, and a two-dimensional variation met1 for intra-component winding within the device.线 结构。 Line structure. As with the layout of FIG. 2A, the layout of FIG. 7 uses multiple input logic gates with input electrodes substantially aligned.

According to several embodiments of the present invention, FIG. 8A shows a layout illustrating an exemplary standard device, in which input pins are arranged between diffusion fins of the same type to alleviate winding congestion, and several diffusion fins are used as interconnect conductors. 8C shows a circuit diagram of the layout of FIG. 8A, including input pins 8a, 8b, 8c, and 8d. Planar standard components, ie, non-fin field-effect transistor components, usually have input pins between the diffused features of the opposite type (ie, n-type versus p-type), or between the diffused features and adjacent power rails In this way, a higher density of input pins is achieved in the local area of the planar element. As shown in FIG. 8A, by using diffusion fins and arranging several input pins between diffusion fins of the same diffusion type, the input pins can be separated in a more uniform manner over a larger area To reduce the winding congestion of the component. In addition, as shown in FIG. 8A, by selectively removing several gate electrode structures, as shown in area 8001, the diffusion fin layer can be used as a substantially horizontal winding layer to connect to non-adjacent Crystal or local interconnect. For example, in the region 8001, the diffusion fin 8003 is used as a horizontal wire-wound conductor.

According to several embodiments of the present invention, FIG. 8B shows a variation of FIG. 8A in which two different gate electrode pitches p1 and p2 are used. More specifically, in FIG. 8B, every other pair of adjacently arranged gate electrode structures are arranged according to a smaller pitch p2. In several embodiments, the larger gate electrode pitch p1 is about 80 nanometers (nm) and the smaller gate electrode pitch p2 is about 60 nm. It should be understood that several embodiments may utilize more than two gate electrode structure pitches within a specific element or block. Moreover, some embodiments may utilize a single gate electrode structure pitch within a specific element or block. In addition, it should be understood that any semiconductor device layer or part thereof may be formed in a manner similar to the gate electrode pitch described herein. For example, a local interconnect layer of a semiconductor device or a higher level interconnect layer or a portion thereof may include interconnects formed at more than one corresponding pitch in a manner similar to the gate electrode pitch described herein Line conduction structure.

In addition, the conductive structures or their parts in different layers (also called hierarchies) of the semiconductor device can be configured according to their respective pitch arrangements, where there is a certain relationship between the pitch arrangements of the conductive structures of different layers. For example, in some embodiments, the diffusion fins in the diffusion fin layer are configured according to a diffusion fin pitch arrangement that may include more than one diffusion fin pitch, and the metal in the met1 layer The layer 1 (met1) interconnect structure is configured according to a met1 pitch arrangement that can contain more than one met1 pitch, where more than one diffusion fin pitch is related to more than one met1 node with a rational number (x / y) Distance, where x and y are integers. In several embodiments, the relationship between the pitch of the diffusion fin and met1 pitch is defined by a rational number in the range of (1/4) to (4/1).

In addition, in some embodiments, the vertical local interconnect structure (liv) may be configured according to the vertical local interconnect pitch substantially equal to the gate electrode pitch. In several embodiments, the gate electrode pitch is less than 100 nanometers. In addition, in a manner similar to that described above regarding the relationship of the diffusion fin pitch to the met1 pitch, in some embodiments, the diffusion fin pitch arrangement can be related to the horizontal local interconnecting nodes by rational numbers (x / y) Distance arrangement, where x and y are integers. That is, more than one diffusion fin pitch can be related to more than one horizontal local interconnect pitch by rational numbers (x / y).

According to several embodiments of the present invention, FIG. 9A shows a layout exemplifying a standard element, in which a diffusion fin is used as an interconnect conductor. 9C shows a circuit diagram of the layout of FIG. 9A. The exemplary standard device layout of FIG. 9A is included in a single track, for example, in the gate electrode track 9001, including multiple gate electrode terminals. 9B shows the layout of FIG. 9A, in which three sets of cross-connected transistors are marked. The first group of cross-connected crystal systems is marked by the lines cc1a and cc1b. The second group of cross-connected crystal systems is marked by the lines cc2a and cc2b. The third group of cross-connected crystal systems is marked by lines cc3a and cc3b.

According to several embodiments of the present invention, FIG. 10 shows an exemplary standard device layout in which the gate electrode contact window is substantially disposed above the diffusion fins, not between the diffusion fins. The exemplary standard component layout of FIG. 10 also shows a variable width met1 local power supply structure. In the exemplary standard device layout of FIG. 10, the contact layer is vertically aligned above the diffusion fins, not between the diffusion fins. This method can share the adjacent edges between the diffusion fin structures without dummy diffusion fins, which provides a more efficient layout. It should be understood that the dummy diffusion fin is a diffusion fin where transistors are not formed. In addition, it should be understood that this method of vertically aligning the contact layer above the diffusion fin can change the vertical alignment relationship between the interconnection structure of met1 and the diffusion fin.

According to several embodiments of the present invention, FIG. 11 shows an exemplary element layout implementing a diffusion fin. In the illustrated layout of FIG. 11, the gate electrode layer includes the following features: l substantially a linear gate electrode structure, l three or more linear gate electrode structures on the gate electrode layer, of which two are dummy structures (dummy ), That is, the gate electrode hierarchical structure of the gate electrode that does not form a transistor, l Three or more gate electrode structures on the gate electrode layer, which have the same vertical size (length), that is, perpendicular to the diffusion The fins have the same length in the y-direction in the longitudinal direction (x-direction), l The gate electrode structure on the gate electrode layer is substantially evenly divided by a substantially equal longitudinal centerline to longitudinal centerline pitch Separation, l dummy gate electrode structure, which is shared with adjacent components on the left and / or right, and l dummy gate electrode structure, which is cut below the power rail of met1.

In the exemplary layout of FIG. 11, the diffusion fins include the following features: l According to the diffusion fins that are substantially evenly spaced at substantially equal pitches, the diffusion fins can be on a grid, in several embodiments the diffusion fins Pitch is less than 90 nm, more than one diffusion fin of each of lp type and n type. Figure 11 shows two n type diffusion fins and two p type diffusion fins, but other embodiments may include any number Any type of diffusion fins, l the same number of p-type and n-type diffusion fins, other embodiments may have p-type and n-type diffusion fins of different numbers, l delete more than one diffusion fin under the power rail l Delete more than one diffusion fin between the p-type and n-type segments, and l Each diffusion fin with substantially equal width and length.

In the illustrated layout of FIG. 11, the local interconnection includes the following features: l The gate electrode and the diffusion fin source / drain wiring are on different conductor layers, and these different conductor layers are isolated from each other, l A substantially linear conductor layer parallel to the gate electrode connected to the source and drain electrodes; in some embodiments, the same pitch as the gate layer; and in several embodiments, these linear conductor layers can be offset by half Gate pitch. l Local overlap and positive overlap of the diffusion fins.

In the illustrated layout of FIG. 11, the higher-level met1 interconnect layer includes the following features: l the gate conductor contact window between the p-type and n-type diffusion fins, l is divided in both directions (Gridded) contact window, l the contact window connects the local interconnect and the gate conductor to the upper metal layer, l substantially linear metal layer; the metal layer is based on the pitch; the metal layer is based on the same pitch as the diffusion fin With a pitch of half the pitch in the vertical direction, l input node and output node pins on the same layer, l wide power rails on the top and bottom edges, each of which is shared; power The rails are connected to the left and right by abutments, l output and input nodes at the highest metal level; contact windows arranged between p-type and n-type diffusion fins, and l at the top and The power rail contact window at the bottom shared with the adjacent components to the local interconnect.

According to several embodiments of the present invention, FIGS. 12A / B show a variation of the layout of FIG. 11 having a minimum width met1 power rail. FIG. 12B shows the same layout as FIG. 12A, where the layout is depicted in a merged form for clarity. The illustrated layout of FIG. 12A / B also has all met1 of the same width and the same pitch, which includes the power rails. In addition, in the layout of FIG. 12 / B, met1 is arranged at the same (y) direction position as the pitch of the diffusion fins.

According to several embodiments of the present invention, FIG. 13A / B shows a variation of the layout of FIG. 12A / B, which does not have contact windows from various local interconnects and gate electrode structures to met1. FIG. 13B shows the same layout as FIG. 13A, and the layout is depicted in a merged form for clarity. In this embodiment, the met1 system is formed to be directly connected to the local interconnect structure and the gate electrode structure. In addition, in other embodiments, either the local interconnect structure or the gate electrode structure, or both the local interconnect structure and the gate electrode structure, may be directly connected to met1.

According to several embodiments of the present invention, FIG. 14A / B shows a variation of the layout of FIG. 11, which has a minimum width met1 power rail, and all met1 structures, including power rails, have the same width and the same pitch. FIG. 14B shows the same layout as FIG. 14A, and the layout is depicted in a merged form for clarity.

According to several embodiments of the present invention, FIG. 15A / B shows a variation of the layout of FIG. 14A / B, which has a met1 winding structure configured to have a met1 structure at each (y) position. FIG. 15B shows the same layout as FIG. 15A, and the layout is depicted in a merged form for clarity.

According to several embodiments of the present invention, FIGS. 16A / B show a variation of the layout of FIG. 11, which has a gate electrode structure contact window disposed between p-type diffusion fins. FIG. 16B shows the same layout as FIG. 16A, and the layout is depicted in a merged form for clarity. The example layout of FIGS. 16A / B also shows the diffusion fins disposed under the power rail of met1 and connected to VSS / VDD. In addition, the diffusion fin VDD / VSS structure is shared with the upper and / or lower elements. For ease of description, the contact layer is not shown in the layout of FIGS. 16A / B.

According to several embodiments of the present invention, FIGS. 17A / B show exemplary element layouts that implement diffusion fins. FIG. 17B shows the same layout as FIG. 17A, and the layout is depicted in a merged form for clarity. In the illustrated layout of FIG. 17A / B, the gate electrode layer includes the following features: l a substantially linear gate electrode structure, l three or more linear structures on the gate electrode layer, at least two of which are dummy structures ( dummy), l the dummy structure on the gate electrode layer is the same vertical size (length), that is, the same length in the y direction perpendicular to the longitudinal direction (x direction) of the diffusion fin, l in the x direction A structure on the gate electrode layer that is substantially evenly spaced and / or equally pitched. The dummy structure is shared with the adjacent elements on the left and / or right. The dummy structure and the gate electrode structure are drawn as a single Wire, and then cut under the power rail and where needed; the gate electrode structure cut is drawn on different layers; the gate electrode layer with the final result of the cut is shown in Figure 17A / B, three segments The above gate electrode controls more than two p-type and n-type transistors, l multiple gate electrode structures at the same x position, each of which is connected to a different connection; and connected to two different Input connection.

In the exemplary layout of FIG. 17A / B, the diffusion fins include the following features: l Diffusion fins that are substantially evenly spaced according to a substantially equal pitch. The diffusion fins may be on a grid, and the diffusion fins have a pitch of In some embodiments, less than 90 nm, more than one diffusion fin for each of lp and n-type, l the same number of p-type and n-type diffusion fins, l the common diffusion fin under the power rail, l in p-type The diffusion fins can be deleted or not between the n-type segments; Figure 17A / B shows that all fins are present. L Each of the diffusion fins has substantially equal width and length, and the width of the diffusion fins is at Measured in the y direction, and the length of the diffuser fin is measured in the x direction, l The diffuser fin is drawn as a continuous line; individual cutting masks are drawn to divide the diffuser fin into segments; Figure 17A / B shows the segmented diffused fin section; it should be understood that, in some embodiments, the line ends of the diffused fin section can be formed or drawn on the diffused fin layer layout using a cutting mask.

In the illustrated layout of FIG. 17A / B, the local interconnection includes the following features: l The gate electrode and the diffusion fin source / drain wiring are on different conductor layers; these different conductor layers can be added during manufacturing Merge; l Source-drain wiring used for the substantially linear conductor layer parallel to the gate; in several embodiments, the same pitch as the gate layer; and in several embodiments, these linear conductor layers may Offset half gate pitch. l The positive, zero, or negative overlap of the local interconnects and the diffusion fins. l Direct connection of the local interconnects to the source / drain and gate electrode structures of the diffusion fins. l Shared local interconnection under the power rail Line; the partial interconnection line under the power rail can be deleted in several embodiments.

In the illustrated layout of FIG. 17A / B, the interconnect layer of the higher-level met1 includes the following features: l The gate electrode structure contact window between the diffusion fins, l The contact window is one or both of the x and y directions Gridded, l contact windows connect local interconnects and gate conductors to the upper metal layer, l the position of the metal layer can be fixed in one or both of the x and y directions, l on the same layer The output node and input node pins above, l the wide power rails at the top and bottom are shared; the power rail is connected to the left and right by the adjacent part; to the power rail contact window system of the local interconnect Commonly, the metal layer may have a bent portion. In some embodiments, the curved portion in the interconnection of the metal layer may be located in the center between adjacent diffusion fins. In addition, in some embodiments, the vertical section of the interconnection in the metal layer extending in the y direction may be aligned with the vertical local interconnection to follow the vertical local interconnection in the y direction and the vertical local interconnection Extend from above.

According to several embodiments of the present invention, FIG. 18A / B shows a variation of the layout of FIG. 17A / B, wherein the contact window is connected to the horizontal local interconnect, and wherein the horizontal local interconnect is directly connected to the vertical local interconnect. FIG. 18B shows the same layout as FIG. 18A, and the layout is depicted in a merged form for clarity. In the layout of FIG. 18A / B, the cuts on the diffusion fins, gate electrodes, and local interconnect layers are not shown.

According to several embodiments of the present invention, FIG. 19A / B shows a variation of the layout of FIG. 17A / B, where the power rail contact window to the local interconnect is not shared, and where there is no shared local interconnect under the power rail. FIG. 19B shows the same layout as FIG. 19A, and the layout is depicted in a merged form for clarity.

According to several embodiments of the present invention, FIG. 20A / B shows a variation of the layout of FIG. 19A / B, in which the diffusion fins are offset by half the diffusion fin pitch relative to the device boundary. FIG. 20B shows the same layout as FIG. 20A, and the layout is depicted in a merged form for clarity. The layout of FIG. 20A / B also includes the same diffusion fin position as met1. In addition, the diffusion fins are not shared at the top and bottom of the element. FIG. 20A / B also shows the contact window disposed on the gate electrode and the diffusion fin. Figures 20A / B also show the overlap of different diffusion fins / local interconnects. It should be understood that in the specific layout of FIG. 20A / B, although it is shown that the horizontal local interconnection lih and the vertical local interconnection liv overlap each other in the area 2001, the horizontal local interconnection lih and the vertical local interconnection liv In the region 2001, the department does not touch each other. This is also established in the area 2001 in FIG. 21A / B below. However, it should also be understood that in several other layouts, the horizontal local interconnect lih and the vertical local interconnect liv may be brought into contact with each other at positions where they cross each other.

According to some embodiments of the present invention, FIG. 21A / B shows a variation of the layout of FIG. 20A / B, which has a minimum width power rail and a negative vertical partial interconnection of diffusion fins overlapping. FIG. 21B shows the same layout as FIG. 21A, and the layout is depicted in a merged form for clarity.

According to some embodiments of the present invention, FIG. 22A / B shows a variation of the layout of FIG. 17A / B, which has a minimum width power rail, local interconnects and diffusion fins that are not shared under the power rail, and p-fin and n-fin Larger spacing between departments. FIG. 22B shows the same layout as FIG. 22A, and the layout is depicted in a merged form for clarity.

According to several embodiments of the present invention, FIG. 23A / B shows a variation of the layout of FIG. 17A / B. FIG. 23B shows the same layout as FIG. 23A, and the layout is depicted in a merged form for clarity. The layout of Figure 23A / B has the following features: l Unidirectional metal layer interconnection structure, that is, linear metal layer interconnection structure, l No shared local interconnection or fin under the power rail, l In the highest metal One input pin on the layer, and another input pin and output pin on the metal layer below, l The gate electrode contact window is separated from the local interconnect.

In addition, FIGS. 23A / B show the diffusion fins before being cut on the left and right edges.

According to several embodiments of the present invention, FIG. 24A / B shows a variation of the layout of FIG. 23A / B. FIG. 24B shows the same layout as FIG. 24A, and the layout is depicted in a merged form for clarity. The layout of FIG. 24A / B has the following features: l The pitch of the diffusion fin is smaller than the pitch of the metal layer; the pitch of the diffusion fin is half of the pitch of the metal layer, l The gate electrode and local area shown between the diffusion fins Wire cutting; an alternative implementation may have a cut above the diffusion fin cut; this will reduce the number of diffusion fins in more than one transistor, l an input pin on the highest metal layer, the metal below Another input pin and output pin on the layer, l is greater than the minimum spacing between the p-type and n-type diffusion fins; delete more than one diffusion fin between the p-type and n-type diffusion fin sections, l the gate electrode contact window disposed on the diffusion fin, l the local interconnect contact window disposed on the diffusion fin, and l the vertical met2 within the device has a different offset in the x direction.

According to several embodiments of the present invention, FIGS. 25A / B show a variation of the layout of FIG. 23A / B, in which the elements are doubled in height. FIG. 25B shows the same layout as FIG. 25A, and the layout is depicted in a merged form for clarity. The layout of FIG. 25A / B includes twice the total number of diffusion fins in the layout of FIG. 23A / B. The diffusion fin cutting is shown in the layout of FIGS. 25A / B.

According to several embodiments of the present invention, FIG. 26A / B shows an exemplary element layout for implementing a diffusion fin. FIG. 26B shows the same layout as FIG. 26A, and the layout is depicted in a merged form for clarity. In the illustrated layout of FIG. 26A / B, the gate electrode layer includes the following features: l a substantially linear gate electrode structure, l three or more linear structures on the gate electrode layer, at least two of which are dummy structures, l The dummy structure on the gate electrode layer has the same size, l the structure on the gate electrode layer is substantially evenly spaced and / or equal pitched in the x direction, l the dummy structure is on the left and / Or the adjacent components on the right are shared, l cut the dummy structure under the power rail, l control a single gate electrode structure of more than two p-type and n-type transistors, and be separated after the manufacturing process to form more than two Different gate electrodes, such as those depicted in gate electrode structures 2601 and 2603, l The gate electrodes at the same x position are connected to more than two different connections, to more than two different input connections, such as by connecting The gate electrode structure 2601 to the input connection 2605 and the one depicted by the gate electrode structure 2603 connected to the input connection 2607, l more than two dummy segments at the same x position.

In the exemplary layout of FIG. 26A / B, the diffusion fins include the following features: l According to the diffusion fins that are substantially evenly spaced apart at substantially equal pitches, the diffusion fins may be on a grid, and the diffusion fins have a pitch of In some embodiments, less than 90 nm, more than one diffusion fin of each of lp and n-type, l the same number of p-type and n-type diffusion fins, l delete more than one diffusion fin under the power rail, l in No diffusion fins are deleted between the p-type and n-type segments, l each diffusion fin has substantially equal width and length, and l the p-type diffusion fin is arranged between the n-type diffusion fins, and vice versa .

In the illustrated layout of FIG. 26A / B, the local interconnection includes the following features: l The gate electrode and the source / drain wiring of the diffusion fin are on different conductor layers; these different conductor layers are separated from each other, l A substantially linear conductor layer parallel to the gate used for the source-drain wiring; in several embodiments, with the same pitch as the gate layer; and in several embodiments, this linear conductor layer can be offset The half-gate pitch, and the partial overlap of the local interconnect and the diffusion fin are positively overlapping.

In the illustrated layout of FIG. 26A / B, the higher-level met1 interconnect layer includes the following features: l Gate electrode structure contact window between the diffusion fins, l The contact window is in one of the x and y directions or The two are divided, l the contact window connects the local interconnect and the gate conductor to the upper metal layer, l the substantially linear conductor on the output node, l the output node and input node pins on different layers, l The power rail in the middle is opposite to the power rails at the top and bottom; the top and bottom power rails are shared; all power rails are connected to the left and right by the adjacent part, and l the output node on the highest metal layer .

According to several embodiments of the present invention, FIG. 27A / B shows a variation of the layout of FIG. 26A / B. FIG. 27B shows the same layout as FIG. 27A, and the layout is depicted in a merged form for clarity. The layout of FIG. 27A / B includes the following features: l The gate electrode is drawn to have a cut layer, for example, a cut layer including a cut shape portion 2701, l Two gate conductor segments at the same x position, each of which is connected to a Different connections, the gate conductor segments are each connected to an input connection, the gate conductor segments each control a p-type and an n-type transistor constructed with multiple fins, such as gate conductors 2703 and 2705, and One input pin on the highest metal layer, another input pin and output pin on the lower metal layer.

According to several embodiments of the present invention, FIGS. 28A / B show exemplary element layouts that implement diffusion fins. FIG. 28B shows the same layout as FIG. 28A, and the layout is depicted in a merged form for clarity. In the exemplary layout of FIG. 28A / B, the gate electrode layer includes the following features: l a substantially linear gate electrode structure, l three or more linear structures on the gate electrode layer, at least two of which are dummy structures, l Three or more gate electrode structures have the same size, l The structures on the gate electrode layer are substantially evenly spaced and / or equally pitched in the x direction, l The dummy structure is on the left And / or the adjacent components on the right are shared, l the dummy structure is cut under the power rail,

It should be understood that any of the illustrations shown here, including the illustrated layout of FIGS. 28A / B, may have a type 1 diffusion fin defined as a p-type diffusion fin, and an n-type definition depending on the particular implementation embodiment The type 2 diffusion fin of the diffusion fin, or may have a type 1 diffusion fin defined as an n-type diffusion fin, and a type 2 diffusion fin defined as a p-type diffusion fin. In the illustrated layout of FIG. 28A / B, the diffusion fins include the following features: l Diffusion fins that are substantially evenly spaced according to a substantially equal pitch, the diffusion fins can be on a grid, in several embodiments The pitch of the intermediate diffusion fin is less than 90 nm, more than one diffusion fin of each of lp and n-type, l different number of p-type and n-type diffusion fins, l more than one diffusion fin under the power rail Delete, l delete more than one diffusion fin between the p-type and n-type segments, l each diffusion fin has substantially equal width and length.

In the illustrated layout of FIG. 28A / B, the local interconnection includes the following features: l The gate electrode and the diffusion fin source / drain wiring are directly from a conductive layer, l The source drain wiring is parallel to The substantially linear conductive layer of the gate; in some embodiments, the same pitch as the gate layer; and in several embodiments, the linear conductor layer can be offset by half the gate pitch, l partially interconnected Zero or negative overlap with the diffusion fin and gate electrode structure. L The local interconnect can be constructed in two steps, firstly the vertical local interconnect structure, then the horizontal local interconnect structure; each step creates a Group of linear, unidirectional local interconnect structures, and l or, two separate local interconnect layers, namely a vertical local interconnect layer and a horizontal local interconnect layer.

In the illustrated layout of FIG. 28A / B, the higher-level met1 interconnect layer includes the following technical features: l The diffusion fin can be disposed under the power rail l The contact window is divided in one or both of the x and y directions Gridded, l the contact window connects all local interconnects to the upper metal layer, and l the contact window can be placed at any location.

According to several embodiments of the present invention, FIG. 29A / B shows a variation of the layout of FIG. 28A / B, in which there is no local interconnect structure between the gate electrode structures of two n-type transistors. FIG. 29B shows the same layout as FIG. 29A, and the layout is depicted in a merged form for clarity.

According to several embodiments of the present invention, FIGS. 30A / B show exemplary element layouts implementing diffusion fins. FIG. 30B shows the same layout as FIG. 30A, and the layout is depicted in a merged form for clarity. In the exemplary layout of FIG. 30A / B, the gate electrode layer includes the following features: l a substantially linear gate electrode structure, l three or more linear structures on the gate electrode layer, at least two of which are dummy structures, l More than three gate electrode structures have the same size, l The structures on the gate electrode layer are substantially evenly spaced and / or equally pitched in the x direction, l The dummy structure is on the left and / or right The adjacent components of the square are shared, and the dummy structure is cut under the power rail.

In the exemplary layout of FIG. 30A / B, the diffusion fins include the following features: l According to the diffusion fins that are substantially evenly spaced apart at substantially equal pitches, the diffusion fins can be diffused on a grid in several embodiments Fin pitch is less than 90 nm, one or more diffuse fins of lp and n-type, l The same number of p-type and n-type diffuse fins, l Delete more than one diffuse fin under the power rail, l More than one diffusion fin is deleted between the p-type and n-type segments, l Each of the diffusion fins has substantially equal width and length.

In the illustrated layout of FIG. 30A / B, the local interconnection includes the following features: l The gate electrode and the source / drain wiring of the diffusion fin are directly from a conductor layer, l The source-drain wiring is parallel to the gate The substantially linear conductor layer of the pole; in several embodiments, with the same pitch as the gate layer; and in several embodiments, this linear conductor layer can be offset by half the gate pitch, l partially interconnected Zero or negative overlap with the diffusion fin and gate electrode structure. L The local interconnect can be established in two steps, firstly the vertical local interconnect structure, then the horizontal local interconnect structure; each step establishes a set of lines, Unidirectional local interconnection structure, and l In some embodiments, vertical and horizontal local interconnection structures can be formed to cross and connect with each other, thereby forming a two-dimensionally varying local interconnection structure, that is, having a curvature Local interconnect structure, or alternatively, two independent local interconnect layers—a vertical local interconnect layer and a horizontal local interconnect layer.

In the exemplary layout of FIG. 30A / B, the interconnect layer of the higher-level met1 includes the following features: l The diffusion fin can be disposed under the power rail l The contact window is divided in one or both of the x and y directions Gridded, l configure the met1 interconnect structure according to the same pitch as the gate electrode structure, l the contact window connects all local interconnects to the upper metal layer, and l can configure the contact window at any position.

According to several embodiments of the present invention, FIG. 31A shows an exemplary sdff device layout in which the gate electrode and the local interconnect line end gap are located at the substantial center between the diffusion fins. In FIG. 31A, the gate electrode wire end gap is circled. FIG. 31B shows the example sdff device layout of FIG. 31A, in which a partial inner wire end gap located at the substantially center between the diffusion fins is circled. Based on FIGS. 31A to 31B, it should be understood that a cell library structure may be generated in which all gate electrodes and vertical interconnect line end gaps are located substantially in the center between the diffusion fins. According to several embodiments of the present invention, FIG. 31C shows the example sdff device layout of FIGS. 31A and 31B labeled with the region 3105 between two adjacent gate electrode structures, in which the ends of the diffusion fins overlap each other in the x direction.

According to some embodiments of the present invention, FIGS. 32-34 show three examples of a part of the circuit layout of a standard device. FIG. 32 shows an example layout in which all contact layer structures are arranged between diffusion fins. 33 and 34 show an exemplary layout in which all contact layer structures are arranged on the diffusion fins. In the example of FIG. 32, the gate electrode line end gap is substantially located at the center above the diffusion fins in some examples, as indicated by circle 3201, and in some examples, the gate electrode line end gap is substantially located in The center between the diffusion fins is indicated by circle 3203. By using a device structure in which all contact layer structures are arranged above the diffusion fins, all gate electrode terminal gaps can be located substantially in the center between the diffusion fins, as indicated by circle 3301 in FIGS. 33 and 34 Mark. An advantage here is that the gate electrode end gaps all have a fixed pitch. From a manufacturing point of view, it does not matter whether the gate electrode line end gap is on the center of the diffusion fins or between the diffusion fins. However, it is important that the gap between the gate electrode ends is not mixed, as shown in the example of FIG. 32. Making the gate electrode line gaps all have the same pitch will cause the gate electrode manufacturing process to be less expensive, more reliable, or satisfy both.

35A-69A show various device layouts showing examples of different ways in which cross-connected transistor configurations can be implemented using fin field effect transistors. The cross-connect layout of Figures 35A-69A is shown in the background of the two-input multiplexer circuit (MUX2). According to several embodiments of the present invention, FIG. 35C shows a circuit diagram of the layout of FIGS. 35A / B to 47A / B and 63A / B to 67A / B. According to several embodiments of the present invention, FIG. 48C shows a circuit diagram of the layout of FIGS. 48A / B to 58A / B. According to several embodiments of the present invention, FIG. 59C shows a circuit diagram of the layout of FIG. 59A / B. According to several embodiments of the present invention, FIG. 60C shows a circuit diagram of the layout of FIGS. 60A / B to 62A / B and 68A / B to 69A / B. According to some embodiments of the present invention, FIG. 71C shows a circuit diagram of the layout of FIGS. 71A / B and 77A / B. According to several embodiments of the present invention, FIG. 72C shows a circuit diagram of the layout of FIGS. 72A / B to 76A / B. Transistors on the left and right edges are added to the cross connection to achieve the MUX2 function. For other functions with cross-connect circuits, these may be different. FIGS. 35B-69B show the same layouts as those in FIGS. 35A-69A, respectively. The layouts are depicted in a merged form for clarity, and circuit icons based on the component layouts show the nodes of the circuit. In addition, the cross-connect transistor wiring in FIGS. 35A-69A is marked with lines cc1 and cc2.

Figures 35A / B to 47A / B and 63A / B to 67A / B show a cross-connect transistor configuration with transmission gates on both logic paths, which requires all internal nodes to have a connection between p-type and n-type. Figures 48A / B to 57A / B show the configuration of a cross-connected transistor with a transmission gate on the logic path that uses a larger transistor, and a tri-state gate on the other path. The tri-state gate does not require wiring between p-type diffusion and n-type diffusion on internal nodes.

Figures 58A / B to 59A / B show a cross-connect transistor configuration with a transmission gate on a logic path that uses a smaller transistor, and a tri-state gate on other paths. The tri-state gate does not require wiring between p-type diffusion and n-type diffusion on internal nodes.

Figures 60A / B to 62A / B and 68A / B to 69A / B show cross-connect transistor configurations with tri-state gates on both logic paths.

63A / B to 69A / B show device layouts having the number of p-type diffusion fins equal to the number of n-type diffusion fins. Other FIGS. 35A / B to 62A / B, some of which show device layouts having a number of p-type diffusion fins that is not equal to the number of n-type diffusion fins.

Figure 40A / B shows the layout of components using tighter spacing between horizontal / vertical local interconnect structures. 37A / B, 45A / B, and 49A / B show examples of device layouts that use a larger spacing between diffusion fins. Figures 63A / B to 69A / B show examples of device layouts using tighter spacing between diffusion fins. 43A / B and 44A / B show examples of device layouts using a diffusion fin as a wiring.

35A / B to 41A / B, 48A / B to 65A / B, and 68A / B to 69A / B show examples of device layouts using dense gate electrode structure implementations without separate gates. 42A / B to 47A / B and 66A / B to 67A / B show examples of device layouts using separate gate implementations with less wiring and larger transistor size.

Figures 35A / B to 69A / B show examples of component layouts, which show several different wiring examples for various component layouts. Figures 35A / B to 69A / B show examples of display element layouts showing the use of fully filled gate electrode layers, including extensions of gate electrode end caps and the use of dummy structures that may be within the gate electrode layer. Several device layouts shown in FIGS. 35A / B to 69A / B show the structure of the dummy gate electrode layer without cutting on the top and bottom of the device, that is, before the cutting mask operation during the manufacturing process. Several component layouts, such as FIGS. 53A / B to 55A / B and 66A / B, show exemplary component layouts in which the power bus is deleted.

The cross-connect transistor structure of FIGS. 35A / B to 69A / B includes structures formed on layers and combinations of layers, and many of the above-mentioned element layout features can be applied independently of each other. It should be understood that the device layout of FIGS. 35A / B to 69A / B shows an example that can be implemented using a fin field effect transistor cross-connected transistor structure, and does not represent all inclusive sets of possible device layout configurations. Any of the features shown in the various device layout examples of FIGS. 35A / B to 69A / B can be combined to produce additional device layouts.

The technology with insufficient optical resolution to directly analyze the line pattern will use several types of pitch division. Pitch division can be self-aligned through multiple exposure steps or using compartments at achievable resolution. For example, for the ArF excimer laser scanner using a water immersion last lens and a portion of the exposed wafer, the optical resolution is limited to ~ 40 nm. This corresponds to an effective numerical aperture of 1.35 and a k1 value of 0.28 at a wavelength of 193 nm. For the diffusion fin layer and gate electrode layer and other layers formed by pitch division (such as spacer double patterning, spacer quad patterning, multiple exposure lithography-etching-lithography-etching, etc.), Even if the layout is carried out with a uniform pitch (longitudinal centerline to longitudinal centerline pitch) for the conductive structure (that is, for the isolines), the conductive structure may slightly deviate from the target due to processing variations after manufacturing, making the final crystal There are multiple (eg, two, four, etc.) pitches on the circle.

Can be used with self-aligned spacer method or multiple lithography exposure method to apply pitch division multiple times, such as two-pitch division (pitch-division-by-2), four-pitch division (pitch-division-by -4). The division at four pitches has been recorded to achieve a line / space of about 11 nm. A limitation of the pitch division is that the resulting line pattern can have a slightly different pitch within the pattern. For splitting by two pitches, this means that the two-line group will have a pitch, the next two-line group may have a slightly different pitch, and the next two-line group will have the same pitch as the first group Set equal pitches and so on. The result on the finished wafer will be the line intended to have a uniform, fixed pitch, but these will eventually have a pitch of two or four or more. For self-aligned spacers, the original core line pattern will be drawn at a fixed, uniform pitch. For multiple exposures, each of the exposures will have lines drawn at a uniform fixed pitch. The non-uniform pitch introduced by the pitch division process may be in the order of 10% or less of the final pitch. For example, for a final target pitch of 50 nm, the pitch of each of the two line groups may be less than 5 nm. Restricted gate hierarchy layout structure

As discussed above, various circuit layouts including fin field effect transistors can be implemented within a limited gate hierarchy layout structure. For the gate hierarchy, several parallel virtual lines are defined to extend through the layout. These parallel virtual lines are called gate electrode tracks because they are used to indicate the configuration of the gate electrodes of various transistors within the layout. In several embodiments, the parallel virtual lines forming the gate electrode tracks are defined by the vertical spacing therebetween that is equal to the specified gate electrode pitch. Therefore, the arrangement of the gate electrode sections on the gate electrode track corresponds to the specified gate electrode pitch. In another embodiment, the gate electrode tracks may be separated by a variable pitch greater than or equal to a specified gate electrode pitch.

According to several embodiments of the present invention, FIG. 70A shows an example of gate electrode tracks 70-1A to 70-1E defined within a restricted gate hierarchy layout structure. The gate electrode tracks 70-1A to 70-1E are formed by parallel imaginary lines extending through the gate hierarchy layout of the wafer, with a vertical pitch equal to a specified gate electrode pitch 70-3 in between.

Within the restricted gate hierarchy layout structure, the gate hierarchy feature layout channel is defined with respect to a specific gate electrode track to extend between the gate electrode tracks adjacent to the specific gate electrode track. For example, the gate-level feature layout channels 70-5A to 70-5E are defined with respect to the gate electrode tracks 70-1A to 70-1E, respectively. It should be understood that each gate electrode track has a corresponding gate hierarchy feature layout channel. In addition, for gate electrode tracks that are configured to be adjacent to the edge of a specified layout space (eg, adjacent to the device boundary), the corresponding gate-level feature layout channel extension results as a virtual gate outside the specified layout space The electrode tracks are as described in the gate hierarchy feature layout channels 70-5A and 70-5E. It should be further understood that each gate level feature layout channel is defined to extend along the entire length of its corresponding gate electrode track. Therefore, each gate-level feature layout channel is defined to extend through the gate-level layout within a portion of the chip associated with the gate-level layout.

In a restricted gate hierarchy layout structure, the gate hierarchy features associated with a specific gate electrode track are defined within the gate hierarchy feature layout channel associated with the specific gate electrode track. A continuous gate hierarchy feature may include both the part defining the gate electrode of a transistor (such as the fin field effect transistor disclosed herein) and the part not defining the gate electrode of a transistor. Therefore, a continuous gate level feature can extend above both a diffusion area (ie, diffusion fin) and a lower wafer level dielectric area.

In some embodiments, the portions of the gate level feature that form the gate electrode of a transistor are configured to be substantially in the center of a particular gate electrode track. In addition, in this embodiment, the portion of the gate-level feature that does not form the gate electrode of a transistor can be configured within the gate-level feature layout channel associated with the particular gate track. Therefore, a specific gate level feature can be defined substantially anywhere within a specific gate level feature layout channel, as long as the gate electrode portion of the specific gate level feature is in the gate corresponding to the specific gate level feature The center of the pole electrode track, and as long as the specific gate level feature meets the design rule spacing relative to other gate level features in the adjacent gate level layout channel. In addition, physical contact between gate-level features defined in the gate-level feature channels associated with adjacent gate electrode tracks is not allowed.

According to several embodiments of the present invention, FIG. 70B shows the exemplary restricted gate hierarchy layout structure of FIG. 70A, which has several exemplary gate hierarchy features 7001-7008 defined therein. The gate hierarchy feature 7001 is defined within the gate hierarchy feature layout channel 70-5A associated with the gate electrode track 70-1A. The gate electrode portion of the gate level feature 7001 is located substantially at the center of the gate electrode track 70-1A. In addition, the non-gate electrode portion of the gate-level feature 7001 maintains the design rule spacing requirement, wherein the gate-level features 7002 and 7003 are defined within the adjacent gate-level feature layout channels 70-5B. Similarly, gate-level features 7002-7008 are defined within their respective gate-level feature layout channels, and their gate electrode portions are centered on the gate electrode tracks corresponding to their respective gate-level feature layout channels. In addition, it should be understood that each of the gate-level features 7002-7008 maintains the design rule spacing requirement, where the gate-level features are defined within the adjacent gate-level feature layout channels and avoid contact with adjacent gates The physical contact of any additional gate hierarchical features defined within the hierarchical feature layout channel.

A gate electrode corresponds to a part of a respective gate level feature extending above a diffusion structure (ie, above the diffusion fin), wherein the respective gate level feature is defined as a gate level as a whole Feature layout within the channel. Without physical contact with another gate-level feature defined within the adjacent gate-level feature layout channel, each gate-level feature is defined within its gate-level feature layout channel. As illustrated in the example gate-level feature layout channels 70-5A to 70-5E of FIG. 70B, each gate-level feature layout channel is associated with a specific gate electrode track and corresponds to a layout area along the layout area The specific gate electrode track extends vertically in each opposite direction from the specific gate electrode track to an adjacent gate electrode track or any one of a virtual gate electrode track outside the layout boundary, the closest of which is the closest Outside extension.

Several gate level features may have more than one contact head portion, which is defined at any number of locations along its length. The contact head portion of a particular gate-level feature is defined as a gate-level feature section having a height and width of sufficient size to accommodate the gate contact window structure. In this example, "width" is defined across the substrate in a direction perpendicular to the gate electrode track of the specific gate level feature, and "height" is defined as the gate parallel to the specific gate level feature The direction of the electrode track is defined across the substrate. Depending on the orientation of the gate-level features within an element, the gate-level feature width and height may or may not correspond to the element width W and element height H. It should be understood that the contact head of a gate level feature, when viewed from above, can be defined by virtually any layout shape, which includes a square or a rectangle. In addition, depending on layout requirements and circuit design, a particular contact head portion of a gate hierarchy feature may or may not have a gate contact window defined above it.

A gate hierarchy defined in several embodiments disclosed herein is defined as a restricted gate hierarchy, as described above. Some of these gate level features form gate electrodes of transistor devices. The other of these gate level features may form a conductive section extending between two points within the gate level. In addition, others of these gate-level features can operate non-functionally with respect to integrated circuits. It should be understood that, regardless of the function, without physical contact with other gate-level features defined by the adjacent gate-level feature layout channels, each gate-level feature is defined as its own gate-level feature layout The gate level extends through the channel.

In several embodiments, the gate hierarchy feature is defined to provide a limited number of controlled layout shapes to shape lithography interactions, which can be accurately predicted and optimized during manufacturing and design. In this embodiment, the gate hierarchy feature is defined to avoid the layout shape-to-shape spatial relationship that would introduce adverse lithographic interactions within the layout. The adverse lithographic interactions cannot be accurately predicted and have no High possibility to mitigate. However, it should be understood that when the corresponding lithographic interaction is predictable and controllable, changes in the direction of the gate hierarchy feature within the gate hierarchy layout channel of the gate hierarchy feature are acceptable.

It should be understood that regardless of the function, each gate level feature is defined as a gate level feature that does not follow a specific gate electrode track is constructed from different gates directly connected within the gate level to Another gate level feature defined by the pole electrode track does not utilize the non-gate level feature. In addition, the connections between the gate level features within different gate level layout channels associated with different gate electrode tracks are made to pass through more than one Gate level features, that is, pass through one or more interconnect levels above the gate level, or are made by local interconnect features at or below the gate level.

According to several embodiments of the present invention, FIGS. 71A / B to 77A / B show several exemplary SDFF circuit layouts that utilize cross-connect circuit structures based on both transmission and tri-state gates. According to several embodiments of the present invention, FIG. 71C shows circuit diagrams of FIGS. 71A / B and 77A / B. According to several embodiments of the present invention, FIG. 72C shows the circuit diagrams of FIGS. 73A / B to 76A / B. 71B-77B show the same layouts as in FIGS. 71A-77A, respectively, where the layout is depicted in a merged manner for clarity, and the nodes of the circuit are marked based on the component layout circuit diagram. The illustrated SDFF circuit layouts in Figures 71A / B to 77A / B include the following features: 1. Gate conductors: a. Substantially evenly spaced gate conductors. b. Using the same gate conductor gap formed by the cutting mask, it is combined with the large gate conductor gap to avoid local interconnection, or if there is enough space to allow a larger gate conductor without cutting Line end gap. c. In some examples, several gate conduction systems are used as wiring to reduce the utilization rate of the metal layer, that is, to reduce the utilization rate of the interconnection of higher levels. 2. Diffusion fins: a. Diffusion fins that are substantially evenly spaced apart. b. Remove the diffusion fins between the p-type and n-type and the top and bottom element edges. c. The relationship between the width of the diffusion fins and the pitch may vary, or may have a substantially equal relationship, as depicted in the examples of FIGS. 71A / B to 77A / B. 3. Local interconnection: a. Local interconnection structure can be directly connected to the diffuser fin and gate conductor. b. The local interconnect structure can be connected to the metal layer 1 (met1 or M1) via a contact layer. c. Horizontal and vertical local interconnect structures, such as those shown in Figure 76A / B for illustration purposes, can be manufactured using separate design layers, that is, using separate mask layers. d. The horizontal and vertical local interconnect structures can be on the same layer, that is, on the same mask layer, as shown in the examples of Figures 71A / B to 75A / B and 77A / B. In addition, during manufacturing, the horizontal and vertical local interconnect structures can be fabricated in two different steps or in a single step. e. The local interconnect structure may have positive, zero, or negative overlap with the diffusion fin and gate conductor. f. The vertical partial interconnection may have a pitch similar to that of the gate conductor, and have a half-pitch offset from the gate conductor. 4. Contact window: a. The contact window can be defined to connect the local interconnect structure to the metal layer 1 (met1 or M1). b. The local interconnect structure may have positive, zero, or negative overlap on the contact window. c. The metal layer 1 (met1 or M1) may have a positive, zero, or negative overlap on the contact window. 5. Metal layer 2 (met2 or M2) a. In several embodiments, the structure of the metal layer 2 may be unidirectional, that is, linear. b. The metal layer 2 structure can extend in the horizontal (x) and / or vertical (y) direction.

The example SDFF circuit layout of FIG. 71A / B shows the following features it contains: l The metal layer 2 system is not used for internal wiring. l Metal layer 2 is used for power rails. l Use three-state and transmission gate to cross connect transistor structure. l The partial interconnection structure extends in the horizontal (x) and vertical (y) directions. l Several gate conduction systems are used for wiring, and the gate electrode of a transistor is not formed. l Configure gate conductor cutting in various positions and combinations. l The gate conductor cutting is consistent in size. l The gate conductor layer is completely filled, that is, at least one gate conductor system is arranged at each available gate conductor pitch position in the device.

The example SDFF circuit layout shown in FIG. 72A / B shows the following features included: The metal layer 2 structure is used for internal wiring in the vertical (y) direction. l A denser circuit layout than the example in Figure 71A / B. l Use the cross-connect transistor structure of both tri-state and transmission gate. l The gate conductor layer is completely filled, that is, at least one gate conductor system is arranged at each available pitch position of the gate conductor in the element. l Show gate conductor cutting. l Use substantially consistent gate conductor cutting in various combinations and / or locations to optimize the layout.

The example SDFF circuit layout of FIGS. 73A / B shows a version of the SDFF circuit that uses both the gate conductor and the metal layer 2 for vertical (y direction) wiring. The example SDFF circuit layout of FIGS. 74A / B shows a version of the SDFF circuit that uses a horizontally oriented (ie, in the x direction) metal layer 2 structure for internal wiring. The exemplary SDFF circuit layout of FIG. 75A / B shows an alternative version of the SDFF circuit, which also uses a horizontally oriented (ie, in the x direction) metal layer 2 structure for internal wiring. The example SDFF circuit layout of FIGS. 76A / B shows a variation of the layout of FIG. 72A / B, in which horizontal partial interconnects and vertical partial interconnects are used as independent conductors to allow the removal of the inner metal layer 2 conductors. 77A / B illustrates the SDFF layout of the SDFF circuit layout display section, which describes an alternative way to define the circuit structure to minimize the use of the metal layer 2 and maximize the transistor density.

It should be understood that, based on the circuit layout and the description provided here, more than one of the following features may be used in several embodiments: l Commonly aligned and the spacing distance between the ends of the diffusion fins in adjacent configurations (ie, diffusion fins) The cutting distance) can be smaller than the gate electrode pitch. L The vertical local interconnect structure can overlap with a diffusion fin (which is horizontally oriented) on one edge of the diffusion fin (horizontally oriented edge); In this case, several cuts (in a cutting mask) used to separate the vertical local interconnect structure can be defined as contacting or overlapping with a diffusion fin. L A horizontal local interconnect structure can be located at the gate electrode One edge of the structure (vertically oriented edge) overlaps with a gate electrode structure (which is vertically oriented). L The size of the gate electrode cover (that is, the distance that the gate electrode structure extends beyond the diffusion fin below) can be less than one The size of the above diffusion fin pitch, or the size smaller than the average diffusion fin pitch, l The distance between the ends of the gate electrode structure that are commonly aligned and adjacently arranged (ie, the gate Electrode structure cutting distance) can be less than or equal to the size of more than one diffusion fin pitch, or less than the average diffusion fin pitch size, l the longitudinal centerline spacing between adjacent n-type and p-type diffusion fins The distance (as measured in the direction perpendicular to the diffusion fins) can be defined as an integer multiple of more than one diffusion fin pitch, or an integer multiple of the average diffusion fin pitch.

In an exemplary embodiment, the semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor has a source region and a drain region within a first diffusion fin. The first diffusion fin is constructed to protrude from a surface of the substrate. The first diffusion fin is constructed to extend longitudinally in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin. The second transistor has a source region and a drain region within a second diffusion fin. The second diffusion fin is configured to protrude from the surface of the substrate. The second diffusion fin is constructed to extend longitudinally in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin. The second diffusion fin is configured to be adjacent to the first diffusion fin and spaced apart from the first diffusion fin. In addition, either the first end or the second end of the second diffusion fin is disposed between the first end and the second end of the first diffusion fin in the first direction between.

The above-mentioned first and second transistors may be located at different positions in the second direction. In addition, each of the first and second transistors may be a three-dimensional gated transistor.

The first transistor includes a first linear gate electrode structure. When viewed from above the substrate, the first linear gate electrode structure extends longitudinally in a second direction perpendicular to the first direction. The second transistor includes a second linear gate electrode structure. When viewed from above the substrate, the second linear gate electrode structure extends longitudinally in the second direction perpendicular to the first direction. At least one of the first end and the second end of the first diffusion fin may be disposed between the first and second linear gate electrode structures in the first direction. In addition, at least one of the first and second end portions of the second diffusion fin may be disposed between the first and second linear gate electrode structures in the first direction. The first linear gate electrode structure is disposed adjacent to and separated from the second linear gate electrode structure.

The semiconductor device may also include a linear partial interconnect structure that extends in the second direction and is disposed between the first and second linear gate electrode structures. The linear partial interconnection structure may be located substantially in the center between the first and second linear gate electrode structures in the first direction. The linear partial interconnect structure can be connected to more than one of the first and second diffusion fins.

The semiconductor device may also include a linear partial interconnect structure that extends in the first direction and is disposed between the first and second diffusion fins. The linear partial interconnection structure may be located at a substantial center between the first and second diffusion fins in the second direction. In addition, the linear partial interconnect structure can be connected to more than one of the first and second gate electrode structures.

The above-mentioned linear partial interconnection structure extending in the first direction may be referred to as a first linear partial interconnection structure. The semiconductor device may also include a second linear partial interconnect structure that extends in the second direction and is disposed between the first and second linear gate electrode structures. The second linear partial interconnection structure may be located substantially in the center between the first and second linear gate electrode structures in the first direction. In addition, the second linear partial interconnection structure may be connected to more than one of the first diffusion fin and the second diffusion fin. In addition, in some embodiments, the first linear local interconnect structure may be a first linear section of a two-dimensionally changing non-linear local interconnect structure, and the second linear local interconnect structure may be the A second linear section of a two-dimensionally changing non-linear local interconnect structure. Furthermore, in several examples, the first and second linear partial interconnecting structures may be connected to each other.

The semiconductor device may also include a contact structure disposed between the first and second diffusion fins. In several embodiments, the contact structure may be located substantially in the center between the first and second diffusion fins. In some embodiments, the contact structure may be connected to either the first gate electrode structure or the second gate electrode structure.

The semiconductor device may also include a contact structure disposed between the first and second gate electrode structures. In several embodiments, the contact structure may be located substantially in the center between the first and second gate electrode structures. In addition, in some embodiments, the semiconductor device may include a conductive interconnect structure disposed between the first and second diffusion fins in the second direction, wherein the contact structure is connected to the conductive interconnect structure . In some embodiments, the conductive interconnect structure is a lowest-level interconnect structure of the non-diffusion fin that extends in the first direction.

The semiconductor device may also include a conductive interconnect structure disposed between the first and second diffusion fins in the first direction, wherein the contact structure is connected to a conductive interconnect structure. In some embodiments, the conductive interconnect structure is a higher-level interconnect structure.

The semiconductor device may also include more than one interconnect structure, wherein several of the more than one interconnect structure include more than one interconnect section extending in the first direction. In some embodiments, several of the one or more interconnect sections extending in the first direction are disposed between the first and second diffusion fins. In addition, in some embodiments, some of the one or more interconnection segments extending in the first direction are disposed above either the first diffusion fin or the second diffusion fin. In some embodiments, the one or more inner line segments extending in the first direction are configured according to a second direction inner line pitch, the pitch is more than one in the second direction Measured between the centerlines of the first and second orientations of the inner line segments.

In some embodiments, the first and second diffusion fins may be configured according to a diffusion fin pitch, the pitch being the respective first of the first and second diffusion fins in the second direction Measured between the centerlines oriented in the direction, wherein the pitch of the interconnection line in the second direction is a rational multiple of the pitch of the diffusion fin, the rational multiple is defined as an integer ratio.

In some embodiments, each of the first and second diffusion fins is centered according to either a first diffusion fin pitch or a second diffusion fin pitch, the first The diffusion fin pitch is measured in the second direction, the second diffusion fin pitch is measured in the second direction, wherein the first and second diffusion pitches are in the second direction Alternate one after another, and one of the average diffusion fin pitches is the average of the first and second diffusion fin pitches, and

The pitch of the interconnection in the second direction is a rational multiple of the average diffusion fin pitch. The rational multiple is defined as the ratio of integer values. In some embodiments, the first diffusion fin pitch is equal to the second diffusion fin pitch. In some embodiments, the first diffusion fin pitch is different from the second diffusion fin pitch.

The above-mentioned one or more interconnect structures may include a local interconnect structure, a higher-level interconnect structure, or any combination thereof, where the local interconnect structure is the lowest of the non-diffused fins A hierarchical interconnect structure, wherein the higher-level interconnect structure is an interconnect structure formed at a level above the local interconnect structure of the substrate.

In some embodiments, each of the first and second diffusion fins is based on a first diffusion fin pitch measured in the second direction, or measured in the second direction A second diffusion fin pitch of any one is centerline arranged, wherein the first and second diffusion pitches alternate in the second direction one after another, and one of the average diffusion fin pitches is The average pitch of the first and second diffusion fins. In addition, the one or more interconnect sections extending in the first direction can be based on a first interconnect pitch measured in the second direction or a measured in the second direction A centerline configuration is applied to any of the second interconnection pitches, wherein the first and second interconnection pitch systems alternate in the second direction one after another, and one of the average interconnection pitch systems The average of the pitch of the first and second interconnecting lines. In addition, the average interconnection pitch is a rational multiple of the average diffusion fin pitch, and the rational multiple is defined as a ratio of integer values.

In some embodiments, the first diffusion fin pitch is equal to the second diffusion fin pitch, and the first interconnect pitch is equal to the second interconnect pitch. In some embodiments, the first diffusion fin pitch is different from the second diffusion fin pitch, and the first interconnect pitch is different from the second interconnect pitch. In some embodiments, the first diffusion fin pitch is equal to the first interconnect pitch, and the second diffusion fin pitch is equal to the second interconnect pitch.

The semiconductor device may also include more than one interconnect structure, wherein several of the more than one interconnect structure include more than one interconnect section extending in the second direction. In some embodiments, several of the one or more interconnect sections extending in the second direction are disposed between the first and second gate electrode structures. In some embodiments, several of the one or more interconnect sections extending in the second direction are located above either the first gate electrode structure or the second gate electrode structure.

In some embodiments, the one or more interconnecting line segments extending in the second direction are configured according to a first direction interconnecting line pitch, the pitch is more than one in the first direction Measured between the centerlines of the inner line segments oriented in the second direction. In addition, the first and second gate electrode structures can be configured according to a gate electrode pitch that is oriented in the second direction of the respective first and second gate electrode structures in the first direction Measured between centerlines. The inner line pitch in the first direction may be a rational multiple of the gate electrode pitch, and the rational multiple is defined as a ratio of integer values.

The above-mentioned one or more interconnect structures may include any of a local interconnect structure, a higher-level interconnect structure, or a combination thereof, where the local interconnect structure is the lowest level of the non-diffused fin The interconnect structure, and the higher level interconnect structure is an interconnect structure, which is formed at a level above the partial interconnect structure relative to the substrate.

In some embodiments, the semiconductor device may also include a first complex transistor, each of which has a respective source region and a respective drain region formed by respective diffusion fins. Each of the diffusion fins of the first plurality of transistors is configured to protrude from the surface of the substrate. Each diffusion fin of the first complex transistor is constructed to extend longitudinally in the first direction from a first end to a second end of the respective diffusion fin. The first ends of the diffusion fins of the first complex transistor are substantially aligned with each other in the first direction.

In addition, the semiconductor device may also include second complex transistors, each of which has a respective source region and a respective drain region formed by respective diffusion fins. Each diffusion fin of the second complex transistor is configured to protrude from the surface of the substrate. Each diffusion fin of the second complex transistor is constructed to extend longitudinally in a first direction from a first end to a second end of the respective diffusion fin. The first ends of the diffusion fins of the second complex transistor are substantially aligned with each other in the first direction. Furthermore, one or more of the first ends of the diffusion fins of the second complex transistor are configured to be interposed in one of the diffusion fins of the first complex transistor in the first direction Between these first and second ends.

In some embodiments, each of the first ends of the diffusion fins of the second complex transistor is arranged in the first direction between more than one of the diffusion fins of the first complex transistor Between the first and second ends. In some embodiments, at least one of the diffusion fins of the second complex transistor is configured to be adjacent to and spaced apart from at least one diffusion fin of the first complex transistor. In addition, in some embodiments, the first complex transistor may include n-type transistor, p-type transistor, or any combination of n-type and p-type transistor, and the second complex transistor may include n Type transistor, p-type transistor, or any combination of n-type and p-type transistors. In some embodiments, the first complex transistor system is an n-type transistor, and the second complex transistor system is a p-type transistor.

In some embodiments, the first and second complex diffusion fins are configured such that their respective centerlines oriented in the first direction are substantially aligned with a diffusion fin alignment grating, The diffusion fin alignment grid is defined by a first diffusion fin pitch measured in the second direction and a second diffusion fin pitch measured in the second direction. The first and second diffusion fin pitches appear in the second direction in an alternating order. Furthermore, in several embodiments, the diffusion fins of the first and second complex transistors collectively occupy at least part of at least eight consecutive alignment positions of the diffusion fin alignment grid.

In the illustrated embodiment, a method of manufacturing a semiconductor device is disclosed. The method includes providing a substrate. The method also includes forming a first transistor on the substrate so that the first transistor has a source region and a drain region within a first diffusion fin, and the first diffusion fin is formed Protruding from a surface of the substrate and making the first diffusion fin longitudinally in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin extend. The method also includes forming a second transistor on the substrate so that the second transistor has a source region and a drain region within a second diffusion fin, and the second diffusion fin is made Is formed to protrude from the surface of the substrate, and the second diffusion fin is formed in a first direction from a first end of the second diffusion fin to a first of the second diffusion fin The two end portions extend longitudinally, and the second diffusion fin is formed at a position adjacent to and spaced apart from the first diffusion fin. In addition, the first and second transistors are formed so that either the first end or the second end of the second diffusion fin is interposed between the first in the first direction The diffusion fin is formed at a position between the first end and the second end.

It should be understood that any circuit layout including fin field effect transistors as disclosed herein can be stored in a physical form, such as a digital format on a computer-readable medium. For example, a specific circuit layout can be stored in a layout data file, and can be selected from more than one component library. The layout data file can be formatted as a GDS II (graphical data system) database file, an OASIS (Open Original Image System Exchange Standard) database file, or any other type of data file format suitable for storing and disseminating the layout of semiconductor devices. In addition, the multi-level layout of devices including fin field effect transistors as disclosed herein can be included in the multi-level layout of larger semiconductor devices. The multi-level layout of the larger semiconductor device can also be stored in the form of the layout data file described above, for example.

In addition, the invention described herein can be embodied as computer-readable codes on a computer-readable medium. For example, the computer-readable code may include a layout data file in which the layout of the device including fin field effect transistors as disclosed herein is stored. The computer readable code may also include program instructions for selecting more than one layout library and / or components including fin field effect transistors as disclosed herein. The layout library and / or components can also be stored in a digital format on a computer-readable medium.

The computer-readable medium mentioned here is any data storage device that can store data that can be read later by the computer system. Examples of computer-readable media include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROM, CD-R, CD-RW, magnetic tape, and other optical and non-magnetic Optical data storage device. Multiple computer-readable media distributed in the network of connected computer systems can also be used to store various parts of the computer-readable code, so that the computer-readable code is stored in a distributed manner within the network And implementation.

In an exemplary embodiment, a data storage device has computer executable program instructions stored thereon for providing a layout of a semiconductor device. The data storage device includes computer program instructions for defining a first transistor formed on a substrate, so that the first transistor is defined as having a source region and a The drain region, and so that the first diffusion fin is defined to protrude from a surface of the substrate, and so that the first diffusion fin is defined as a first The end extends longitudinally from a second end of the first diffusion fin. The data storage device also includes computer program instructions for defining the formation of a second transistor on the substrate, so that the second transistor is defined as having a source region and a drain within a second diffusion fin Polar region, and so that the second diffusion fin is defined to protrude from the surface of the substrate, and so that the second diffusion fin is defined from the first end of the second diffusion fin in the first direction Part to the second end of the second diffusion fin to extend longitudinally, and so that the second diffusion fin is defined to be disposed adjacent to and spaced apart from the first diffusion fin, and so that the second The diffusion fin is defined such that its first end or its second end is configured to be interposed between the first end and the second end of the first diffusion fin in the first direction.

It should be further understood that any circuit layout including fin field effect transistors as disclosed herein can be manufactured as part of a semiconductor device or wafer. In the manufacture of semiconductor devices such as integrated circuits, memory devices, etc., a series of manufacturing operations are performed to define features on the semiconductor wafer. The wafer includes an integrated circuit device in the form of a multi-layer structure defined on a silicon substrate. At a substrate level, a transistor device having diffusion regions and / or diffusion fins is formed. At the subsequent level, the interconnect metal lines are patterned and electrically connected to the transistor device to define a desired integrated circuit device. In addition, the patterned conductive layer is insulated from other conductive layers by dielectric materials. Although this invention has been described in terms of several embodiments, it is obvious to those skilled in the art that after studying the foregoing description and drawings, they will understand various changes, additions, substitutions, and equivalents thereof. Therefore, the present invention should include all such changes, additions, substitutions, and equivalents that fall within the true spirit and scope of the present invention.

100‧‧‧Fin field effect transistor
102‧‧‧Diffusion fin
104‧‧‧Gate electrode layer
105‧‧‧ substrate
106‧‧‧ Gate oxide layer
107‧‧‧Core
109‧‧‧Side partition
201A / 201B‧‧‧Diffuse Fin
203‧‧‧pitch
205‧‧‧pitch
207‧‧‧Gate electrode structure
209‧‧‧Gate Pitch
211‧‧‧Horizontal local interconnecting structure
213‧‧‧Vertical local interconnecting structure
215‧‧‧met1 interconnect structure
215A / 215B‧‧‧Interconnect structure
217‧‧‧Contact window
219‧‧‧met2 interconnect structure
221‧‧‧‧‧‧Interlayer window structure
250‧‧‧Ellipse
251‧‧‧Ellipse
260‧‧‧yuan
261‧‧‧ Yuan
270‧‧‧arrow
2001‧‧‧Region
2601 and 2603 ‧‧‧ gate electrode structure
2605‧‧‧ input connection
2607‧‧‧ input connection
2701‧‧‧cut shape part
2703 and 2705 ‧‧‧ gate conductor
3105‧‧‧Region
3201‧‧‧ Yuan
3301‧‧‧ Yuan
70-1A to 70-1E ‧‧‧ gate electrode track
70-3‧‧‧Gate electrode pitch
70-5A to 70-5E‧‧‧channel
7001-7008‧‧‧ Gate characteristics
8001‧‧‧Region
8003‧‧‧Diffusion fin

According to several embodiments of the present invention, FIGS. 1A and 1B show an exemplary layout of a fin field effect transistor.

According to several embodiments of the present invention, FIG. 1C shows the deformation of the fin-type field effect transistor of FIGS. 1A / 1B, in which the diffused fin 102 is more angular-vertical in the vertical cross-sectional view A-A.

According to several embodiments of the present invention, FIG. 1D shows a simplified vertical cross-sectional view of a substrate having a plurality of fin field effect transistors formed thereon.

According to several embodiments of the present invention, FIG. 1E shows a diagram of the fin pitch relationship, where the inner fin pitch Ps1 is substantially equal to the outer fin pitch Ps2.

According to several embodiments of the present invention, FIG. 1F shows a change in the relationship diagram of the fin pitch of FIG. 1E, in which the denominator (y) of the rational number is two.

According to several embodiments of the present invention, FIG. 1G shows a change in the diagram of the pitch relationship of the fins in FIG. 1E, where the denominator (y) of the rational number is three.

According to several embodiments of the present invention, FIG. 1H shows a more generalized version of the fin pitch relationship diagram of FIG. 1E, where the inner fin pitch Ps1 and the outer fin pitch Ps2 are different.

According to several embodiments of the present invention, FIG. 2A shows an exemplary device layout including fin field effect transistors.

According to several embodiments of the present invention, FIG. 2B shows a circuit diagram corresponding to the 2-input NAND configuration of FIG. 2D.

According to several embodiments of the present invention, FIG. 2C shows a circuit diagram corresponding to the 2-input NOR configuration of FIG. 2E.

According to several embodiments of the present invention, FIG. 2D shows the layout of FIG. 2A, wherein the diffusion fin 201A is formed of n-type diffusion material, and the diffusion fin 201B is formed of p-type diffusion material.

According to several embodiments of the present invention, FIG. 2E shows the layout of FIG. 2A, wherein the diffusion fin 201A is formed of p-type diffusion material, and the diffusion fin 201B is formed of n-type diffusion material.

According to several embodiments of the present invention, FIG. 2F shows a variation of the layout of FIG. 2A, in which the end of the gate electrode structure is substantially aligned at the top of the element and the bottom of the element. .

According to several embodiments of the present invention, FIG. 2G shows a variation of the layout of FIG. 2A, wherein the contact window is formed to extend from the met1 interconnection structure to the horizontal partial interconnection structure at the top and bottom of the device under the power rail.

According to several embodiments of the present invention, FIG. 2H shows a variation of the element of FIG. 2A, in which two different diffusion fin pitches are used.

According to several embodiments of the present invention, FIG. 2I shows a variation of the layout of FIG. 2A, in which the diffused fins and the horizontal partial interconnect structure under the power rails at the top and bottom of the device extend as the full width.

According to several embodiments of the present invention, FIG. 3 shows a variation of the layout of FIG. 2A, where the met1 power rail is connected to a vertical local interconnect so that the met1 power rail serves as a local power source.

According to several embodiments of the present invention, FIG. 4 shows a variation of the layout of FIG. 2A, in which a two-dimensionally changed met1 interconnect structure is used within the device for internal device winding.

According to several embodiments of the present invention, FIG. 5 shows a variation of the layout of FIG. 2A, in which the met1 power rail is connected to a vertical partial interconnect, and wherein a two-dimensionally changed met1 interconnect structure is used in the device for internal device wiring.

According to several embodiments of the present invention, FIG. 6 shows a variation of the layout of FIG. 2A, in which a fixed, minimum width, common local met1 power supply is used, and a two-dimensional variation met1 interconnect structure for in-device winding within the device is used.

According to several embodiments of the present invention, FIG. 7 shows a variation of the layout of FIG. 2A, which has a common local and global power supply with hard-wiring in the device, and a two-dimensional variation met1 in the device for internal wiring of the device. structure.

According to several embodiments of the present invention, FIG. 8A shows a layout illustrating an exemplary standard device, in which input pins are arranged between diffusion fins of the same type to alleviate winding congestion, and several diffusion fins are used as interconnect conductors.

According to several embodiments of the present invention, FIG. 8B shows a variation of FIG. 8A where two different gate electrode pitches are used.

According to several embodiments of the present invention, FIG. 8C shows a circuit diagram of the layout of FIG. 8A.

According to several embodiments of the present invention, FIG. 9A shows an exemplary standard device layout in which diffusion fins are used as interconnect conductors.

According to several embodiments of the present invention, FIG. 9B shows the layout of FIG. 9A, in which three sets of cross-connected transistors are marked. .

According to several embodiments of the present invention, FIG. 9C shows a circuit diagram of the layout of FIG. 9A.

According to several embodiments of the present invention, FIG. 10 shows an exemplary standard device layout in which the gate electrode contact window is substantially disposed above the diffusion fin.

According to several embodiments of the present invention, FIG. 11 shows an exemplary element layout implementing a diffusion fin.

According to several embodiments of the present invention, FIGS. 12A / B show a variation of the layout of FIG. 11 having a minimum width met1 power rail.

According to several embodiments of the present invention, FIG. 13A / B shows a variation of the layout of FIG. 12A / B, which does not have contact windows from various local interconnects and gate electrode structures to met1.

According to several embodiments of the present invention, FIG. 14A / B shows a variation of the layout of FIG. 11, which has a minimum width met1 power rail, and all met1 structures including the power rail have the same width and the same pitch.

According to several embodiments of the present invention, FIG. 15A / B shows a variation of the layout of FIG. 14A / B, which has a met1 winding structure configured to have a met1 structure at each (y) position.

According to several embodiments of the present invention, FIGS. 16A / B show a variation of the layout of FIG. 11, which has a gate electrode structure contact window disposed between p-type diffusion fins.

According to several embodiments of the present invention, FIGS. 17A / B show exemplary element layouts that implement diffusion fins.

According to several embodiments of the present invention, FIG. 18A / B shows a variation of the layout of FIG. 17A / B, wherein the contact window is connected to the horizontal local interconnect, and wherein the horizontal local interconnect is directly connected to the vertical local interconnect.

According to several embodiments of the present invention, FIG. 19A / B shows a variation of the layout of FIG. 17A / B, where the power rail contact window to the local interconnect is not shared, and where there is no shared local interconnect under the power rail.

According to several embodiments of the present invention, FIG. 20A / B shows a variation of the layout of FIG. 19A / B, in which the diffusion fins are offset by half the diffusion fin pitch relative to the device boundary.

According to some embodiments of the present invention, FIG. 21A / B shows a variation of the layout of FIG. 20A / B, which has a minimum width power rail and a negative vertical partial interconnection of diffusion fins overlapping.

According to some embodiments of the present invention, FIG. 22A / B shows a variation of the layout of FIG. 17A / B, which has a minimum width power rail, local interconnects and diffusion fins that are not shared under the power rail, and p-fin and n-fin Larger spacing between departments.

According to several embodiments of the present invention, FIG. 23A / B shows a variation of the layout of FIG. 17A / B.

According to several embodiments of the present invention, FIG. 24A / B shows a variation of the layout of FIG. 23A / B.

According to several embodiments of the present invention, FIGS. 25A / B show a variation of the layout of FIG. 23A / B, in which the elements are doubled in height.

According to several embodiments of the present invention, FIG. 26A / B shows an exemplary element layout for implementing a diffusion fin.

According to several embodiments of the present invention, FIG. 27A / B shows a variation of the layout of FIG. 26A / B.

According to several embodiments of the present invention, FIGS. 28A / B show exemplary element layouts that implement diffusion fins.

According to several embodiments of the present invention, FIG. 29A / B shows a variation of the layout of FIG. 28A / B, in which there is no local interconnect structure between the gate electrode structures of two n-type transistors.

According to several embodiments of the present invention, FIGS. 30A / B show exemplary element layouts implementing diffusion fins.

According to several embodiments of the present invention, FIG. 31A shows an exemplary sdff device layout in which the gate electrode and the local interconnect line end gap are located at the substantial center between the diffusion fins.

According to several embodiments of the present invention, FIG. 31B shows the exemplary sdff device layout of FIG. 31A, in which a partial inner wire end gap located in the substantially center between the diffusion fins is circled.

According to several embodiments of the invention, FIG. 31C shows the illustrated sdff element layout of FIGS. 31A and 31B with the label between the regions between two adjacent gate electrode structures, where the ends of the diffusion fins overlap each other in the x direction.

According to several embodiments of the present invention, FIG. 32 shows an exemplary layout in which all contact layer structures are arranged between the diffusion fins.

According to several embodiments of the present invention, FIGS. 33 and 34 show exemplary layouts in which all contact layer structures are arranged on the diffusion fins.

According to several embodiments of the present invention, FIGS. 35A / B to 47A / B show a cross-connected transistor configuration with transmission gates on both logic paths, which requires all internal nodes to have a connection between p-type and n-type.

According to several embodiments of the present invention, FIG. 35C shows a circuit diagram of the layout of FIGS. 35A / B to 47A / B and 63A / B to 67A / B.

According to several embodiments of the present invention, FIGS. 48A / B to 57A / B show a cross-connected transistor configuration with a transmission gate on a logic path using a larger transistor, and a tri-state gate on other paths.

According to several embodiments of the present invention, FIG. 48C shows a circuit diagram of the layout of FIGS. 48A / B to 58A / B.

According to several embodiments of the present invention, FIGS. 58A / B to 59A / B show a cross-connected transistor configuration with a transmission gate on a logic path using a smaller transistor, and a tri-state gate on other paths.

According to several embodiments of the present invention, FIG. 59C shows a circuit diagram of the layout of FIG. 59A / B.

According to several embodiments of the present invention, FIGS. 60A / B to 62A / B show a cross-connected transistor configuration with tri-state gates on both logic paths.

According to several embodiments of the present invention, FIG. 60C shows a circuit diagram of the layout of FIGS. 60A / B to 62A / B and FIGS. 68A / B to 69A / B.

According to several embodiments of the present invention, FIGS. 63A / B to 67A / B show a cross-connect transistor configuration with transmission gates on both logic paths, which requires all internal nodes to have a connection between p-type and n-type. .

According to several embodiments of the invention, FIGS. 68A / B to 69A / B show a cross-connected transistor configuration with tri-state gates on both logic paths.

According to several embodiments of the present invention, FIG. 70A shows an example of gate electrode tracks 70-1A to 70-1E defined within a restricted gate hierarchy layout structure.

According to several embodiments of the present invention, FIG. 70B shows the exemplary restricted gate hierarchy layout structure of FIG. 70A, which has several exemplary gate hierarchy features 7001-7008 defined therein.

According to several embodiments of the present invention, FIGS. 71A / B to 77A / B show several exemplary SDFF circuit layouts that utilize cross-connect circuit structures based on both transmission and tri-state gates.

According to some embodiments of the present invention, FIG. 71C shows a circuit diagram of the layout of FIGS. 71A / B and 77A / B.

According to several embodiments of the present invention, FIG. 72C shows a circuit diagram of the layout of FIGS. 72A / B to 76A / B.

201A / 201B‧‧‧Diffuse Fin

203‧‧‧pitch

207‧‧‧Gate electrode structure

209‧‧‧Gate Pitch

211‧‧‧Horizontal local interconnecting structure

213‧‧‧Vertical local interconnecting structure

215‧‧‧met1 interconnect structure

217‧‧‧Contact window

221‧‧‧Interlayer window structure

Claims (26)

A component circuit of a semiconductor device, comprising: a substrate; a first diffusion type four diffusion fins formed to extend in a parallel relationship with each other, the first diffusion type adjacent to the four diffusion fins It is configured according to a fixed centerline to centerline pitch; a second diffusion type four diffusion fins, which are formed to extend in a parallel relationship with each other, adjacent It is configured according to the fixed centerline to centerline pitch; a first gate electrode extending above two of the four diffusion fins of the first diffusion type; a second gate electrode, at The two of the four diffusion fins of the second diffusion type extend above two; and a third gate electrode above two of the four diffusion fins of the first diffusion type and above the second diffusion type Two of the four diffusion fins extend above. As in the element circuit of the semiconductor device of claim 1, the third gate electrode is disposed between the first gate electrode and the second gate electrode. An element circuit of a semiconductor device as claimed in item 2 of the patent scope, wherein each of the first gate electrode, the second gate electrode, and the third gate electrode is linear and oriented in the A first reference direction extends longitudinally. An element circuit of a semiconductor device as claimed in item 3 of the patent scope, wherein each of the four diffusion fins of the first diffusion type is linear and oriented in a first direction perpendicular to the first reference direction The two reference directions extend longitudinally, and wherein each of the four diffusion fins of the second diffusion type is linear and oriented to extend longitudinally in the second reference direction. A component circuit of a semiconductor device as claimed in item 4 of the patent application, wherein the first gate electrode is separated from the third gate electrode by a first distance measured in the first reference direction, and wherein, The second gate electrode is separated from the third gate electrode by the first distance measured in the first reference direction. An element circuit of a semiconductor device as claimed in item 5 of the patent scope, wherein each of the first gate electrode, the second gate electrode, and the third gate electrode has a measurement in the second reference direction One of them has substantially equal width. The component circuit of the semiconductor device as claimed in item 6 further includes: a first contact window structure which is formed to physically contact the first gate electrode; a second contact window structure which is formed Physically contact the second gate electrode; and a third contact window structure, which is formed to physically contact the third gate electrode. As in the element circuit of the semiconductor device of claim 7, the first contact window structure is substantially in the center between two diffusion fins of the first diffusion type in the first reference direction. An element circuit of a semiconductor device according to claim 8 of the patent application, wherein the second contact window structure is substantially in the center between two diffusion fins of the second diffusion type in the first reference direction. An element circuit of a semiconductor device as claimed in item 9 of the patent scope, wherein the third contact window structure is one of the first diffusion type diffusion fins and the second diffusion type in the first reference direction A substantial center between the diffusion fins. For example, the component circuit of the semiconductor device of claim 10 further includes: a first interconnect structure, which is formed to physically contact the first contact window structure; a second interconnect structure, which is It is formed to physically contact the second contact window structure; and a third interconnect structure is formed to physically contact the third contact window structure. A component circuit of a semiconductor device as claimed in item 11 of the patent scope, wherein each of the first interconnect structure, the second interconnect structure, and the third interconnect structure is located on the semiconductor device It is formed within the same interconnect hierarchy. An element circuit of a semiconductor device as claimed in item 12 of the patent application, wherein the first interconnect structure is linear and oriented to extend longitudinally in the second reference direction. An element circuit of a semiconductor device according to claim 13 of the patent application, wherein the second interconnection structure is linear and oriented to extend longitudinally in the second reference direction. An element circuit of a semiconductor device as claimed in item 14 of the patent application, wherein the third interconnection structure is linear and oriented to extend longitudinally in the second reference direction. A component circuit of a semiconductor device as claimed in item 15 of the patent scope, wherein each of the first interconnect structure, the second interconnect structure, and the third interconnect structure has the first reference One measured in the direction is substantially equal in width. For example, the device circuit of the semiconductor device of claim 16 further includes: a first local interconnect structure extending above the four diffusion fins of the first diffusion type; a second local interconnect structure, Extending above the four diffusion fins of the second diffusion type; a third local interconnect structure, two of the four diffusion fins of the second diffusion type and the four diffusions of the first diffusion type The fin extends above; and a fourth partial interconnect structure extends above two of the four diffusion fins of the second diffusion type. An element circuit of a semiconductor device as claimed in claim 17, wherein the first partial interconnect structure, the second partial interconnect structure, the third partial interconnect structure, and the fourth partial interconnect Each of the wire structures is linear and oriented to extend longitudinally in the first reference direction. A component circuit of a semiconductor device according to claim 18 of the patent application scope, wherein a first center line of the first partial interconnect structure is substantially aligned with a first center line of the second partial interconnect structure. A component circuit of a semiconductor device as claimed in item 19 of the patent scope, wherein the first center line of the third partial interconnect structure is substantially aligned with the first center line of the fourth partial interconnect structure. For example, a component circuit of a semiconductor device according to claim 20, wherein the first partial interconnection structure is separated from the second partial interconnection structure by a second distance measured in the first reference direction, And, wherein the third partial interconnection structure is separated from the fourth partial interconnection structure by the second distance measured in the first reference direction. An element circuit of a semiconductor device as claimed in claim 21, wherein the second distance measured in the first reference direction is substantially equal to the first distance measured in the first reference direction. A component circuit of a semiconductor device according to claim 22, wherein the first partial interconnection structure and the second partial interconnection structure are each of the first, second, and third gate electrodes One of them is arranged on a first side, and wherein the third partial interconnect structure and the fourth partial interconnect structure are at each of the first, second, and third gate electrodes Is configured on the second side. A component circuit of a semiconductor device as claimed in item 23, wherein the first partial interconnection structure is separated from the first gate electrode by a third distance measured in the second reference direction, and the The first partial interconnection structure is separated from the third gate electrode by the third distance measured in the second reference direction, and the second partial interconnection structure is separated from the second gate electrode The third distance measured in the second reference direction and the second partial interconnect structure are separated from the third gate electrode by the third distance measured in the second reference direction. A component circuit of a semiconductor device according to claim 24, wherein the third partial interconnection structure is separated from the first gate electrode by a fourth distance measured in the second reference direction, and the The third partial interconnection structure is separated from the third gate electrode by the fourth distance measured in the second reference direction, and the fourth partial interconnection structure is separated from the second gate electrode The fourth distance measured in the second reference direction and the fourth partial interconnect structure are separated from the third gate electrode by the fourth distance measured in the second reference direction. An element circuit of a semiconductor device as claimed in claim 25, wherein the fourth distance measured in the second reference direction is substantially equal to the third distance measured in the second reference direction.