CN107393903A - 多层金属焊盘 - Google Patents

多层金属焊盘 Download PDF

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Publication number
CN107393903A
CN107393903A CN201710293949.9A CN201710293949A CN107393903A CN 107393903 A CN107393903 A CN 107393903A CN 201710293949 A CN201710293949 A CN 201710293949A CN 107393903 A CN107393903 A CN 107393903A
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China
Prior art keywords
layer
conductive material
pad
metal
conductive
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Granted
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CN201710293949.9A
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CN107393903B (zh
Inventor
F.赫林
M.施内甘斯
B.魏德甘斯
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明公开多层金属焊盘。一种用于制造半导体器件的方法包括在第一区中在第一着陆焊盘之上以及在第二区中在第二着陆焊盘之上形成导电衬垫。方法还包括在形成于导电衬垫之上的抗蚀剂层内的第一开口内沉积第一导电材料。第一导电材料满溢以形成第一焊盘以及第二焊盘的第一层。方法还包括在第一导电材料之上沉积第二抗蚀剂层，并且图案化第二抗蚀剂层以形成暴露第二焊盘的第一层而不暴露第一焊盘的第二开口。在第二焊盘的第二层之上沉积第二导电材料。

Description

多层金属焊盘
技术领域
本发明一般涉及半导体器件，并且在特定实施例中，涉及多层金属焊盘和制作它们的方法。
背景技术
半导体器件使用在各种电子和其他应用中。除了其他许多东西之外，半导体器件还包括集成电路或分立器件，其通过在半导体晶片之上沉积一种或多种类型的材料薄膜并且图案化材料薄膜以形成集成电路而被形成在半导体晶片上。
在半导体衬底内制造各种器件之后，这些器件通过金属互连部而被互连。金属互连部形成在器件区之上并且形成在称为金属化物层级多个层或层级中。金属互连部在传统工艺中由铝制成。
技术缩放已经积极地要求减小较低金属化物层级中的金属互连部的厚度。减小的厚度造成这些金属线的增加的电阻。因此，较低的金属化物层级已经被铜取代，其具有较低的电阻。
另外，功率器件具有附加的要求。通过焊盘汲取的电流在功率器件中明显更高。这样的焊盘必须更厚以改进热耗散和热容量。这增加将厚铜集成到最上部金属化物层级中的复杂度。
发明内容
根据本发明的实施例，一种用于制造半导体器件的方法，所述方法包括在第一区中在第一着陆焊盘（landing pad）之上以及在第二区中在第二着陆焊盘之上形成导电衬垫（liner）。所述方法还包括在形成于导电衬垫之上的抗蚀剂层内的第一开口内沉积第一导电材料。第一导电材料满溢（overfill）以形成第一焊盘以及第二焊盘的第一层。所述方法还包括在第一导电材料之上沉积第二抗蚀剂层，并且图案化第二抗蚀剂层以形成暴露第二焊盘的第一层而不暴露第一焊盘的第二开口。所述方法还包括在第二焊盘的第二层之上沉积第二导电材料。
根据本发明的实施例，一种用于制造半导体器件的方法包括在第一区中在第一着陆焊盘之上以及在第二区中在第二着陆焊盘之上形成导电衬垫，在导电衬垫之上沉积抗蚀剂层，以及图案化抗蚀剂层以在抗蚀剂层中形成第一开口。所述方法还包括在第一开口内沉积第一导电材料，第一导电材料满溢以形成第一焊盘以及第二焊盘的第一层。所述方法还包括在第一导电材料之上沉积蚀刻停止衬垫，在蚀刻停止衬垫之上沉积第二导电材料，以及蚀刻第二导电材料和蚀刻停止衬垫以形成第二焊盘。第二焊盘包括第一导电材料层和第二导电材料层。
根据本发明的实施例，一种半导体器件包括衬底中的第一区和衬底中的第二区，所述第一区包括晶体管，所述第二区包括功率晶体管。功率晶体管是用于向第一区中的晶体管提供功率的电路的部分。第一焊盘设置在第一区之上。第一焊盘耦合到第一区中的晶体管，并且第二焊盘设置在第二区之上。第二焊盘耦合到第二区中的功率晶体管。第一焊盘包括第一金属层的第一部分。第二焊盘包括第一金属层的第二部分和设置在第一金属层的第二部分之上的第二金属层的层。第一金属层包括第一导电材料，并且第二金属层包括第二导电材料。第二金属层的层具有比第一金属层的第二部分更小的覆盖区（foot print）。
附图说明
为了本发明及其优点的更加完整的理解，现在参照结合附图得到的以下描述，在所述附图中：
图1A图示根据本发明的实施例的半导体器件的横截面视图；
图1B图示根据本发明的实施例的半导体器件的顶视图；
图2A图示根据本发明的实施例的半导体器件的部分的顶视图；
图2B图示根据本发明的可替换实施例的半导体器件的部分的横截面视图；
图3A-3L图示根据本发明的实施例的依照用于制作半导体器件的过程的处理的各种阶段期间的半导体器件的横截面视图；以及
图4A-4E图示用于制造半导体器件的依照可替换实施例的处理的各种阶段期间的半导体器件的横截面视图。
具体实施方式
通过持续收缩集成电路芯片的物理尺寸，已经实现了性能增强、节能和生产成本中的降低。然而，热能的耗散仍旧是一项挑战。对此的主要原因是芯片的每单位面积的电流中的巨大增加。
在常规器件中，最上部的金属线由铝制成。因此，诸如铜之类的金属开始使用在最上部金属层中，其中电流密度最高。然而，不但在处理期间而且后来在产品使用期限期间存在与厚结构化的铜相关联的主要问题，其可以负面地影响产品的寿命。
示例包括与厚铜的沉积相关联的问题。例如，可以沉积的最大厚度由细间距结构限制。这是因为铜被镀在图案化的抗蚀剂结构之间。特别地，抗蚀剂结构必须比正沉积的铜的厚度更厚。然而，抗蚀剂的最大厚度在细间距结构中是有限的。这限制细间距结构中的金属的厚度，所述细间距结构在诸如逻辑、存储器和其他之类的功能电路区域之上使用。例如，可以沉积的铜的最大厚度小于大约20μm。
当铜的厚度减小以适应细间距结构时，半导体器件的冷却能力降低。功率半导体器件生成大量的热，其必须从器件抽出以用于器件的适当运转。无能力形成厚功率金属可以造成产品使用期限中的显著减少。
另外，厚铜层由于较高的（固有）应力而造成高晶片翘曲，所述较高的（固有）应力是由于金属层相对于硅的热膨胀的失配所致。这样的高应力可以导致整个焊盘的分层。然而，导致较低应力水平的膜典型地对于进行电接触而言是差的，例如由于与导线接合部的差的接合所致。
因此，通过使用厚功率金属进行的良好热耗散和良好的电接触传统上要求相反的条件。本发明的实施例通过在多个层级之上形成焊盘来克服这些和其他问题。形成在多个层级之上的焊盘避免热耗散和电连接性的冲突需要。
图1A和1B将用于描述本发明的结构实施例。图2A和2B图示本发明的可替换的结构实施例。制作器件的可替换实施例将使用图3和4来描述。
图1A图示根据本发明的实施例的半导体器件的横截面视图。
参照图1A，半导体芯片布置在衬底10上。在各种实施例中，半导体芯片可以包括集成电路芯片。在一个或多个实施例中，半导体芯片可以包括逻辑芯片、存储器芯片、模拟芯片、混合信号芯片及其组合，诸如片上系统，或其他合适类型的器件。半导体芯片可以包括各种类型的有源和无源器件，诸如二极管、晶体管、晶闸管、电容器、电感器、电阻器、光电子器件、传感器、微机电系统和其他。
在各种实施例中，半导体芯片包括不同类型的器件区。如所图示的，半导体芯片包括第一区1和第二区2，所述第一区1包括低功率或标准电压器件，所述第二区2包括高电压或功率器件。第二区2的功率器件可以包括操作在较高电压处的器件，并且一般用作用于向标准电压器件提供功率的输入/输出器件。例如，标准电压器件可以操作在0.8V至1.8V的阈值电压处，而功率器件可以操作在高于5V的阈值电压处。
在各种实施例中，半导体芯片可以形成在硅衬底10上。衬底10可以包括外延层，其包括异质外延或同质外延层。衬底10的一些示例是块体单晶硅衬底（或生长在其上或以其他方式形成在其中的层）、（100）硅晶片上的（110）硅的层、绝缘体上硅（SOI）晶片的层或绝缘体上锗（GeOI）晶片的层。可替换地，在其他实施例中，半导体芯片可以已经形成在碳化硅（SiC）上。在一个实施例中，半导体芯片可以已经至少部分地形成在氮化镓（GaN）上。例如，半导体芯片可以是形成在硅上的GaN上的横向晶体管。在另一实施例中，半导体芯片可以是形成在块体GaN衬底上的GaN上的垂直晶体管。在其他实施例中，其他半导体，诸如硅锗、锗、砷化镓、砷化铟、砷化镓铟（indium gallium arsenide）、锑化铟、磷化铟、其组合或其他，可以用作衬底10。
衬底10包括第一区1中的第一有源器件区11和第二区2中的第二有源器件区12。第一有源器件区11可以包括例如形成标准电压晶体管的掺杂区。相比之下，第二有源器件区12可以包括形成功率器件（例如，漏极延伸型金属氧化物半导体（DMOS）晶体管）的掺杂区。
接下来，在第一和第二有源器件区11和12之上设置金属化物以电接触和互连有源器件。金属化物和有源器件区一起形成完整功能的集成电路。换言之，芯片的电功能可以由互连的有源电路执行。作为示例，在逻辑器件中，金属化物可以包括许多层（例如，九个或更多）铜或可替换地其他金属。
参照图1A，为了图示，在衬底10之上设置第一绝缘层16。在一个或多个实施例中，第一绝缘层16可以包括蚀刻停止层诸如氮化硅、氮氧化硅以及其他。
第一绝缘层16包括SiO2（使用如下沉积的），诸如正硅酸乙酯（TEOS）或氟化TEOS（FTEOS），但是在各种实施例中可以包括典型地使用在半导体制造中以用于层级间电介质（ILD）层的绝缘材料，诸如掺杂玻璃（BPSG、PSG、BSG）、有机硅酸盐玻璃（OSG）、碳掺杂的氧化物（CDO）、氟化硅酸盐玻璃（fluorinated silicate glass）（FSG）、旋涂玻璃（SOG）或低k绝缘材料，例如具有大约4或更小的介电常数，或电介质扩散屏障层或蚀刻停止层诸如氮化硅（SiN）、氮氧化硅（SiON）、碳化硅（SiC）或碳氮化硅（silicon carbo nitride）（SiCN），例如具有大约4或更高的介电常数，或其组合或多个层，作为示例，尽管可替换地，第一绝缘层16可以包括其他材料。作为示例，第一绝缘层16还可以包括致密SiCOH或多孔电介质，其具有大约3或更低的k值。第一绝缘层16还可以包括例如超低k（ULK）材料，其具有大约2.3或更低的k值。第一绝缘层16可以包括例如大约500nm或更小的厚度，尽管可替换地，第一绝缘层16可以包括其他尺寸。
多个接触插头形成在第一绝缘层16内以耦合到衬底10的各种区，包括第一有源器件区11和第二有源器件区12。作为示例，所述多个接触插头可以耦合到衬底10的硅化物区。
第二绝缘层17设置在第一绝缘层16之上。第一金属层级M1耦合到第一绝缘层16中的所述多个接触插头并且形成在第二绝缘层17内。第二绝缘层17可以包括层级间电介质层，并且可以例如如以上针对第一绝缘层16所描述的那样被适当地选择。
多个金属线形成在第二绝缘层17内以形成第一金属层级M1。金属线可以包括多个层，例如粘附层、例如用以防止铜扩散到底层中的金属屏障层、用于填充材料的后续生长的种子层以及填充材料。
后续层可以使用双镶嵌工艺来形成，尽管在各种实施例中，还可以使用镶嵌工艺。例如，具有金属层级和通孔层级的每一个层级包括双层开口，其具有上部导电线和下部导电通孔。上部导电线可以是诸如沟槽之类的开口（但是还可以是孔），并且可以填充有金属。导电通孔可以是诸如孔之类的开口（但是还可以是沟槽），并且也可以填充有金属。
第一通孔层级V1和第二金属层级M2可以形成在第三绝缘层18内作为单个结构。类似于第一金属层级M1，单个结构可以包括粘附层、金属屏障层、种子层和填充材料。
另外的金属和通孔层级可以形成在附加的绝缘层中。例如，多个通孔形成在第三绝缘层18之上的第四绝缘层19中。
多个着陆焊盘30形成在第四绝缘层19之上。所述多个着陆焊盘30可以嵌入在第五绝缘层20内。所述多个着陆焊盘30也可以包括粘附层、屏障层、种子层和填充金属，如在各种实施例中那样。例如在一个实施例中，可以使用包括钨-钛的常见粘附和屏障层，而种子层可以是铜层和/或附加的功能层，并且填充材料可以是电镀的铜。
多个通孔40形成在所述多个着陆焊盘30之上并且将所述多个着陆焊盘30耦合到多个焊盘，所述多个焊盘包括第一类型的焊盘50和第二类型的焊盘60。第一类型的焊盘50形成在诸如第一有源器件区11之类的标准电压区之上，而第二类型的焊盘60形成在第二有源器件区12中的功率器件之上。在各种实施例中，第一类型的焊盘50相对于第二类型的焊盘60处于不同高度处。第二类型的焊盘60比第一类型的焊盘50厚得多。
在各种实施例中，第一类型的焊盘50为大约50μm至大约15μm，例如在一个实施例中为10μm至12μm。在各种实施例中，第二类型的焊盘60为大约20μm至大约50μm，例如在一个实施例中为25μm至35μm。
如图1A中进一步图示的，第二类型的焊盘60包括第一层60A和第二层60B。第一层60A具有与第一区1中的第一类型的焊盘50相同的组成，而第二层60B具有与第一类型的焊盘50不同的组成。
进一步地，如图1A中所图示的，第二层60B具有比第二层60B正下方的第一层60A更小的覆盖区。例如，沿平行于衬底10的主表面的临界尺寸，第二层60B比第一层60A小距离d的两倍。在各种实施例中，距离d为至少半微米。在一个或多个实施例中，距离d为大约1微米至10（2）微米。相应地，第二层60B的覆盖区（重叠在衬底10之上的区域）小于第一层60A的覆盖区。
在各种实施例中，第一层60A是与第二层60B不同类型的材料。在一个实施例中，第一层60A可以包括铜层，而第二层60B可以包括不同类型的铜材料层。
在一个或多个实施例中，第二层60B比第一层60A更加多孔。在一个实施例中，第一层60A是包括空隙的第二层60B的十倍那么致密。例如，百分数孔隙率和空隙的数目可以取决于正使用的沉积方法和材料系统而进行调节。例如，第一层60A可以具有按照体积小于1%的孔隙，而第二层60B可以具有按照体积大于5%的孔隙，并且在一个实施例中具有按照体积在5%至50%之间的孔隙。
在各种实施例中，第二层60B具有与第一层60A不同的组成。在一个实施例中，第一层60A可以包括重掺杂的铜层，而第二层60B可以包括较少掺杂。掺杂或合金化可以增加第一层60A的稳定性或韧性，而第二层60B仅用作适当的储热器或散热器。在一个实施例中，第二层60B具有比第一层60A的粒度更大的粒度。在一个实施例中，第二层60B可以使用不同的电化学添加剂来沉积，其可以使所沉积的第一层60A和第二层60B内的硫组分变化。换言之，在各种实施例中，第一层60A具有与第二层60B不同的硫含量。
图1B图示根据本发明的实施例的半导体器件的顶视图。
半导体芯片在主表面上包括多个焊盘。在常规芯片中，所有焊盘在相同表面处，即共平面。然而，在本发明的实施例中，耦合到第一有源器件区11的焊盘处于比耦合到第二有源器件区12的焊盘更低的表面处。例如，第二类型的焊盘60的第一焊盘61、第二焊盘62和第三焊盘63比所有其他焊盘（其全部是第一类型的焊盘50）更厚。然而，如从图1B清楚的并且以下进一步描述的，第一类型的焊盘50和第二类型的焊盘60二者的电接触焊盘仍旧在相同平面处。
如从图1A和1B清楚的，第二类型的焊盘60包括用于电接触的部分，即接触焊盘，以及用于冷却的部分，即冷却焊盘。通过基于功能而将接触焊盘分成分离的组件，本发明的实施例能够设计具有比常规器件更好的热耗散的器件同时维持出众的电连接性。
图2A图示根据本发明的实施例的半导体器件的部分的顶视图。
图2A图示根据本发明的实施例的经封装的半导体器件。参照图2A，半导体管芯5布置在衬底上。封装衬底25在一些示例中可以是导电衬底。例如，在一个实施例中，封装衬底25可以包括铜。在其他实施例中，封装衬底25包括金属材料，其可以包括导电金属及其合金。封装衬底25还可以包括金属间化合物材料。在另一可替换的实施例中，封装衬底25可以不是导电的。在再其他的实施例中，若干不同或相同的半导体管芯5可以通过不同技术附连在封装衬底25上。
封装衬底25在一个实施例中可以包括引线框架。例如，在一个实施例中，封装衬底25可以包括管芯座（paddle），半导体管芯5可以附连在所述管芯座之上。在另外的实施例中，封装衬底25可以包括一个或多个管芯座，一个或多个管芯可以附连在所述一个或多个管芯座之上。
多个引线31设置在半导体管芯5周围。多个导线71将第一类型的焊盘50和第二类型的焊盘60电连接到所述多个引线31。
如图2A中所图示的，第二类型的焊盘60具有第一层60A和第二层60B，例如如使用图1A所描述的。第二层60B可以仅用作热沉，而第一层60A可以用作电接触焊盘。这可能是因为第一层60A包括提供良好电接触的致密材料，而第二层60B包括多孔材料，其提供良好热耗散但是可能不与导线71形成良好电接触或导线接合。相应地，第一层60A可以包括焊盘区，其可以用于与导线71接合。
在一个实施例中，所述多个导线71形成为楔形接合部。在楔形接合期间，向导线施加压力和超声力以在第一类型的焊盘50和第二类型的焊盘60的接合焊盘上形成楔形接合部。在可替换的实施例中，球形接合部可以用于所述多个导线71。关于球形接合，金属球首先通过熔化导线末端而形成。将球放置在第一类型的焊盘50的接合焊盘上，并且向球施加压力、热和超声力达指定的时间量。
在一个或多个实施例中，用于所述多个导线71的导线接合材料尤其可以包括铜、铝和金。在其他实施例中，导线接合材料可以包括钨、钛、钽、钌、镍、钴、铂、银和这样的其他材料。
半导体管芯5、封装衬底25和所述多个导线71可以全部嵌入在包封剂24中。在各种实施例中，包封剂24包括电介质材料，并且在一个实施例中可以包括模制化合物。在一个或多个实施例中，包封剂24可以包括以下中的一个或多个：聚合物、共聚物、生物聚合物、纤维浸渍聚合物（例如，树脂中的碳或玻璃纤维）、颗粒填充的聚合物和其他有机材料。在再其他的说明性示例中，包封剂24可以包括不使用模制化合物形成的密封剂，以及诸如环氧树脂和/或硅树脂之类的材料。在各种实施例中，包封剂24可以由任何适当的硬质塑料、热塑塑料、热固性材料或层压件制成，并且在一些实施例中可以包括填充物材料。在另一实施例中，包封剂24可以包括环氧树脂材料和填充材料，所述填充材料包括玻璃或其他电绝缘矿物填充物材料（比如铝或有机填充材料）的小颗粒。
图2B图示根据本发明的可替换实施例的半导体器件的部分的横截面视图。
本发明的实施例可以应用于形成多层级焊盘。为了说明，图2B图示具有三个层级的焊盘。第一区1具有第一类型的焊盘50，第二区2具有第二类型的焊盘60，并且第三区3具有第三类型的焊盘64。如图2B中所图示的，第三类型的焊盘64形成在三个层级内。每一个层级使用分离的掩蔽步骤形成。最低层级包括填充金属172，并且可以用于电接触焊盘。第二层级包括第二填充金属173，并且可以通过分离的图案化和沉积工艺形成。附加的第三层级包括第三填充金属176，其可以使用另外的图案化和沉积工艺形成。例如，第二区2可以包括比第三区3更细的间距结构，由于这第二填充金属173的厚度可能是有限的。可替换地，第三区3中的器件可以比第二区2运行得更热，并且可能要求更厚的金属用于适当冷却。
图3A-3L图示根据本发明的实施例的依照用于制作半导体器件的过程的处理的各种阶段期间的半导体器件的横截面视图。
图3A图示在后端金属化期间半导体器件的横截面视图。在衬底10中和其之上形成有源区和掺杂区之后，在衬底10之上形成金属化物层级。
在各种实施例中，包括金属线层级和通孔层级的金属化物层级可以使用镶嵌或双镶嵌工艺形成。另外在可替换的实施例中，金属化物层级可以使用填充工艺和/或硅化物工艺来形成。
多个着陆焊盘30形成在最上部金属层级处。所述多个着陆焊盘30包括第一着陆焊盘141和第二着陆焊盘142。在各种实施例中，所述多个着陆焊盘30形成在第四绝缘层内。
第一蚀刻停止层160可以形成在所述多个着陆焊盘30之上，随后是层级间电介质层155（例如，图1中的第五绝缘层20）。蚀刻停止层还可以是防止金属扩散到电介质材料中的扩散屏障。第一蚀刻停止层160在一个实施例中使用物理气相沉积工艺来沉积。例如，在一个实施例中沉积氮化物膜（例如，氮化硅）。在各种实施例中，这样的层可以用于压盖金属线，并且可以包括电介质材料，诸如氮化硅（SiN）、碳化硅（SiC）、碳氮化硅（SiCN）或其他合适的电介质屏障层或其组合。在各种实施例中，第一蚀刻停止层160可以包括氧化物、氮化物或氮氧化物，诸如二氧化硅、氮化硅、氮氧化硅及其他。在可替换的实施例中，第一蚀刻停止层160可以包括硼掺杂的层，包括BPSG、氮化硼、硼氮化硅（silicon boron nitride）、碳氮化硅、硅锗、锗、基于碳的层诸如无定形碳。在另外的实施例中，第一蚀刻停止层160可以包括包含SiC:H的碳化硅，其包括C-H、Si-H、Si-CH3、Si-(CH2)n和Si-C的各种组合。
层级间电介质层155可以包括如之前关于图1A中的第一绝缘层16所描述的绝缘层。例如，层级间电介质层155包括绝缘材料，诸如SiO2、正硅酸乙酯（TEOS）、氟化TEOS（FTEOS）、掺杂玻璃（BPSG、PSG、BSG）、有机硅酸盐玻璃（OSG）、氟化硅酸盐玻璃（FSG）、旋涂玻璃（SOG）、SiN、SiON或低k绝缘材料，例如具有大约4或更小的介电常数，或其组合或多个层，作为示例，尽管可替换地，层级间电介质层155可以包括其他材料。作为示例，层级间电介质层155还可以包括致密SiCOH或多孔电介质，其具有大约3或更低的k值。例如，层级间电介质层155还可以包括例如超低k（ULK）材料，其具有大约2.3或更低的k值。层级间电介质层155可以包括例如大约500nm或更小的厚度，尽管可替换地，层级间电介质层155可以包括其他尺寸。
第二蚀刻停止层165沉积在层级间电介质层155之上。第一掩蔽层190形成在层级间电介质层155与抗蚀剂层157之上。抗蚀剂层157可以包括多个层，并且还可以包括硬掩模层。抗蚀剂层157或第一掩蔽层190还可以包括抗反射涂敷层。第一掩蔽层190可以是例如光致抗蚀剂层。
第一掩蔽层190在各种实施例中可以使用光刻工艺图案化。在一个实施例中，开口195通过第一掩蔽层190而形成以暴露抗蚀剂层157。
使用经图案化的第一掩蔽层190作为蚀刻掩模，抗蚀剂层157被进一步向下蚀刻，如图3B中示出的。即使在改变蚀刻化学物质之后，蚀刻工艺也可以继续以蚀刻穿层级间电介质层155。在各种实施例中，使用诸如反应离子蚀刻之类的各向异性蚀刻工艺。所暴露的第一蚀刻停止层160可以通过例如湿法蚀刻工艺来去除。
参照图3D，去除抗蚀剂层157从而暴露第二蚀刻停止层165。如接下来在图3E中所图示的，将导电衬垫171沉积在开口195内和第二蚀刻停止层165的顶表面之上。在各种实施例中，导电衬垫171可以包括多个层。例如，导电衬垫171可以包括粘附层、扩散屏障层和随后的种子层。扩散屏障层可以配置成防止铜扩散到底层中。在另外的实施例中，导电衬垫171还可以包括用于焊料金属的屏障层，该焊料金属用于接触要形成的焊盘。作为示例，导电衬垫171的扩散屏障金属可以包括钨-钛、钛、氮化钛、钽、氮化钽、钨、氮化钨、碳氮化钨（WCN）、钌或其他合适的导电氮化物或氧化物。
种子层可以沉积在扩散屏障层之上。在各种实施例中，种子层可以用于后续的沉积工艺，诸如电化学沉积工艺。相应地，在一个实施例中，种子层包括铜层。
在一个实施例中，导电衬垫171包括通过物理气相沉积（PVD）沉积的钨钛的扩散屏障层和随后的包括铜的种子层。导电衬垫171还可以包括凸块下金属化物，并且相应地包括焊料金属屏障，诸如镍钒、纯镍。
参照图3F，第二抗蚀剂层181被沉积和使用例如常规的光刻工艺图案化。例如，第二抗蚀剂层181可以使用光刻工艺来曝光和显影。第二抗蚀剂层181在各种实施例中可以具有大约5μm至大约30μm的厚度，并且在一个实施例中具有大约10μm至大约20μm的厚度。
使用导电衬垫171的暴露的种子层，填充金属172沉积在导电衬垫171之上。例如，电化学沉积工艺用于沉积填充金属172。在各种实施例中，铜被电镀以形成填充金属172。在各种实施例中，填充金属172可以包括大约4μm至大约25μm的厚度，并且在一个实施例中具有大约5μm至大约15μm的厚度。填充金属172相对于第二抗蚀剂层181更薄。
参照图3H，第三抗蚀剂层182被沉积并且使用例如常规的光刻工艺来图案化。例如，第三抗蚀剂层182可以使用光刻工艺进行曝光和显影。第三抗蚀剂层182在各种实施例中可以具有大约30μm至大约80μm的厚度，并且在一个实施例中具有大约40μm至大约60μm的厚度。第三抗蚀剂层182的图案化暴露例如第二着陆焊盘142之上的填充金属172的顶表面。
相应地，在各种实施例中，必要时可以使用抗蚀剂的不同的设计布局和不同的厚度。厚抗蚀剂仅在第二区2中被需要，在所述第二区2中沉积较厚的金属。这避免对于图案化细间距结构之上的厚抗蚀剂层的需要。
在可替换的实施例中，第二抗蚀剂层181可以被去除并且第三抗蚀剂层182可以被沉积和图案化以暴露例如第二着陆焊盘142之上的填充金属172的顶表面。
使用填充金属172的顶表面，将第二填充金属173沉积在填充金属172之上。例如，电化学沉积工艺用于沉积第二填充金属173。在各种实施例中，铜被电镀以形成第二填充金属173。第二填充金属173在各种实施例中可以包括大约15μm至大约50μm的厚度，并且在一个实施例中包括大约25μm至大约35μm的厚度。
在各种实施例中，第二填充金属173是与填充金属172不同类型的材料。例如，第二填充金属173可以具有比填充金属172更大的孔隙率。可替换地，第二填充金属173相比于填充金属172可以较不致密。在另一示例中，第二填充金属173可以与填充金属172不同地掺杂。在又另一示例中，第二填充金属173可以包括比填充金属172更大的粒度。
参照图3J，第三抗蚀剂层182和第二抗蚀剂层181被去除从而暴露导电衬垫171，即种子层。所暴露的导电衬垫171然后可以使用蚀刻工艺来去除，如图3K中图示的。导电衬垫171，其可以包括诸如屏障层和种子层之类的多个层，可以在没有附加的掩蔽步骤的情况下被蚀刻，因为填充金属172和第二填充金属173在导电衬垫171的蚀刻期间的小量蚀刻是可接受的。
参照图3L，可以沉积仅暴露电接触件的保护层174。保护层174在一个示例中可以包括酰亚胺层。
常规器件具有跨整个器件的厚功率金属。功率金属的厚层引入与底层通孔（例如，通孔层级中的多个通孔40）的界面处的大应力。这样的高应力可以导致与所述多个通孔40分层。有利地，本发明的实施例避免由于厚功率金属所致的分层问题。这是因为如以上所描述的，第二填充金属173仅形成在第二区2中而不在第一区1中。相应地，在各种实施例中，半导体器件的大区域不具有较厚的第二填充金属173。较低量的功率金属减小器件中的高应力区域，并且因而导致较少的由于厚功率金属的分层所致的故障。
图4A-4E图示用于制造半导体器件的依照可替换实施例的处理的各种阶段期间的半导体器件的横截面视图。本发明的实施例还可以应用于减法沉积工艺，如使用图4A-4E进一步描述的。
该实施例遵循直至图3G的在先实施例。例如，工艺步骤可以类似于图3A-3G中图示的实施例。随后，代替沉积和图案化另一抗蚀剂层，而去除第二抗蚀剂层181。
第二抗蚀剂层181的去除之后是第二导电衬垫201的沉积。类似于以上描述的在先导电衬垫，第二导电衬垫201可以包括多个层。类似于之前所描述的导电衬垫，第二导电衬垫201可以例如包括扩散屏障层和铜种子层以用于后续电化学沉积。在一个实施例中，第二导电衬垫201包括通过物理气相沉积（PVD）沉积的钨钛的扩散屏障层以及随后的包括铜的种子层。
第二导电衬垫201在各种实施例中沉积为包层（blanket layer）。第三填充金属202沉积在第二导电衬垫201之上。第三填充金属202在一个实施例中可以包括铜并且可以被电镀。在另一实施例中，第二导电衬垫201可以包括扩散屏障并且随后是铝的沉积。
诸如化学机械抛光工艺之类的平面化工艺可以用于在沉积第三填充金属202之后形成大体平面的表面。
参照图4B，在第三填充金属202之上沉积第四抗蚀剂层203。第四抗蚀剂层203被图案化并且去除未覆盖在第二着陆焊盘142上面的抗蚀剂材料以便暴露第三填充金属202。
如接下来在图4C中图示的，使用蚀刻工艺去除所暴露的第三填充金属202。蚀刻工艺在一个实施例中可以是各向异性蚀刻工艺诸如反应离子蚀刻，或者在基于铜的金属层的情况下可以是湿法蚀刻工艺，因为可能难以利用等离子体蚀刻铜。蚀刻工艺可以设计成在第二导电衬垫201处停止，如图4C中所图示的。
蚀刻工艺还可以创建第四抗蚀剂层203下方的某种底切。然而，因为焊盘的宽度中的变化极小，所以横向底切将在第二区2中的焊盘之间是一致的并且可以被容易地补偿。因为仅去除类似成形的焊盘，所以蚀刻工艺更加容易。相比之下，如果还必须使用蚀刻工艺图案化细间距结构，则需要非常小的容限。
相应地，在一个或多个实施例中，由于第三填充金属202不用于电连接性，针对第三填充金属202的设计要求则松懈得多。因此，甚至减法工艺可以用于沉积第三填充金属202。
参照图4D，使用例如另一蚀刻工艺来去除所暴露的第二导电衬垫201。在一个实施例中，第三填充金属202和第二导电衬垫201可以使用常见工艺来去除。如接下来在图4E中图示的，可以去除第四抗蚀剂层203。
相应地，通过不同金属在不同设计布局中的堆叠进行的多层沉积现在使得能够顺序沉积用于细间距设计和接触件的薄层，随后沉积直接在需要冷却的芯片区域之上的较厚层。
另外的处理继续，如早前的实施例中所描述的，例如继续保护层的沉积。
已经在具体上下文（即沉积具有不同厚度的导电焊盘）中关于各种实施例描述了本发明。然而，本发明的实施例还可以应用于其他实例，在所述其他实例中去除金属或其他材料的厚层而不损害相邻结构。类似地，本发明的实施例可以应用于其他工艺，诸如用于形成重分布线的晶片级工艺，该重分布线连接片上系统器件中的相邻电路。例如，功率器件的重分布线在一个实施例中可以比标准器件的重分布线更厚。
如在各种实施例中所描述的，包括金属的材料可以例如是纯金属、多孔金属、金属合金、金属化合物、金属间化合物及其他，即包括金属原子的任何材料。
虽然已经参照说明性实施例描述了该发明，但是该描述不意图以限制性含义来解释。说明性实施例的各种修改和组合，以及本发明的其他实施例，在参照本描述时对于本领域技术人员而言将是明显的。作为说明，图1-4中描述的实施例可以在各种实施例中与彼此组合。因而意图在于，所附权利要求涵盖任何这样的修改或实施例。

Claims (20)

1.一种用于制造半导体器件的方法，所述方法包括：
在第一区中在第一着陆焊盘之上以及在第二区中在第二着陆焊盘之上形成导电衬垫；
在形成于导电衬垫之上的抗蚀剂层内的第一开口内沉积第一导电材料，第一导电材料满溢以形成第一焊盘以及第二焊盘的第一层；
在第一导电材料之上沉积第二抗蚀剂层；
图案化第二抗蚀剂层以形成暴露第二焊盘的第一层而不暴露第一焊盘的第二开口；以及
在第二焊盘的第二层之上沉积第二导电材料。
2.权利要求1所述的方法，其中第一导电材料是与第二导电材料不同类型的材料。
3.权利要求1所述的方法，其中第二导电材料比第一导电材料更加多孔。
4.权利要求1所述的方法，其中第二导电材料具有与第一导电材料不同的组成。
5.权利要求1所述的方法，还包括：
去除第一抗蚀剂层和第二抗蚀剂层；以及
去除在去除第一抗蚀剂层和第二抗蚀剂层之后暴露的导电衬垫。
6.权利要求1所述的方法，其中导电衬垫包括扩散屏障层和种子层。
7.权利要求1所述的方法，还包括在沉积第二导电材料之后退火。
8.权利要求1所述的方法，还包括：
在第二导电材料之上沉积第三抗蚀剂层；
图案化第三抗蚀剂层以形成暴露第二焊盘的第二导电材料而不暴露第一焊盘的第三开口；以及
在第二焊盘的第二导电材料之上沉积第三导电材料。
9.权利要求1所述的方法，还包括利用酰亚胺层涂敷所暴露的第二导电材料和第一导电材料。
10.一种用于制造半导体器件的方法，所述方法包括：
在第一区中在第一着陆焊盘之上以及在第二区中在第二着陆焊盘之上形成导电衬垫；
在导电衬垫之上沉积抗蚀剂层；
图案化抗蚀剂层以在抗蚀剂层中形成第一开口；
在第一开口内沉积第一导电材料，第一导电材料满溢以形成第一焊盘以及第二焊盘的第一层；
在第一导电材料之上沉积蚀刻停止衬垫；
在蚀刻停止衬垫之上沉积第二导电材料；以及
蚀刻第二导电材料和蚀刻停止衬垫以形成第二焊盘，其中第二焊盘包括第一导电材料层和第二导电材料层。
11.权利要求10所述的方法，其中第一导电材料是与第二导电材料不同类型的材料。
12.权利要求10所述的方法，其中第二导电材料比第一导电材料更加多孔。
13.权利要求10所述的方法，其中第二导电材料具有与第一导电材料不同的组成。
14.权利要求10所述的方法，还包括利用酰亚胺层涂敷所暴露的第二导电材料和第一导电材料。
15.一种半导体器件，包括：
衬底中的第一区，所述第一区包括晶体管；
衬底中的第二区，所述第二区包括功率晶体管，功率晶体管是用于向第一区中的晶体管提供功率的电路的部分；
设置在第一区之上的第一焊盘，第一焊盘耦合到第一区中的晶体管；以及
设置在第二区之上的第二焊盘，第二焊盘耦合到第二区中的功率晶体管，其中第一焊盘包括第一金属层的第一部分，其中第二焊盘包括第一金属层的第二部分和设置在第一金属层的第二部分之上的第二金属层的层，其中第一金属层包括第一导电材料，并且第二金属层包括第二导电材料，并且其中第二金属层的层具有比第一金属层的第二部分更小的覆盖区。
16.权利要求15所述的器件，其中第一导电材料是与第二导电材料不同类型的材料。
17.权利要求15所述的器件，其中第二导电材料比第一导电材料更加多孔。
18.权利要求15所述的器件，其中第二导电材料具有与第一导电材料不同的组成。
19.权利要求15所述的器件，其中第二金属层包括第一外侧壁和相对的第二外侧壁，其中第一外侧壁偏离第一金属层的第二部分的对应第一外侧壁，并且其中第二外侧壁偏离第一金属层的第二部分的对应第二外侧壁。
20.权利要求15所述的器件，还包括：
涂敷第二金属层的层的主外表面的保护层。
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