CN107342270B - 电子组件的系统级封装 - Google Patents

电子组件的系统级封装 Download PDF

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CN107342270B
CN107342270B CN201610826441.6A CN201610826441A CN107342270B CN 107342270 B CN107342270 B CN 107342270B CN 201610826441 A CN201610826441 A CN 201610826441A CN 107342270 B CN107342270 B CN 107342270B
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metal
circuit
redistribution
inverted
redistribution circuit
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CN107342270A (zh
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胡迪群
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Abstract

本发明公开了一种电子组件的系统级封装，芯片以封装胶体包裹，第一电路重新分配层直接制作于封装胶体的底侧；第二电路重新分配层直接制作于第一电路重新分配层的底侧；第一电路重新分配层以第一组倒T型金属，电性耦合至芯片的底侧金属；第二电路重新分配层以第二组倒T型金属，电性耦合至第一电路重新分配层的底侧金属。本发明整个封装内部不使用焊锡球于的电性组件之间，也不使用中介层(interposer)于芯片和封装基材之间，不使用独立的系统板(system board)，不使用独立的封装基材(discrete package substrate)，也不使用独立的底部填充材料(underfill)。

Description

电子组件的系统级封装
技术领域
本发明涉及一种电子封装系统，特别是一种系统级的电子封装系统(system inpackage,SiP)。
背景技术
图1显示一个习知技艺。
图1显示芯片101、102设置于一个传统的电子系统封装的顶侧，三组焊锡球141、142、143被使用于该系统封装之中，分别电性耦合两个独立组件。复数个第一组焊锡球141电性耦合芯片101、102至独立的硅中介层(silicon interposer)11，第二组复述个焊锡球142电性耦合硅中介层11至独立的封装基材(package substrate)12，第三组复数个焊锡球143电性耦合封装基材12至独立的系统板(system board)13。
复数个输出/输入(I/O)焊垫103设置于芯片101、102的底侧，硅中介层11具有核心硅基材110，复数个纵向导通金属(through silicon via,TSV)171穿过核心硅基材110，作为上层电路重新分配层(redistribution layer,RDL)111和下层电路重新分配层(RDL)112之间的电性耦合；上层电路重新分配层111设置于核心硅基材110的顶部，下层电路重新分配层112设置于核心硅基材110的底部。复数个第一组焊锡球141设置于芯片的I/O焊垫103与上层电路重新分配层RDL 111之间。
封装基材12设置于硅中介层11的下方，封装基材12具有核心基材120，核心基材120系由层压板(laminates)与预浸材料(prepregs)所构成。复数个层压板纵向导通金属(through laminate via,TLV)172，穿过核心基材120。上层电路重新分配层RDL 121设置于在核心基材120的顶侧，下层电路重新分配层RDL 122设置于核心基材120的底侧。第二组复数个焊锡球142设置于硅中介层11与封装基材12之间，层压板纵向导通金属TLV172设置于上层电路重新分配层RDL 121和下层电路重新分配层122之间。
系统板13设置于封装基材12的底部，系统板13有一个由层压板和预浸材料所构成的的核心基材130，复数个层压板纵向导通金属(TLV)173，穿过核心基材130，上层电路重新分配层RDL 131设置于核心基板130的顶侧，下层电路重新分配层RDL 132设置于核心基材130的底侧，第三组复数个焊锡球154设置于封装基材12和系统板13之间，层压板纵向导通金属(TLV)173电性耦合上层电路重新分配层RDL 131与下层电路重新分配层RDL 132。
第一底部填充材料151被填充到芯片101,102和硅中介层11的空间中，第二底部填充材料152填充到硅中介11和封装基材12之间的空间中，第三底部填充材料153填充到封装基材12和系统板13之间的空间中。
习知技艺使用三组复数个焊锡球141、142、143作为独立组件之间的电性耦合，用以联接相邻堆栈的两个电气组件。习知技艺还采用了独立的硅中介层11作为芯片101、102和封装基材12之间的电性耦合。习知技艺也采用了独立的系统板13，且以第三组复数个焊锡球154作为封装基材12和系统板13之间的电性耦合。习知技艺进一步采用了三组底部填充材料151、152、153，用于填充增强乡堆栈的两个独立的电气组件的可靠性。
习知技艺是一个庞大复杂的多个独立组件相互连接的电子系统，不但制程复杂且可靠度降低。今日，响应于电子产品的轻、薄、短、小的消费需求，一个新的可靠的电子系统需求一直都被研发人员所渴望开发的。
发明内容
针对现有技术的上述不足，根据本发明的实施例，希望提供一种结构简化、可靠性提高，不必使用独立的焊锡球(discrete solder ball)、中介层(discrete interposer)、封装基材(discrete package substrate)、底部填充材料(underfill)和系统电路板(discrete system circuit board)等电子组件(discrete electronic elements)的系统级封装(SIP)。
根据实施例，本发明提供的一种电子组件的系统级封装，其创新点在于，包括至少一个芯片、封装胶体、第一重新分配电路和第二重新分配电路，
芯片具有复数个输入/输出焊垫；
封装胶体包裹于芯片外部；
第一重新分配电路依据第一设计准则制作，设置于封装胶体的底侧；第一重新分配电路具有第一上层倒T型金属以及第一下层倒T型金属；经由第一上层倒T型金属电性耦合至芯片的输入/输出焊垫；第一重新分配电路向下扇出，使得第一下层倒T型金属具有一个密度低于第一上层倒T型金属；
第二重新分配电路依据第二设计准则制作，设置于第一重新分配电路的底侧；第二重新分配电路具有第二上层倒T型金属与第二下层倒T型金属；第二重新分配电路向下扇出，使得第二下层倒T型金属具有一个密度低于第二上层倒T型金属；
第二重新分配电路经由第二上层倒T型金属电性耦合至第一重新分配电路的第一下层倒T型金属的底侧；
第二重新分配电路的任一导线的厚度与宽度，大于第一重新分配电路的任一导线的厚度与宽度。
根据实施例，本发明提供的一种电子组件的系统级封装方法，包括如下步骤：
准备至少一个芯片；
使用封装胶体包裹所述之至少一个芯片；
制作第一重新分配电路于封装胶体下方；
制作第二重新分配电路于第一重新分配电路下方，制作完成系统级封装，其中：
第一重新分配电路设置于封装胶体的底侧；第一重新分配电路具有第一上层倒T型金属与第一下层倒T型金属；经由第一上层倒T型金属电性耦合至芯片的输入/输出端(输入/输出焊垫)；第一重新分配电路向下扇出，使得第一下层倒T型金属具有一个密度低于第一上层倒T型金属；
第二重新分配电路设置于第一重新分配电路的底侧；第二重新分配电路具有第二上层倒T型金属与第二下层倒T型金属；第二重新分配电路向下扇出，使得第二下层倒T型金属具有一个密度低于第二上层倒T型金属；
第二重新分配电路经由第二上层倒T型金属电性耦合至第一重新分配电路的第一下层倒T型金属；
第二重新分配电路的任一导线的厚度与宽度，大于第一重新分配电路的任一导线的厚度与宽度。
相对于现有技术，本发明提供的一种电子组件的系统级封装，芯片以封装胶体包裹，第一电路重新分配层直接制作于封装胶体的底侧；第二电路重新分配层直接制作于第一电路重新分配层的底侧；第一电路重新分配层以第一组倒T型金属电性耦合至芯片的底侧金属；第二电路重新分配层以第二组倒T型金属电性耦合至第一电路重新分配层的底侧金属。整个封装内部不使用焊锡球于的电性组件之间，也不使用中介层(interposer)于芯片和封装基材之间，不使用独立的系统板(system board)，不使用独立的封装基材(discrete package substrate)，也不使用独立的底部填充材料(underfill)。
附图说明
图1显示一个习知技艺的结构示意图。
图2显示本发明的第一实施例的结构示意图。
图3A～3C显示本发明第一实施例的制程图。
图4显示本发明的第二实施例的结构示意图。
图5显示本发明的第三实施例的结构示意图。
图6显示本发明的第四实施例的结构示意图。
图7显示图6的一个应用实施例的俯视图。
图8显示本发明的第五实施例的结构示意图。
图9显示图8的一个应用实施例的顶视图。
其中：101、102为芯片；103为输入/输出(I/O)焊垫；110为核心硅基材；11为硅中介层；12为封装基材；13为系统板；141、142、143为焊锡球；151、152、152为底部填充；171为纵向金属，TSV为硅；172、173为纵向导通金属，TLV为层压；21、22为RDL；211、221为重新分配电路；212、222为介电层；215、225为纵向导通金属；255为延伸单元；26为封装胶体；271为软性电路板；272为金手指；28为被动组件；31E、311E、312E、313E、314E、315E为第一延伸单元；32E、321E、322E、323E、324E、325E为第二延伸单元；31P、311P、312P、313P、314P、315P为金属接点；32P、321P、322P、323P、324P、325P为金属接点；RDL111为上层电路重新分配层；RDL112为下层电路重新分配层；RDL121为上层电路重新分配层；RDL122为下层电路重新分配层；RDL131为上层电路重新分配层；RDL132为下层电路重新分配层；RDL31为上层电路重新分配层；RDL32为下层电路重新分配层。
具体实施方式
下面结合附图和具体实施例，进一步阐述本发明。这些实施例应理解为仅用于说明本发明而不用于限制本发明的保护范围。在阅读了本发明记载的内容之后，本领域技术人员可以对本发明作各种改动或修改，这些等效变化和修改同样落入本发明权利要求所限定的范围。
本发明以下实施例揭露一个结构简化、可靠性提高的电子产品的系统级封装(SIP)，本发明以下实施例的系统级封装，不必使用下列独立的电子组件(discreteelectronic elements)：焊锡球、中介层(discrete interposer)、封装基材、系统电路板(discrete systemcircuit board)以及底部填充材料(discrete underfill)。
第一电路重新分配层RDL 21系依据IC设计准则所制作的，用以整合习知技艺的复数个第一组焊锡球141以及硅中介层1。第二电路重新分配层RDL 22系依据PCB设计准则所制作的，用以整合习知技艺的第二组复数个焊锡球142、封装基材12、第三组复数个焊锡球143以及系统板13。本发明以下实施例揭露一种电子组件的厚度极薄的系统级封装。
图2显示本发明的第一实施例。
图2显示一个系统级封装，它包括芯片101、102设置于系统级封装的顶侧。复数个输入/输出(I/O)103设置于每个芯片101、102的底侧；封装胶体26封装了芯片101、102的至少四个侧面和底侧。
第一电路重新分配层RDL 21具有埋设在第一介电层212的第一重新分配电路211，第一重新分配电路211系依据IC设计准则所制作的；第一重新分配电路211设置于封装胶体26的底侧，第一重新分配电路211的顶端，经由复数个第一组纵向导通金属215，电性耦合至芯片的I/O焊垫103。
第二电路重新分配层RDL 22具有埋设于第二介电层222的第二个重新分配电路221，第二个重新分配电路221是依据PCB设计准则所制作的；第二重新分配电路221设置于第一重新分配电路211的底侧；第二重新分配电路221的顶侧，经由第二组复数个纵向导通金属225，电性耦合至第一重新分配电路211。
封装胶体26的顶表面与芯片101、102的顶表面为共平面，上方可以安置散热单元。
参考图2，每一个纵向金属215、225与它的底部的扁平金属，整体形成一个倒T型金属1T、2T。由于倒T型金属1T、2T的纵向金属215、225与其底部扁平金属是在相同的一个金属制程中所形成的，所以倒T型金属1T、2T是单一金属，也就是说，纵向金属215、225和其底部的扁平金属之间的金属材料分布均匀，于剖面图中，不存在有分隔线，且每个纵向金属215、225在剖面图中，呈现上窄下宽的梯型形状。
图3A～3C显示本发明第一实施例的制造过程。
图3A显示：封装胶体26包装复数个芯片101、102；其中，一个临时附加电路板(图中未显示)设置于芯片101、102的顶侧，临时附加电路板并未于图式中绘制，是为了简化本说明书。
图3B显示：第一电路重新分配层RDL 21制作于封装胶体26下方；第一电路重新分配层RDL 21具有埋设在第一介电层212的第一重新分配电路211。
图3C显示：第二电路重新分配层RDL 22制作于第一电路重新分配层RDL 21的底侧；第二电路重新分配层RDL 22具有埋设于第二介电层222的第二重新分配电路221。
图4显示本发明的第二实施例。
图4显示复数个第一组金手指251，设置于第二介电层222的底侧，且电性耦合至第二重新分配电路221；复数个第一组金手指251作为系统封装SiP的输入/输出(I/O)的接点。
软性电路板271单独制备完成，复数个金手指272设置于软性电路板271左边；复数个金手指272系对应于复数个金手指251而设置，软性电路板271的右端电性耦合至电源(power)。
图5显示本发明的第三实施例。
图5显示第二电路重新分配层RDL 22的左侧延伸突出于封装胶体26的左侧。图5显示一个延伸单元255系由第二电路重新分配层RDL 22的向左边延伸而成，复数个第一组金手指251设置于延伸单元255下方；第二组复数个金手指252设置于延伸单元255的顶侧；金手指251、252可以电性耦合至外部一个金手指插座(图中未显示)或是其它电性耦合器(图中未显示)，使得本发明的系统级封装SIP可以电性耦合至外部的其他电子组件。图6进一步显示，至少一个被动组件28，例如电阻器、电容器、电感器或其它电子组件(图中未显示)可以选择性地设置于第二电路重新分配层RDL 22的底侧，并电性耦合至第二重新分配电路221。
图6显示本发明的第四实施例。
图6显示两个芯片101、102埋设于封装胶体26内；第一电路重新分配层RDL 31设置于封装胶体26的底面；第一电路重新分配层RDL 31具有第一重新分配电路211，第一重新分配电路211埋设于第一介电层212中；第一重新分配电路211具有多个第一倒T型金属；第一重新分配电路211的上端倒T型金属1T，电性耦合到芯片101、102的底部金属接点，即输入/输出焊垫。
第二电路重新分配层RDL 32设置于第一电路重新分配层RDL 31的下方，第二电路重新分配层RDL 32具有第二重新分配电路221埋设于第二介电层222中；第二重新分配电路221具有多个第二倒T型金属2T，第二重新分配电路221的上层多个第二倒T型金属2T电性耦合到第一重新分配电路211的底侧金属。
第一电路重新分配层RDL 31具有至少一个延伸单元31E延伸超过封装胶体26的一个对应边，多个金属接点31P设置于延伸单元31E的一个终端上，用以电性耦合到一个外部的电子装置，例如：麦克风、电源、音量键、扬声器、以及摄像头...等。
第一重新分配电路211是依据第一设计准则制作的，例如集成电路设计准则；第二重新分配电路221是依据第二设计准则制作的，例如印刷电路板设计准则；因此，比对于第一重新分配电路211，第二重新分配电路221中的每一个电路系较厚和较宽；第二倒T型金属2T的设置密度，小于第一倒T型金属1T的设置密度，以便电路向下展开。
应用实施例
图7显示图6的一个应用实施例的俯视图。
图7显示图6的一个应用实施例中，例如，应用于一个可携式电子装置的顶视图。图7显示，从顶部观察时，两个芯片101、102埋设于封装胶体26内。
第一电路重新分配层RDL31的第一延伸单元311E在左边延伸至左上方，多个金属接点311P设置于第一延伸单元311E的端点处，用以电性耦合到一个外部的电子装置，例如，音量键等。
第一电路重新分配层RDL31的第二延伸单元312E在上方中间延伸向上，多个金属接点312P设置于第二延伸单元312E的端点处，用以电性耦合到一个外部的电子装置，例如，扬声器等。
第一电路重新分配层RDL31的第三延伸单元313E在上方右边向右上方延伸，多个金属接点313P设置于第三延伸单元313E的端点处，用以电性耦合到一个外部的电子装置，例如，照相机等。
第一电路重新分配层RDL31的第四延伸单元314E在左边向左延伸，多个金属接点314P设置于第四延伸单元314E的端点处，用以电性耦合到一个外部的电子装置，例如，麦克风。
第一电路重新分配层RDL31的第五延伸单元315E在右边向右延伸，多个金属接点315P设置于第五扩展315E的端点处，用以电性耦合到一个外部的电子装置，例如，一个电源。
图8显示本发明的第五实施例。
图8显示两个芯片101、102埋设于封装胶体26；第一电路重新分配层RDL 31设置于封装胶体26的底面；第一电路重新分配层RDL 31具有埋设于第一介电层212的第一重新分配电路211；第一重新分配电路211的最上层的多个第一倒T型金属1T电性耦合到芯片101的底侧输入输出焊垫103；第二电路重新分配层RDL 32设置于第一电路重新分配层RDL 31的底侧；第二电路重新分配层RDL 32具有埋设于第二介电层222的第二重新分配电路221。第二重新分配电路221的上层的多个第二倒T型金属2T电性耦合至第一重新分配电路211的底侧金属。
第二电路重新分配层RDL 32具有至少一个延伸单元32E延伸超过封装胶体26的一个对应边，多个金属接点32P设置于延伸单元32E的一个终端上，用以电性耦合到一个外部的电子装置如麦克风、电源、音量键、扬声器或是摄像头等。
应用实施例
图9显示图8的一个应用实施例的顶视图。
图9显示图8的一个应用实施例，例如，应用于一个可携式电子装置的顶视图。图9所示，从顶部观察时，两个芯片101、102埋设于封装胶体26中。
第二电路重新分配层RDL32的第一延伸单元321E在左边延伸至左上方，多个金属接点321P设置于第一延伸单元321E的端点处，用以电性耦合到一个外部的电子装置，例如，音量键等。
第二电路重新分配层RDL32的第二延伸单元322E在上方中间延伸向上，多个金属接点322P设置于第二延伸单元322E的端点处，用以电性耦合到一个外部的电子装置，例如，扬声器等。
第二电路重新分配层RDL32的第三延伸单元323E在上方右边向右上方延伸，多个金属接点323P设置于第三延伸单元323E的端点处，用以电性耦合到一个外部的电子装置，例如，照相机等。
第二电路重新分配层RDL32的第四延伸单元324E在左边向左延伸，多个金属接点324P设置于第四延伸单元324E的端点处，用以电性耦合到一个外部的电子装置，例如，麦克风。
第二电路重新分配层RDL32的第五延伸单元325E在右边向右延伸，多个金属接点325P设置于第五扩展325E的端点处，用以电性耦合到一个外部的电子装置，例如，一个电源。

Claims (15)

1.一种电子组件的系统级封装，其特征是，包括至少一个芯片、封装胶体、第一重新分配电路和第二重新分配电路，
芯片具有复数个输入/输出焊垫；
封装胶体包裹于芯片外部；
第一重新分配电路依据第一设计准则制作，设置于封装胶体的底侧；第一重新分配电路具有第一上层倒T型金属以及第一下层倒T型金属；经由第一上层倒T型金属电性耦合至芯片的输入/输出焊垫；第一重新分配电路向下扇出，使得第一下层倒T型金属具有一个密度低于第一上层倒T型金属；
第二重新分配电路依据第二设计准则制作，设置于第一重新分配电路的底侧；第二重新分配电路具有第二上层倒T型金属与第二下层倒T型金属；第二重新分配电路向下扇出，使得第二下层倒T型金属具有一个密度低于第二上层倒T型金属；
第二重新分配电路经由第二上层倒T型金属电性耦合至第一重新分配电路的第一下层倒T型金属的底侧；
第二重新分配电路的任一导线的厚度与宽度，大于第一重新分配电路的任一导线的厚度与宽度。
2.如权利要求1所述之电子组件的系统级封装，其特征是，所述之倒T型金属由剖面图观察为一次成型，上端纵向金属与下端横向金属之间没有分隔线。
3.如权利要求1所述之电子组件的系统级封装，其特征是，所述之封装胶体的顶表面与芯片的顶表面为共平面。
4.如权利要求1所述之电子组件的系统级封装，其特征是，进一步包含第一介电层、第二介电层和复数个第一组金手指，第一介电层埋设所述之第一重新分配电路，构成第一电路重新分配层；第二介电层埋设所述之第二重新分配电路，构成第二电路重新分配层；复数个第一组金手指设置于第二介电层的底部。
5.如权利要求4所述之电子组件的系统级封装，其特征是，进一步包含延伸单元和第二组复数个金手指，延伸单元系第二电路重新分配层延伸超出封装胶体的一个对应的侧边所构成；第二组复数个金手指设置于所述之延伸单元的顶侧。
6.如权利要求5所述之电子组件的系统级封装，其特征是，进一步包含软性电路板单元和第三组复数个金手指，第三组复数个金手指设置于所述之软性电路板单元；第三组复数个金手指对应于所述之复数个第一组金手指，且适于电性耦合至复数个第一组金指。
7.如权利要求5所述之电子组件的系统级封装，其特征是，进一步包含复数个底部金属垫，所述之复数个底部金属垫设置于第二重新分配电路的底侧。
8.如权利要求7所述之电子组件的系统级封装，其特征是，进一步包含复数个开口，所述之复数个开口设置于所述之第二介电层的底侧，每个开口分别裸露第二重新分配电路的一个对应的底部金属垫的底表面。
9.如权利要求8所述之电子组件的系统级封装，其特征是，进一步包含至少一个被动组件，所述之被动组件电性耦合至底部金属垫。
10.如权利要求1所述之电子组件的系统级封装，其特征是，所述之倒T型金属由上端纵向金属与下端水平金属所构成，且于剖面图中，上端纵向金属呈上窄下宽的形状。
11.如权利要求4所述之电子组件的系统级封装，其特征是，进一步包含延伸单元和复数个金属接点，延伸单元由第一电路重新分配层的一边延伸出来，延伸超出封装胶体的一个对应的侧边；复数个金属接点设置于延伸单元的端点处，提供外部电子组件电性耦合之用。
12.如权利要求11所述之电子组件的系统级封装，其特征是，所述之外部电子组件为控制按键、扬声器、照相机、麦克风或电源。
13.如权利要求4所述之电子组件的系统级封装，其特征是，进一步包含延伸单元和复数个金属接点，延伸单元由第二电路重新分配层的一边延伸出来，延伸超出封装胶体的一个对应的侧边；复数个金属接点设置于延伸单元的端点处，提供外部电子组件电性耦合之用。
14.如权利要求13所述之电子组件的系统级封装，其特征是，所述之外部电子组件为控制按键、扬声器、照相机、麦克风或电源。
15.一种电子组件的系统级封装方法，其特征是，包括如下步骤：
准备至少一个芯片；
使用封装胶体包裹所述之至少一个芯片；
制作第一重新分配电路于封装胶体下方；
制作第二重新分配电路于第一重新分配电路下方，制作完成系统级封装，其中：
第一重新分配电路设置于封装胶体的底侧；第一重新分配电路具有第一上层倒T型金属与第一下层倒T型金属；经由第一上层倒T型金属电性耦合至芯片的输入/输出端；第一重新分配电路向下扇出，使得第一下层倒T型金属具有一个密度低于第一上层倒T型金属；
第二重新分配电路设置于第一重新分配电路的底侧；第二重新分配电路具有第二上层倒T型金属与第二下层倒T型金属；第二重新分配电路向下扇出，使得第二下层倒T型金属具有一个密度低于第二上层倒T型金属；
第二重新分配电路经由第二上层倒T型金属电性耦合至第一重新分配电路的第一下层倒T型金属；
第二重新分配电路的任一导线的厚度与宽度，大于第一重新分配电路的任一导线的厚度与宽度。
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