CN107306477B - 印刷电路板及其制造方法和半导体封装件 - Google Patents

印刷电路板及其制造方法和半导体封装件 Download PDF

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CN107306477B
CN107306477B CN201710099075.3A CN201710099075A CN107306477B CN 107306477 B CN107306477 B CN 107306477B CN 201710099075 A CN201710099075 A CN 201710099075A CN 107306477 B CN107306477 B CN 107306477B
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layer
pattern
conductive
insulating layer
aluminum
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CN107306477A (zh
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朴寿财
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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Abstract

提供了一种印刷电路板(PCB)及其制造方法和一种半导体封装件，所述印刷电路板包括：绝缘层，具有上表面和与上表面相对的下表面；第一导电图案，在绝缘层的上表面上；第二导电图案，在绝缘层的下表面上；铝图案，覆盖第一导电图案的上表面的至少一部分；以及第一钝化层，覆盖第一导电图案的侧面的至少一部分，并且防止进入第一导电图案中的扩散。

Description

印刷电路板及其制造方法和半导体封装件
本申请要求于2016年04月22日在韩国知识产权局提交的第10-2016-0049384号韩国专利申请的优先权和权益，该韩国专利申请的内容通过引用全部包含于此。
技术领域
本发明构思的实施例针对一种印刷电路板(PCB)和一种半导体封装件，更具体地，针对一种具有使用铝对其焊盘执行的表面处理的PCB和一种半导体封装件。
背景技术
随着电子组件已经变得大规模，已经开发了印刷电路板(PCB)的各种表面处理技术。金属镀覆技术用来处理PCB的表面。另外，由于消费者的需求，目前电子系统具有高性能功能和更小的尺寸，这导致连接到电子系统中包括的PCB的连接端子的数量的增加以及连接端子的间隔和尺寸的减小。可以通过使连接端子的间隔和尺寸减小来减小PCB的总面积。因此，已经研究了诸如封孔、半加成工艺(SAP)和改进的半加成工艺(MSAP)的工艺。
发明内容
本发明构思的实施例可以提供一种减少工艺成本并且改善键合工艺可靠性的印刷电路板(PCB)。
本发明构思的实施例也可以提供一种减少工艺成本并且改善键合工艺可靠性的半导体封装件。
根据本发明构思的实施例，提供了一种印刷电路板(PCB)，所述印刷电路板包括：绝缘层，包括上表面和与上表面相对的下表面；第一导电图案，在绝缘层的上表面上；第二导电图案，在绝缘层的下表面上；铝图案，覆盖第一导电图案的上表面的至少一部分；以及第一钝化层，覆盖第一导电图案的侧面的至少一部分，并且防止进入第一导电图案中的扩散。
根据本发明构思的另一实施例，提供了一种半导体封装件，所述半导体封装件包括：封装基底；半导体芯片，在封装基底上；以及键合引线，将封装基底和半导体芯片连接，其中，封装基底包括绝缘层、在绝缘层的上表面上并且包括铜的第一布线图案、在第一布线图案上并且包括与第一布线图案的材料不同的材料的第二布线图案以及在第一布线图案的侧面上并且防止进入第一布线图案中的扩散的有机钝化层。
根据本发明构思的另一实施例，提供了一种用于制造印刷电路板(PCB)的方法，所述方法包括：提供包括载体层、脱模层和铝层的载体基底；在载体基底上形成第一导电层；在第一导电层上形成绝缘层和第二导电层；形成穿透绝缘层并且将第一导电层和第二导电层电连接的接触塞；通过将脱模层分离为两个子层来将载体层和铝层彼此分离，其中，第一子层与载体层保留在一起，第二子层与铝层保留在一起；去除分离的载体层和脱模层的第一子层；通过分别将铝层、第一导电层和第二导电层图案化并且将脱模层的第二子层从铝层去除来形成铝图案、第一导电图案和第二导电图案；分别在绝缘层的上表面和绝缘层的与上表面相对的下表面上形成第一阻焊层和第二阻焊层，其中，第一阻焊层包括暴露第一导电图案的一部分和铝图案的一部分的至少一个开口；以及通过有机可焊性防腐剂(OSP)表面处理在第一导电图案和第二导电图案的各自的暴露的表面上形成第一钝化层和第二钝化层。
附图说明
图1是根据实施例的印刷电路板(PCB)的剖视图。
图2是根据实施例的图1的部分A的放大的剖视图。
图3A至图3H是示出根据实施例的制造PCB的方法的剖视图。
图4是根据实施例的PCB的一部分的放大的剖视图。
图5是根据实施例的PCB的一部分的放大的剖视图。
图6A至图6D是示出根据实施例的制造PCB的方法的剖视图。
图7是根据实施例的PCB的剖视图。
图8是根据实施例的图7的部分B的放大的剖视图。
图9A至图9D是示出根据实施例的制造PCB的方法的剖视图。
图10是根据实施例的使用PCB的半导体封装件的剖视图。
具体实施方式
图1是根据实施例的印刷电路板(PCB)1a的剖视图。图2是根据实施例的图1的部分A的放大的剖视图。
参照图1和图2，根据实施例的PCB 1a包括具有上表面和与上表面相对的下表面的绝缘层10、第一导电图案100、第二导电图案200、铝图案110、第一钝化层120、第二钝化层220、第一阻焊层130和第二阻焊层230。
根据实施例，绝缘层10包括从酚醛树脂、环氧树脂和聚酰亚胺中选择的至少一种材料。例如，绝缘层10可以包括从阻燃剂4(FR4)、四官能环氧树脂、聚苯醚、环氧树脂/聚苯醚、双马来酰亚胺三嗪(BT)、聚酰胺短纤席材、氰酸酯、聚酰亚胺和液晶聚合物中选择的至少一种材料。在一些实施例中，绝缘层10包括例如聚酯(PET)、聚酯对苯二甲酸酯、氟化乙烯丙烯(FEP)、树脂涂层纸、液态聚酰亚胺树脂、聚萘二甲酸乙二醇酯(PEN)膜等。
根据实施例，第一导电图案100形成在绝缘层10的上表面上。第二导电图案200形成在绝缘层10的下表面上。为了将第一导电图案100和第二导电图案200电连接，形成了穿透绝缘层10的接触塞150。可以构造多个第一导电图案100和多个第二导电图案200。因此，也可以形成多个接触塞150。第一导电图案100可以包括铜(Cu)、镍(Ni)、铝(Al)、金(Au)、铂(Pt)和银(Ag)中的至少一种。例如，第一导电图案100可以包括铜。第二导电图案200可以包括与第一导电图案100的材料相似的材料，但是实施例不限于此。第二导电图案200可以包括与第一导电图案100的材料不同的材料。
根据实施例，铝图案110形成为覆盖第一导电图案100的上表面的至少一部分。铝图案110可以防止第一导电图案100被暴露。在这方面，第一导电图案100的上表面高于绝缘层10的上表面。因此，铝图案110具有从绝缘层10突出的形状。像第一导电图案100一样，也可以构造多个铝图案110。铝具有良好的导电性和低的价格，因此可以替代通常用来处理在基底上形成的焊盘的表面的金、银等。结果，可以减少PCB 1a的制造成本。
根据实施例，铝图案110在与绝缘层10的上表面垂直的方向上的厚度T1小于第一导电图案100在与绝缘层10的上表面垂直的方向上的厚度T2。即，薄的铝图案110可以形成在第一导电图案100的上表面上。然而，为了突显起见，在图1和图2中相对夸大了铝图案110的厚度T1。铝图案110的厚度T1可以为从大约0.1μm至大约1μm。第一导电图案100的厚度T2可以为从大约0.1μm至大于10μm。
根据实施例，第一钝化层120覆盖第一导电图案100的侧面的至少一部分。第一钝化层120可以防止进入第一导电图案100中的扩散。第一钝化层120包括通过有机可焊性防腐剂(OSP)表面处理形成的材料。例如，当第一导电图案100包括铜时，第一钝化层120可以包括可以附着到铜表面并与铜原子化学地结合的有机化合物(诸如苯并三唑、咪唑、苯并咪唑等)。具体地，当第一导电图案100包括铜时，对其执行OSP表面处理的第一钝化层120可以防止在第一导电图案100的表面中发生不希望的氧化反应或者防止表面被损坏。
根据实施例，第一钝化层120在第一导电图案100的侧面上相对薄。第一钝化层120在第一导电图案100的侧面上的厚度T3等于或小于0.5μm。因此，第一导电图案100之间的空间在尺寸上增加，并且工艺可靠性在PCB 1a的引线键合期间增加。
根据实施例，第一阻焊层130形成在绝缘层10上，并且包括开口130a。铝图案110的一部分的上表面通过第一阻焊层130的开口130a暴露。第二阻焊层230形成在绝缘层10的下表面上。在这方面，第二阻焊层230形成为覆盖第二导电图案200的侧面。第一阻焊层130和第二阻焊层230为绝缘层，并且可以包括聚酰亚胺膜、聚酯膜、柔性焊接掩模、感光覆盖层(PIC，photoimageable coverlay)、感光阻焊剂(photoimageable solder resist)等。第一阻焊层130可以保护第一导电图案100并且可以防止在相邻的第一导电图案100之间发生桥接现象，第二阻焊层230可以保护第二导电图案200并且可以防止在相邻的第二导电图案200之间发生桥接现象。
根据实施例，第二钝化层220另外形成在第二导电图案200的不接触第二阻焊层230的下表面上。第二钝化层220覆盖第二导电图案200的下表面的至少一部分。第二钝化层220通过同一工艺包括与第一钝化层120相同的材料，并且可以执行与第一钝化层120相同的功能。
根据实施例，上面描述的PCB 1a具有使用铝对其焊盘执行的表面处理，从而减少工艺成本。PCB 1a也具有在形成于其上的焊盘之间的更大的空间，从而增加电连接的可靠性并且增加键合工艺的可靠性。
图3A至图3H是示出根据实施例的制造PCB的方法的剖视图。
根据实施例，参照图3A，提供了包括载体层20、脱模层30和铝层40的载体基底2a。载体层20具有包括诸如树脂、玻璃纤维等的多个绝缘层的堆叠结构。载体层20可以在将在下面描述的随后的工艺中支撑其它层。
根据实施例，脱模层30包括合金和有机化合物。脱模层30也可以包括粘合层，并且可以形成为非导电膜(NCF)、各向异性导电膜(ACF)、瞬时粘合剂、热固性粘合剂、激光可固化粘合剂、超声可固化粘合剂等。可以通过例如旋涂、绘涂、喷涂等形成粘合层。
可以通过化学沉积、金属溅射、电镀和无电金属镀覆工艺形成铝层40。脱模层30和铝层40在图3A中示出为形成在载体层20的一个表面上，但是实施例不限于此。在其他实施例中，也可以在与脱模层30和铝层40形成在其上的表面相对的表面上形成另一脱模层和另一铝层。
参照图3B，根据实施例，在载体基底2a上形成第一导电层70。例如，可以在载体基底2a的铝层40上形成种子层，可以通过利用种子层作为种子通过镀覆而形成第一导电层70。可以通过浸镀、无电镀、电镀或这些的结合来形成第一导电层70。因此，当种子层包括铜时，第一导电层70包括铜。在一些实施例中，第一导电层70使用包含添加剂的镀覆溶液施加电流。添加剂可以为例如使镀层平整的平整剂、使镀层的颗粒细化的晶粒细化剂、使镀层在被镀覆于其上时的应力减小的应力减小剂或者使镀覆原子很好地粘附至阴极的表面的湿润剂中的至少一种。
参照图3C，根据实施例，在第一导电层70上形成绝缘层10和第二导电层90。在上面参照图1描述了用于形成绝缘层10的材料。绝缘层10具有包括多个层的堆叠结构并且包括布线，这将在下面进行描述。以与第一导电层70相同的方式形成第二导电层90。因此，可以在形成种子层之后通过镀覆来形成第二导电层90。第一导电层70和第二导电层90可以包括相同的材料。例如，第一导电层70和第二导电层90可以包括铜。
参照图3D，根据实施例，形成穿透绝缘层10并将第一导电层70与第二导电层90电连接的接触塞150。通过使用湿法刻蚀或干法刻蚀或者通过机械钻孔或激光钻孔形成接触孔150a并随后通过镀覆工艺使用导电材料填充接触孔150a来形成接触塞150。激光钻孔可以使用例如CO2激光器、钇铝石榴石(YAG)激光器、准分子激光器、Cu蒸气激光器或这些激光器的混合组合。
参照图3E，根据实施例，通过将脱模层30分离为两个子层来将载体层20和铝层40彼此分离。可以通过使用刀片的物理方法、使用分离溶剂的化学方法、使用激光的激光烧蚀等来执行分离工艺。脱模层30的子层30a与载体层20保留在一起。脱模层30的另一子层30b与铝层40保留在一起。去除分离的载体层20和脱模层30的子层30a。
参照图3E和图3F，根据实施例，通过分别将铝层40、第一导电层70和第二导电层90图案化来形成铝图案110、第一导电图案100和第二导电图案200。使用掩模通过蚀刻铝层40、第一导电层70和第二导电层90来形成铝图案110、第一导电图案100和第二导电图案200。在这方面，也从铝层40去除脱模层30的另一子层30b。
参照图3G，根据实施例，在绝缘层10的上表面上形成预备的第一阻焊层130b，在绝缘层10的与上表面相对的下表面上形成第二阻焊层230。预备的第一阻焊层130b覆盖铝图案110的上表面和侧表面两者以及第一导电图案100的侧面。第二阻焊层覆盖第二导电图案200的侧面。
可以通过例如使用丝网印刷或喷墨印刷而利用热固性油墨直接涂覆绝缘层10并且使涂覆的热固性油墨热固化来形成预备的第一阻焊层130b和第二阻焊层230。可选择地，可以通过例如使用网版印刷或喷涂而利用感光阻焊剂完全地涂覆绝缘层10来形成预备的第一阻焊层130b和第二阻焊层230。可以通过例如将聚酰亚胺膜或聚酯膜附着到绝缘层10上的层压法来形成预备的第一阻焊层130b和第二阻焊层230。在上面参照图1描述了第一阻焊层130和第二阻焊层230的材料。
参照图3G和图3H，根据实施例，通过去除预备的第一阻焊层130b的一部分来形成包括开口130a的第一阻焊层130。通过使用曝光和显影去除不必要的部分来形成开口130a。通过开口130a暴露第一导电图案100的一部分和铝图案110的一部分。第一导电图案100和铝图案110的暴露的部分可以用作接触键合引线的焊盘，所述键合引线将PCB与安装在PCB上的半导体芯片或半导体封装件电连接。
根据实施例，分别在第一导电图案100和第二导电图案200的暴露的表面上形成第一钝化层120和第二钝化层220。因此，在第一导电图案100的一部分的侧面上形成第一钝化层120，在第二导电图案200的至少一部分的下表面上形成第二钝化层220。通过OSP表面处理形成第一钝化层120和第二钝化层220。可以同时形成第一钝化层120和第二钝化层220，但是实施例不限于此。
图4是根据实施例的PCB 1b的一部分的放大的剖视图。PCB 1b的这一部分与图1的部分A对应。
参照图4，根据实施例的PCB 1b包括绝缘层10、第一导电图案100、第二导电图案200、铝图案110、第一钝化层120、第二钝化层220、第一阻焊层130、第二阻焊层230和阻挡图案140。
根据实施例，阻挡图案140可以防止因导电材料从第一导电图案100至铝图案110的扩散导致的电导率的减少。阻挡图案140可以包括例如镍(Ni)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、金(Au)、银(Ag)和钨(W)。例如，阻挡图案140可以为包括镍(Ni)的层。
图5是根据实施例的PCB 1c的一部分的放大的剖视图。PCB 1c的这一部分与图1的部分A对应。
参照图5，根据实施例的PCB 1c包括绝缘层10、第一导电图案100、第二导电图案200、铝图案110、第一钝化层120、第二钝化层220、第一阻焊层130、第二阻焊层230、阻挡图案140和氧化物层115。例如，氧化物层115可以为氧化铝(Al2O3)。氧化物层115可以防止铝图案110的另外的氧化和变色，从而改善铝图案110用作焊盘时的可靠性。自然被氧化的铝可以在没有进一步的工艺的情况下有效地保护内部形成的导电材料。
图6A至图6D是示出根据实施例的制造PCB的方法的剖视图。省略了图6A至图6D与图3A至图3H之间的多余描述。
参照图6A，根据实施例，提供包括载体层20、脱模层30、铝层40、阻挡层50和种子层60的载体基底2b。脱模层30、铝层40、阻挡层50和种子层60在图6A中示出为形成在载体层20的一个表面上，但是实施例不限于此。在其它实施例中，可以在与脱模层30、铝层40、阻挡层50和种子层60形成在其上的表面相对的表面上形成另一脱模层、另一铝层、另一阻挡层和另一种子层。种子层60为包括铜(Cu)的铜种子层。
参照图6B，根据实施例，在载体基底2b上形成第一导电层70。利用种子层60作为种子通过镀覆而形成第一导电层70。因此，当种子层60包括铜时，第一导电层70包括铜。
参照图6C，根据实施例，在第一导电层70上形成绝缘层10和第二导电层90。形成穿透绝缘层10并将第一导电层70和第二导电层90电连接的接触塞150。在上面参照图1描述了用于形成绝缘层10的材料。在这方面，第一导电层70、第二导电层90和接触塞150包括相同的材料。例如，第一导电层70、第二导电层90和接触塞150可以包括铜。然而，第一导电层70、第二导电层90和接触塞150不限于此，在其他实施例中可以包括不同的材料。
参照图6C，根据实施例，通过将脱模层30分离为两个子层来将载体层20和铝层40彼此分离。脱模层30的子层30a与载体层20保留在一起。脱模层30的另一子层30b与铝层40保留在一起。去除分离的载体层20和脱模层30的子层30a。
参照图6C和6D，根据实施例，通过分别将铝层40、阻挡层50、第一导电层70和第二导电层90图案化来形成铝图案110、阻挡图案140、第一导电图案100和第二导电图案200。使用掩模通过蚀刻铝层40、阻挡层50、第一导电层70和第二导电层90来形成铝图案110、阻挡图案140、第一导电图案100和第二导电图案200。在这方面，从铝层40去除脱模层30的另一子层30b。
根据实施例，分别在绝缘层10的上表面和绝缘层10的与上表面相对的下表面上形成第一阻焊层130和第二阻焊层230。第一阻焊层130覆盖铝图案110的上表面和侧面、阻挡图案140的侧面以及第一导电图案100的侧面的至少一部分。第二阻焊层230覆盖第二导电图案200的侧面。
根据实施例，第一阻焊层130包括使第一导电图案100的一部分、阻挡图案140的一部分以及铝图案110的一部分暴露的至少一个开口130a。第一导电图案100、阻挡图案140和铝图案110的暴露的部分可以用作接触键合引线的焊盘，所述键合引线将PCB与安装在PCB上的半导体芯片或半导体封装件电连接。
根据实施例，分别在第一导电图案100和第二导电图案200的暴露的表面上形成第一钝化层120和第二钝化层220。因此，在第一导电图案100的一部分的侧面上形成第一钝化层120，在第二导电图案200的至少一部分的下表面上形成第二钝化层220。通过OSP表面处理形成第一钝化层120和第二钝化层220。
根据实施例，在铝图案110的暴露的表面上形成氧化物层115。氧化物层115可以因铝图案110接触空气而自然地形成。因此，氧化物层115为氧化铝。氧化物层115可以保护铝图案110。
图7是根据实施例的PCB 1d的剖视图。图8是根据实施例的图7的部分B的放大的剖视图。
参照图7和图8，根据实施例的PCB 1d包括绝缘层10a、第一导电图案100、第二导电图案200、铝图案110、第一钝化层120、第二钝化层220、第一阻焊层130、第二阻焊层230、阻挡图案140和氧化物层115。在这方面，绝缘层10a包括第一绝缘层11和第二绝缘层12。第二绝缘层12形成在第一绝缘层11的下部上。在下面省略了图7和图8与图1、图2、图4之间的多余描述。
根据实施例，第三导电图案300形成在第二绝缘层12中。因此，形成穿透第一绝缘层11并且将第一导电图案100和第三导电图案300电连接的第一接触塞160。形成穿透第二绝缘层12并且将第二导电图案200和第三导电图案300电连接的第二接触塞260。绝缘层10a可以包括如图7和图8中示出的两层，但是实施例不限于此。绝缘层10a可以包括附加层，因此可以以各种方式形成接触塞150。
根据实施例，铝图案110在与绝缘层10a的上表面垂直的方向上的厚度小于第一导电图案100在与绝缘层10a的上表面垂直的方向上的厚度。为了突显起见，在图7和图8中相对夸大了铝图案的厚度，这也应用于下面描述的附图。
图9A至图9D是示出根据实施例的制造PCB的方法的剖视图。省略了图9A至图9D与图3A至图3H及图6A至图6D之间的多余描述。
参照图9A，根据实施例，提供包括载体层20、脱模层30、铝层40、阻挡层50和种子层60的载体基底2b。在种子层60上形成第一导电层70。在第一导电层70上形成第一绝缘层11和第三导电图案300。形成穿透第一绝缘层11并且将第一导电层70和第三导电图案300电连接的第一接触塞160。可以通过将第三导电层图案化来形成第三导电图案300。脱模层30、铝层40、阻挡层50、第一导电层70、第一绝缘层11和第三导电图案300在图9A中示出为形成在载体层20的一个表面上，但是实施例不限于此。在其他实施例中，可以在相对的表面上形成脱模层30、铝层40、阻挡层50、第一导电层70、第一绝缘层11和第三导电图案300，从而在两个表面上形成脱模层30、铝层40、阻挡层50、第一导电层70、第一绝缘层11和第三导电图案300。
参照图9B，根据实施例，形成第二绝缘层12以覆盖第三导电图案300。第一绝缘层11和第二绝缘层12包括相同的材料。在上面参照图1描述了用于形成第二绝缘层12的材料。在第二绝缘层12的下部上形成第二导电层90。第一导电层70、第二导电层90和第三导电图案300包括相同的材料。例如，第一导电层70、第二导电层90和第三导电图案300可以包括铜。然而，第一导电层70、第二导电层90和第三导电图案300的实施例不限于此，在其他实施例中可以包括不同的材料。
根据实施例，形成穿透第二绝缘层12的第二接触塞260并且将第二接触塞260连接到第二导电层90。可以通过使用湿法蚀刻或干法蚀刻或者通过机械钻孔或激光钻孔形成接触孔260a并随后通过镀覆工艺使用导电材料填充接触孔260a来形成第二接触塞260。
参照图9C，根据实施例，通过将脱模层30分离为两个子层来将载体层20和铝层40彼此分离。可以通过使用物理方法、化学方法等执行分离工艺。脱模层30的子层30a保留在载体层20上。脱模层30的子层30b保留在铝层40上。去除分离的载体层20和脱模层30的子层30a。通过分别将铝层40、阻挡层50、第一导电层70和第二导电层90图案化来形成铝图案110、阻挡图案140、第一导电图案100和第二导电图案200。在这方面，从铝层40去除脱模层30的子层30b。
参照图9D，根据实施例，分别在绝缘层10a的上表面和绝缘层10a的与绝缘层10a的上表面相对的下表面上形成第一阻焊层130和第二阻焊层230。第一阻焊层130覆盖铝图案110的上表面和侧面、阻挡图案140的侧面和第一导电图案100的侧面的至少一部分。第二阻焊层230覆盖第二导电图案200的侧面。
根据实施例，第一阻焊层130包括使第一导电图案100的一部分、阻挡图案140的一部分和铝图案110的一部分暴露的至少一个开口130a。第一导电图案100、阻挡图案140和铝图案110的暴露的部分可以用作接触键合引线的焊盘，所述键合引线将PCB和安装在PCB上的半导体芯片或半导体封装件电连接。
根据实施例，分别在第一导电图案100和第二导电图案200的暴露的表面上形成第一钝化层120和第二钝化层220。因此，在第一导电图案100的一部分的侧面上形成第一钝化层120，在第二导电图案200的至少一部分的下表面上形成第二钝化层220。可以通过OSP表面处理形成第一钝化层120和第二钝化层220。可以同时形成第一钝化层120和第二钝化层220，但实施例不限于此。在铝图案110的通过开口130a暴露的表面上形成氧化物层115。氧化物层115为氧化铝。氧化物层115可以保护铝图案110。
图10是根据实施例的使用PCB 1的半导体封装件1000的剖视图。
参照图10，根据实施例，半导体封装件1000包括PCB 1、半导体芯片500和模层700。粘合层550形成在PCB 1上。半导体芯片500可以附着到粘合层550。PCB 1可以为图1和图2的PCB 1a、图4的PCB 1b、图5的PCB 1c或者图7和图8的PCB 1d。
在一些实施例中，半导体芯片500可以为控制器芯片、非易失性存储器芯片、易失性存储器芯片和/或虚设芯片或者这些芯片的组合。
非易失性存储器芯片可以为例如NAND闪速存储器、电阻式随机存取存储器(RRAM)、磁阻式RAM(MRAM)、相变式RAM(PRAM)或者铁电式RAM(FRAM)。非易失性存储器芯片可以为包括一个非易失性存储器芯片或者多个堆叠的非易失性存储器芯片的半导体封装件。
在一些实施例中，多个半导体芯片500可以在PCB 1中堆叠。在一些实施例中，多个堆叠的半导体芯片500可以经由贯穿电极彼此电连接。
根据实施例，键合引线600将PCB 1和半导体芯片500电连接。键合引线600可以包括例如铜或金。键合引线600穿透形成在铝图案110的表面上的氧化物层115，以将半导体芯片500的焊盘520和PCB 1的第一导电图案100电连接。
根据实施例，模层700形成在PCB 1的上表面上，以覆盖PCB 1的上表面的至少一部分和半导体芯片500。模层700可以包括例如硅材料、热固性材料、热塑性材料、UV可固化材料等。当模层700包括热固性材料时，模层700可以包括酚类试剂、酸酐类试剂、胺类可固化试剂或丙烯酸类聚合物添加剂。
在一些实施例中，模层700在包括相对小量的填充剂的同时包括树脂。在这方面，填充剂可以为二氧化硅填充剂。
尽管在图10中安装了半导体芯片500，但是另一半导体封装件可以安装在PCB 1上以形成层叠封装件(POP)结构。
虽然已经参照本发明构思的示例性实施例具体地示出并描述了本发明构思的实施例，但是将理解的是，在不脱离权利要求的精神和范围的情况下，在这里可以作出形式和细节上的各种改变。

Claims (19)

1.一种印刷电路板，所述印刷电路板包括：
绝缘层，包括上表面和与上表面相对的下表面；
第一导电图案，在绝缘层的上表面上；
第二导电图案，在绝缘层的下表面上；
铝图案，覆盖第一导电图案的上表面的至少一部分；
第一钝化层，覆盖第一导电图案的侧面的至少一部分，并且防止进入第一导电图案中的扩散；以及
第二钝化层，直接设置在第二导电图案的下表面的至少一部分上。
2.根据权利要求1所述的印刷电路板，其中，第一导电图案的上表面高于绝缘层的上表面。
3.根据权利要求1所述的印刷电路板，其中，第一钝化层包括通过有机可焊性防腐剂表面处理形成的材料。
4.根据权利要求1所述的印刷电路板，所述印刷电路板还包括在绝缘层上具有开口的第一阻焊层，
其中，铝图案的一部分的上表面通过第一阻焊层的开口暴露。
5.根据权利要求4所述的印刷电路板，所述印刷电路板还包括在绝缘层的下表面上的第二阻焊层，
其中，第二阻焊层覆盖第二导电图案的侧面。
6.根据权利要求1所述的印刷电路板，其中，绝缘层包括第一绝缘层和在第一绝缘层的下部上的第二绝缘层，
所述印刷电路板还包括在第二绝缘层中的第三导电图案。
7.根据权利要求6所述的印刷电路板，所述印刷电路板还包括：
接触塞，穿透第一绝缘层或第二绝缘层，并且电连接第一导电图案、第二导电图案和第三导电图案的至少一部分。
8.根据权利要求1所述的印刷电路板，所述印刷电路板还包括在第一导电图案与铝图案之间的阻挡图案。
9.一种半导体封装件，所述半导体封装件包括；
封装基底；
半导体芯片，在封装基底上；以及
键合引线，连接封装基底和半导体芯片，
其中，封装基底包括绝缘层、在绝缘层的上表面上并且包括铜的第一布线图案、在第一布线图案上并且包括与第一布线图案的材料不同的材料的第二布线图案以及在第一布线图案的侧面上并且防止进入第一布线图案中的扩散的有机钝化层。
10.根据权利要求9所述的半导体封装件，其中，封装基底还包括在绝缘层上具有开口的阻焊层，
其中，第一布线图案包括多个布线图案，第二布线图案包括多个布线图案，
其中，阻焊层的开口使第一布线图案的一部分和第二布线图案的一部分暴露。
11.根据权利要求9所述的半导体封装件，其中，第二布线图案包括铝。
12.根据权利要求11所述的半导体封装件，所述半导体封装件还包括在第二布线图案的表面上的氧化物。
13.根据权利要求12所述的半导体封装件，其中，第二布线图案在与绝缘层的上表面垂直的方向上的厚度小于第一布线图案在与绝缘层的上表面垂直的方向上的厚度，并且键合引线穿透氧化物以连接第一布线图案和半导体芯片。
14.根据权利要求9所述的半导体封装件，所述半导体封装件还包括：
第三布线图案，在绝缘层的下表面上；以及
接触塞，电连接第三布线图案和第一布线图案，
其中，第一布线图案和第三布线图案包括相同的材料。
15.一种用于制造印刷电路板的方法，所述方法包括以下步骤：
提供包括载体层、脱模层和铝层的载体基底；
在载体基底上形成第一导电层；
在第一导电层上形成绝缘层和第二导电层；
形成穿透绝缘层并且将第一导电层和第二导电层电连接的接触塞；
通过将脱模层分离为两个子层来将载体层和铝层彼此分离，其中，第一子层与载体层保留在一起，第二子层与铝层保留在一起；
去除分离的载体层和脱模层的第一子层；
通过分别将铝层、第一导电层和第二导电层图案化并且将脱模层的第二子层从铝层去除来形成铝图案、第一导电图案和第二导电图案；
在绝缘层的上表面上形成第一阻焊层并且在绝缘层的与上表面相对的下表面上形成第二阻焊层，其中，第一阻焊层包括暴露第一导电图案的一部分和铝图案的一部分的至少一个开口；以及
通过有机可焊性防腐剂表面处理在第一导电图案的暴露的表面上形成第一钝化层并且在第二导电图案的暴露的表面上形成第二钝化层。
16.根据权利要求15所述的方法，其中：
载体基底还包括阻挡层和种子层，
利用种子层作为种子通过镀覆来形成第一导电层，
通过将阻挡层图案化形成阻挡图案，并且所述至少一个开口使阻挡图案的一部分暴露。
17.根据权利要求15所述的方法，其中，通过如下步骤形成第一阻焊层：在绝缘层的上表面上形成覆盖铝图案的上表面和侧表面两者以及第一导电图案的侧面的预备的第一阻焊层并且去除预备的第一阻焊层的一部分以形成所述至少一个开口。
18.根据权利要求15所述的方法，所述方法还包括在铝图案的暴露的表面上形成氧化物层，其中，氧化物层因铝图案接触空气而形成。
19.根据权利要求15所述的方法，其中，形成绝缘层和形成接触塞的步骤还包括：
在第一导电层上形成第一绝缘层和第三导电图案；
形成穿透第一绝缘层并且将第一导电层和第三导电图案电连接的第一接触塞；
形成覆盖第三导电图案的第二绝缘层，其中，第二导电层形成在第二绝缘层上；以及
形成穿透第二绝缘层并且将第三导电图案和第二导电层电连接的第二接触塞。
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