CN107305879A - 半导体器件及相应的方法 - Google Patents

半导体器件及相应的方法 Download PDF

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Publication number
CN107305879A
CN107305879A CN201611148493.9A CN201611148493A CN107305879A CN 107305879 A CN107305879 A CN 107305879A CN 201611148493 A CN201611148493 A CN 201611148493A CN 107305879 A CN107305879 A CN 107305879A
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CN
China
Prior art keywords
flexible support
semiconductor die
support member
lead frame
conductor wire
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CN201611148493.9A
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CN107305879B (zh
Inventor
A·阿里戈尼
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STMicroelectronics SRL
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STMicroelectronics SRL
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Abstract

各个实施例涉及半导体器件及相应的方法。一种半导体器件，包括引线框架，该引线框架包括接触管脚和具有突出的连接形成物的半导体裸片。柔性支撑构件被设置在引线框架和半导体裸片之间并支撑半导体裸片。柔性支撑构件具有在引线框架和半导体裸片之间延伸的导电线。柔性支撑构件的导电线与引线框架的接触管脚以及半导体裸片的连接形成物电耦合。

Description

半导体器件及相应的方法
相关申请的交叉引用
本申请要求于2016年4月20日提交的意大利专利申请No.102016000040587的优先权，其公开内容通过引用并入本文。
技术领域
本说明书涉及半导体器件。一个或多个实施例可以应用于具有暴露焊盘的基于金属引线框架的封装。
背景技术
当前的基于引线框架的塑料封装可以包括将器件耦合到金属引线框架并且允许热功率和电功率耗散的裸片附接材料。
由于封装经受可靠性应力测试，比如热循环测试(“TCT”)，可能危及裸片附接完整性。
脱层可能由于与涉及的材料，包括硅、裸片附接材料(“DAM”)、铜合金等中的不同的热膨胀系数(“CTE”)值相关的热机械应力而发生。
脱层可导致在接触的两种不同材料之间的界面处，比如在硅/DAM和/或DAM/引线框架界面处，形成间隙。此外，比如在高温存储(“HTS”)测试之后，在DAM的主体内可能形成不连续。
这些事件可能对封装可靠性有害。对于包括暴露焊盘的封装而言，尤其是这样，因为热/电路径的完整性受到不利影响。
封装的质量和可靠性要求变得越来越苛刻，特别是在诸如汽车市场之类的领域中，其中提供无脱层封装的能力可能代表重要因素。
已经开发了各种方法以抵抗裸片附接脱层，主要集中在材料的改进和/或新材料的开发。
例如，可以以各种方式关注引线框架的精加工，包括但不限于：(1)通过提供引线框架表面的“粗糙化”处理，可以增强对裸片附接材料的机械粘附，或者(2)经由在引线框架表面上沉积有机覆层以增强对裸片附接材料的化学粘附。
也已经针对裸片附接材料提出了低应力材料的使用。
虽然某些解决方案已经刺激了一些商业利益，但是这些都不能被认为能够以令人满意的方式解决附接脱层的问题。
发明内容
一个或多个实施例提供了一种基于引线框架的塑料封装，其可能具有暴露的裸片的底表面，能够省去裸片附接材料-DAM和/或导线的使用。
在一个或多个实施例中，半导体器件(例如集成电路，比如IC器件或裸片)可以借助于铜柱或焊料凸块被耦合到柔性衬底(“柔性件”)并且被附接到平面金属引线框架的引脚，从而省去用于容纳裸片的常规裸片焊盘和/或分流条(tie bar)。
在一个或多个实施例中，柔性金属迹线可以被设计成在裸片和引线框架之间提供电连接。
在一个或多个实施例中，可以有效地抵抗裸片/DAM和/或DAM/裸片焊盘界面处的裸片附接脱层。
在一个或多个实施例中，这也可以应用于DAM降级，其中令人满意地降低了热/电耗散降级。
一个或多个实施例可以提供以下优点中的一个或多个：
(1)可以省去裸片附接材料或DAM，使得在裸片/DAM和/或DAM/裸片-焊盘界面处没有芯片附接脱层，也不会发生DAM降级；这可能导致热/电耗散退化被有效地抵消，
(2)可以经由暴露的裸片提高功率耗散，而不存在由DAM材料，裸片焊盘和相关界面提供的热阻；这可以使器件操作温度得到改善；和
(3)由于用柔性导电迹线替换常规导线的可能性，可以在裸片-引线框架布线连接中实现增加的柔性。与标准工艺流程相比，可以实现更简单的工艺流程，(a)由于可以省去裸片焊盘的存在，可以降低引线框架设计的复杂性和成本：这可以有助于通过封装体尺寸而具有单个引线框架并且实现内引线的形状标准化，或者(b)由于省去裸片焊盘和DAM的可能性，可以减小封装体的厚度。
附图说明
现在将参照附图仅通过示例的方式描述一个或多个实施例，其中：
图1至图4是一个或多个实施例中的步骤的示例；和
图5至图7是适于包括若干实施例的各种半导体器件封装的示例。
具体实施方式
应当理解，为了说明的清楚起见，各个附图可能没有以相同的比例绘制。
在随后的描述中，示出了一个或多个具体细节，旨在提供对实施例的示例的深入理解。实施例可以通过一个或多个具体细节或者利用其他方法、组件、材料等来获得。在其他情况下，未详细示出或描述已知的结构、材料或操作，使得实施例的某些方面不会变模糊。
在本说明书的框架中对“实施例”或“一个实施例”的引用旨在指出关于该实施例描述的特殊配置、结构、特性至少符合一个实施例。因此，可能存在于本说明书中的一个或多个点中的诸如“在实施例中”或“在一个(或多个)实施例中”的短语不一定指同一个实施例。此外，如结合任一附图所例示的特定构造、结构或特性可以以可能在其他附图中示例的一个或多个实施例中以任何其他相当的方式组合。
在附图中，半导体裸片(或者半导体器件本身)被指定为10。器件10可以是适于被封装在基于引线框架的封装(比如基于引线框架的塑料封装)中的任何已知类型(例如集成电路)。
图1例示了在这种半导体裸片10上提供焊料凸块12a或金属(例如，铜)柱12b形式的连接形成物(电气-机械)的可能性。
附图例示了提供两种类型的这种连接形成物的可能性。然而，一个或多个实施例可以仅采用一种类型的这种连接形成物，即(仅)焊料凸块12a或(仅)金属柱12b。此外，一个或多个实施例可以包括本领域中已知的其他类型的连接形成物。
如本文所例示的，连接形成物12a和/或12b可以在裸片10面向上的表面处被提供在裸片12的接触焊盘上。在这样的实施例中，然后可以将裸片10上下颠倒(即“翻转”180°)，使得连接形成物12a、12b如图2所示面向下。
图3例示了在一个或多个实施例中柔性衬底构件(“柔性件”)14的可能设置。
在一个或多个实施例中，这种柔性衬底可以以本身已知的方式包括柔性支撑层140，柔性支撑层140可以是聚合物材料，在其上设置有定义到连接形成物12a、12b的电连接布局(比如，在其下侧，参考图3的视角)的导电线或“迹线”(例如，诸如铜或铜合金的金属)142。
图3例示了裸片10的连接形成物12a、12b与柔性支撑件14的线或迹线142的机械和电耦合，其中裸片10的突出连接形成物12a、12b面向柔性支撑构件14。
例如，这可以通过热声或热压处理或适于产生在半导体裸片10的连接形成物12a、12b与柔性支撑构件或柔性件14的导电线142之间建立的金属接合连接的其他工艺(示意性地表示为T1)发生。
在附图的示例性实施例中，导电线142被示出提供在柔性支撑层140与裸片10相对的表面处，连接形成物12a、12b延伸穿过提供在柔性支撑层140中的开口(窗口)以与柔性支撑构件14的导电线142耦合：这种表示仅仅是可能的实施方式的示例，并且不应被解释为实施方式的范围的限制意义。
在如图4中例示的一个或多个实施例中，柔性支撑构件或柔性件14可以被耦合到金属引线框架16。
在一个或多个实施例中，引线框架16可以包括接触管脚(引线指脚或引线尖端)并且通常是环形的，因此具有用于安装半导体裸片10的中心区域。
在一个或多个实施例中，柔性支撑构件14，比如导电线142，与金属引线框架16的接触管脚的金属化(指示为162)的耦合可以在导电线142的金属化部分(指示为1420)处。
在一个或多个实施例中，将柔性支撑构件14(导电线142)与金属引线框架16的引线尖端耦合可以借助于针对该目的已知的另一工艺(图4中的T2)，比如在被镀制到柔性支撑层140上的导电线142的金属化部分(标示为1420)与引线框架的引线尖端(指示为162)的精加工之间提供金属接合连接。
示意性地表示为T2的工艺可以包括热声或扩散焊接工艺。
在一个或多个实施例中，图4中的工艺T2可以与图3中例示的工艺T1相同。
在一个或多个实施例中，工艺可以不同于图3中例示的工艺T1。
应当理解，图1至图4中所示的各个部件/元件的方向仅仅是示例性的。
仅仅作为示例，连接形成物12a、12b可以被提供成：(1)如此处所示，使裸片10的接触焊盘面向上，其中裸片10随后被翻过来(翻转180°)，或者替换地，(2)裸片10已经定向为其接触焊盘朝下，如图2所例示。
类似地，裸片10与柔性支撑件14和引线框架16的耦合可以发生在裸片10位于柔性构件14和引线框架16上方的情况下，或者替代地，发生在裸片10被布置在柔性构件14和/或引线框架16下方的情况下。
因此，图1至图4中所示的各个部件/元件的方向仅仅是示例性的，而不是对实施例的范围的限制。
前述内容也适用于图5至图7。
这些图表示将图4所示的零件/元件的部件与封装18耦合的各种方式。
在一个或多个实施例中，封装18可以包括所谓的“塑料”封装，包括模制到图4的零件/元件的部件上的任何已知类型的封装模制化合物(PMC)。
一个或多个实施例可以采用标准的传递模制工艺，使得裸片10在封装18的外表面处不暴露出来。
图5例示了采用膜辅助模制工艺以便暴露裸片10的硅(背面)表面的一个或多个实施例。
图6例示了在暴露裸片“向上”配置的情况下的标准的切断和切单步骤，其中裸片10在封装18的顶表面处暴露出来，以便允许将热沉(图中不可见)与可能“向下”弯曲的引线框架16的管脚(在16a处示出)耦合。这可以促进与提供在底层安装板(比如印刷电路板或PCB-图中未示出)上的导电线的电耦合。
图7例示了在暴露裸片“向下”配置的情况下的标准的切断和切单步骤，即，在封装18的底表面处(可能在180°的“翻转”之后，即图4中例示的翻转部件)暴露的裸片10与可能再次向下“弯曲”的引线框架16的引脚(在16a处示出)耦合，以便促进可能具有背面金属化“BSM”的电连接(比如经由焊接连接到PCB导电迹线)，以允许将裸片表面焊接到PCB上。
因此，一个或多个实施例可以促进解决裸片附接脱层问题，比如通过省去裸片附接材料。
在那个方面，一个或多个实施例可以因此提供一种半导体器件，包括：(1)包括接触管脚并且具有中心区域的引线框架(例如16)，(2)被布置在引线框架的所述中心区域的半导体裸片(例如10)，该半导体裸片具有突出的连接形成物(例如12a，12b)，以及(3)在所述中心区域处设置在引线框架和半导体裸片之间的柔性支撑构件(例如14)，所述柔性支撑构件具有在引线框架和半导体裸片之间延伸的导电线(例如142)
其中，柔性支撑构件的所述导电线与引线框架的接触管脚和半导体裸片的连接形成物电耦合。
在一个或多个实施例中，半导体裸片的连接形成物可以包括焊料凸块和/或金属柱，金属柱可选地为铜柱。
一个或多个实施例可以包括金属接合连接，其在(1)柔性支撑构件的导电线与引线框架的接触管脚之间，和/或(2)柔性支撑构件的导电线与半导体裸片的连接形成物之间。
在一个或多个实施例中，柔性支撑构件可以包括具有在其上延伸的所述导电线的柔性支撑层(在140处示出)。
在一个或多个实施例中，半导体裸片的连接形成物可以延伸穿过柔性支撑构件的所述柔性支撑层。
一个或多个实施例可以包括封装(在18处示出)，其模制到所述引线框架、所述半导体裸片以及在其之间设置的所述柔性支撑构件上。
在一个或多个实施例中，半导体裸片可以在所述封装的表面处暴露出来。
一个或多个实施例可以提供一种制造半导体器件的方法，包括：(1)提供包括接触管脚并且具有中心区域的引线框架，(2)在引线框架的所述中心区域处布置半导体裸片，所述半导体裸片具有突出连接形成物，以及(3)在所述中心区域处在所述引线框架和所述半导体裸片之间设置柔性支撑构件，所述柔性支撑构件具有在所述引线框架和所述半导体裸片之间延伸的导电线，并且将柔性支撑构件的导电线与引线框架的接触管脚以及半导体裸片的连接形成物电耦合。
一个或多个实施例可以包括：(1)经由热声耦合或热压耦合之一，将柔性支撑构件的导电线与半导体裸片的连接形成物耦合，和/或(2)通过热声耦合和扩散焊接之一，将柔性支撑构件的导电线与引线框架的接触管脚耦合。
在不脱离保护范围的情况下，只要不偏离基本原理，细节和实施例可以相对于仅通过示例公开的内容发生变化，甚至显著地发生变化。

Claims (23)

1.一种半导体器件，包括：
引线框架，所述引线框架包括接触管脚并且具有中心区域；
位于所述中心区域处的半导体裸片，所述半导体裸片具有突出的连接形成物；
柔性支撑构件，所述柔性支撑构件被设置在所述引线框架和所述半导体裸片之间并支撑所述半导体裸片，所述柔性支撑构件具有在所述引线框架和所述半导体裸片之间延伸的导电线；以及
其中所述柔性支撑构件的所述导电线与所述引线框架的所述接触管脚以及与所述半导体裸片的所述连接形成物电耦合。
2.根据权利要求1所述的半导体器件，其中所述半导体裸片的连接形成物包括焊料凸块。
3.根据权利要求1所述的半导体器件，其中所述半导体裸片的连接形成物包括金属柱。
4.根据权利要求1所述的半导体器件，其中所述半导体裸片的连接形成物包括铜柱。
5.根据权利要求1所述的半导体器件，还包括在所述柔性支撑构件的所述导电线和所述引线框架的所述接触管脚之间的金属接合连接。
6.根据权利要求1所述的半导体器件，还包括在所述柔性支撑构件的所述导电线和所述半导体裸片的所述连接形成物之间的金属接合连接。
7.根据权利要求1所述的半导体器件，还包括在所述柔性支撑构件的所述导电线和所述引线框架的所述接触管脚之间以及在所述柔性支撑构件的所述导电线和所述半导体裸片的所述连接形成物之间的金属接合连接。
8.根据权利要求1所述的半导体器件，其中所述柔性支撑构件包括柔性支撑层，所述柔性支撑层具有在其上延伸的所述导电线。
9.根据权利要求8所述的半导体器件，其中所述半导体裸片的连接形成物延伸穿过所述柔性支撑构件的所述柔性支撑层。
10.根据权利要求8所述的半导体器件，还包括模制到所述引线框架、所述半导体裸片和所述柔性支撑构件上的封装。
11.根据权利要求10所述的半导体器件，其中所述半导体裸片在所述封装的表面处暴露出来。
12.根据权利要求1所述的半导体器件，其中，所述柔性支撑构件包括由聚合物材料制成的柔性支撑层，并且其中，所述引线框架由金属材料制成。
13.一种半导体器件，包括：
柔性聚合物支撑构件，所述柔性聚合物支撑构件支撑具有连接形成物的半导体裸片；
导电线，所述导电线被设置在所述柔性聚合物支撑构件上并且被电连接到所述连接形成物；
金属引线框架，所述金属引线框架具有环形形状并且定义接触管脚；以及
其中所述柔性支撑构件上的所述导电线与所述引线框架的所述接触管脚电耦合。
14.根据权利要求13所述的半导体器件，其中所述金属引线框架定义围绕中心区域的内周界部分，所述导电线被附接到所述引线框架的内周界部分。
15.根据权利要求13所述的半导体器件，还包括模制到所述引线框架、所述半导体裸片和所述柔性支撑构件上的封装，所述半导体裸片的表面从所述封装暴露出来。
16.根据权利要求15所述的半导体器件，其中所述半导体裸片的暴露表面与所述封装的上表面共面。
17.根据权利要求13所述的半导体器件，其中所述柔性支撑构件包括柔性支撑层，所述半导体裸片的连接形成物延伸穿过所述柔性支撑层以接触所述导电线。
18.根据权利要求13所述的半导体器件，包括模制到所述引线框架、所述半导体裸片和所述柔性支撑构件上的封装，所述半导体裸片的表面从所述封装暴露出来，所述引线框架的所述接触管脚向下成角度，以延伸远离所述半导体裸片的所述暴露表面。
19.根据权利要求13所述的半导体器件，包括模制到所述引线框架、所述半导体裸片和所述柔性支撑构件上的封装，所述半导体裸片的表面从所述封装暴露出来，所述引线框架的所述接触管脚向下成角度，以延伸朝向所述半导体裸片的所述暴露表面。
20.一种制造半导体器件的方法，包括：
提供包括接触管脚并且围绕中心区域的引线框架；
将半导体裸片布置成与所述中心区域对准，所述半导体裸片具有突出的连接形成物；
在所述引线框架和所述半导体裸片之间提供柔性支撑构件，所述柔性支撑构件具有在所述引线框架和所述半导体裸片之间延伸的导电线；以及
将所述柔性支撑构件的导电线与所述引线框架的接触管脚和所述半导体裸片的连接形成物电耦合。
21.根据权利要求20所述的方法，其中将所述柔性支撑构件的导电线与所述半导体裸片的连接形成物电耦合包括热声耦合和热压耦合中的一种。
22.根据权利要求20所述的方法，其中将所述柔性支撑构件的所述导电线与所述引线框架的所述接触管脚电耦合包括热声耦合和扩散焊接中的一种。
23.根据权利要求20所述的方法，其中：
将所述柔性支撑构件的所述导电线与所述半导体裸片的所述连接形成物电耦合包括热声耦合和热压耦合中的一种；以及
将所述柔性支撑构件的所述导电线与所述引线框架的所述接触管脚电耦合包括热声耦合和扩散焊接中的一种。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110620045A (zh) * 2018-06-20 2019-12-27 安世有限公司 用于半导体器件的引线框架组件

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITUA20162740A1 (it) * 2016-04-20 2017-10-20 St Microelectronics Srl Dispositivo a semiconduttore e procedimento corrispondente
DE102020122662A1 (de) * 2020-08-31 2022-03-03 Infineon Technologies Ag Biegehalbleiterchip für eine Verbindung bei verschiedenen vertikalen Ebenen

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5328079A (en) * 1993-03-19 1994-07-12 National Semiconductor Corporation Method of and arrangement for bond wire connecting together certain integrated circuit components
US20020070449A1 (en) * 2000-12-12 2002-06-13 Lumileds Lighting, U.S., Lls Light-emitting device and production thereof
US6498389B1 (en) * 2001-07-16 2002-12-24 Samsung Electronics Co., Ltd. Ultra-thin semiconductor package device using a support tape
CN103515249A (zh) * 2013-08-06 2014-01-15 江苏长电科技股份有限公司 先封后蚀三维系统级芯片正装凸点封装结构及工艺方法
US20160043020A1 (en) * 2014-02-24 2016-02-11 Nantong Fujitsu Microelectronics Co., Ltd. Semiconductor Packaging Structure And Forming Method Therefor
CN206505916U (zh) * 2016-04-20 2017-09-19 意法半导体股份有限公司 半导体器件

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04243143A (ja) * 1991-01-17 1992-08-31 Fujitsu Ltd 半導体装置の製造方法
JPH07130918A (ja) * 1993-09-10 1995-05-19 Fujitsu Ltd 半導体装置及びその製造方法
JPH0831879A (ja) * 1994-07-18 1996-02-02 Fujitsu Ltd 半導体装置とｔａｂテープ及びそれぞれの製造方法
KR100575590B1 (ko) * 2003-12-17 2006-05-03 삼성전자주식회사 열방출형 적층 패키지 및 그들이 실장된 모듈
US8148822B2 (en) * 2005-07-29 2012-04-03 Megica Corporation Bonding pad on IC substrate and method for making the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5328079A (en) * 1993-03-19 1994-07-12 National Semiconductor Corporation Method of and arrangement for bond wire connecting together certain integrated circuit components
US20020070449A1 (en) * 2000-12-12 2002-06-13 Lumileds Lighting, U.S., Lls Light-emitting device and production thereof
US6498389B1 (en) * 2001-07-16 2002-12-24 Samsung Electronics Co., Ltd. Ultra-thin semiconductor package device using a support tape
CN103515249A (zh) * 2013-08-06 2014-01-15 江苏长电科技股份有限公司 先封后蚀三维系统级芯片正装凸点封装结构及工艺方法
US20160043020A1 (en) * 2014-02-24 2016-02-11 Nantong Fujitsu Microelectronics Co., Ltd. Semiconductor Packaging Structure And Forming Method Therefor
CN206505916U (zh) * 2016-04-20 2017-09-19 意法半导体股份有限公司 半导体器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110620045A (zh) * 2018-06-20 2019-12-27 安世有限公司 用于半导体器件的引线框架组件
CN110620045B (zh) * 2018-06-20 2022-08-02 安世有限公司 用于半导体器件的引线框架组件

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