CN110620045B - 用于半导体器件的引线框架组件 - Google Patents
用于半导体器件的引线框架组件 Download PDFInfo
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- CN110620045B CN110620045B CN201910539172.9A CN201910539172A CN110620045B CN 110620045 B CN110620045 B CN 110620045B CN 201910539172 A CN201910539172 A CN 201910539172A CN 110620045 B CN110620045 B CN 110620045B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 141
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 238000010276 construction Methods 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 34
- 238000000465 moulding Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 24
- 239000012778 molding material Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 3
- 230000001419 dependent effect Effects 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 description 23
- 229910000679 solder Inorganic materials 0.000 description 19
- 239000000853 adhesive Substances 0.000 description 17
- 230000001070 adhesive effect Effects 0.000 description 17
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000003292 glue Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 238000013022 venting Methods 0.000 description 1
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Abstract
本公开涉及用于半导体器件的引线框架组件,引线框架组件包括:裸片附接结构和线夹框架结构;线夹框架结构包括:裸片连接部分,裸片连接部分被配置和布置用于接触在半导体裸片的顶侧上的一个或多个接触端子;一个或多个电引线和引线支撑构件,一个或多个电引线在第一端处从裸片连接部分延伸,并且引线支撑构件从一个或多个引线的第二端延伸;以及与一个或多个电引线正交布置的多个线夹支撑构件,其中多个支撑构件和引线支撑构件被配置和布置成接触裸片附接结构。本发明还涉及用于半导体器件的裸片附接结构和线夹框架结构、包括该裸片附接结构和线夹框架结构的半导体器件以及制造该半导体器件的相关方法。
Description
技术领域
本公开涉及用于半导体器件的引线框架组件。具体地,本公开涉及用于半导体器件的裸片附接结构和线夹(clip)框架结构、包括该裸片附接结构和线夹框架结构的半导体器件以及制造该半导体器件的相关方法。
背景技术
在半导体器件中,通常使用线夹接合的封装来制造从半导体裸片到器件的外部触点的连接。与传统的引线接合封装相比,线夹接合封装具有许多优点。例如,线夹接合封装通常用于在汽车应用中与半导体裸片机械稳固且可靠的电连接。此外,与引线接合材料相比,导电线夹材料可具有增加的热质量,并且因此可用作用于半导体裸片的散热片(heatsink)。
然而,当在半导体裸片上安装和附接线夹时,可能发生线夹相对于半导体裸片的旋转或倾斜错位。这种错位可能导致半导体器件的功能性降低或失效。由于线夹与半导体裸片的连接的性质,可能发生错位或倾斜。通常,通过以下方式实现线夹与半导体裸片的连接:将接合材料(诸如,焊料或导电粘合剂)分配在半导体裸片上,随后将线夹放置在焊料或导电粘合剂上,形成所谓的接合线。由于线夹的重量在焊料或导电粘合剂上施加向下的压力,接合线厚度在其区域上可能不均匀,并且可能导致线夹相对于半导体裸片倾斜。换句话说,线夹的底表面(即面向半导体裸片的表面)不与半导体裸片的顶表面平行。
在某些应用中,可能期望的是,增加线夹材料的厚度以增加半导体裸片的热质量,并且因此提供用于半导体裸片的较大散热片。增加的厚度还可允许线夹的顶表面通过半导体器件封装材料的顶表面暴露。然而,与线夹的增加的厚度相关联的增加的重量可导致焊料或导电粘合剂上的向下压力增加,这可导致接合线厚度在整个接合线的区域上的增加的不均匀性。此不均匀性可导致线夹的如上文所论述的不期望的倾斜或旋转。此外,如上所述的与线夹的倾斜结合的散热片的暴露可导致在封装之后在散热片上不需要的模具飞边(mould flashing)。
通常,在模制后,使用诸如研磨或抛光的机械磨削力移除任何不期望的模具飞边。然而,使用机械力来移除过多的模具飞边可潜在地导致包封半导体裸片和引线框的模制材料与半导体裸片和/或裸片附接结构的损坏性分离,并且此分离可最终导致半导体器件的故障。
此外,线夹相对于半导体裸片的倾斜可导致线夹的一端高于另一端,并且可导致模制化合物在模制处理期间进入模腔的顶部与线夹之间的任何间隙。
发明内容
根据第一方面,提供了一种用于半导体器件的引线框架组件,所述引线框架组件包括:裸片附接结构和线夹框架结构;所述线夹框架结构包括:裸片连接部分,所述裸片连接部分被配置和布置用于接触在所述半导体裸片的顶侧上的一个或多个接触端子;一个或多个电引线和引线支撑构件,所述一个或多个电引线在第一端处从所述裸片连接部分延伸,并且引线支撑构件从所述一个或多个引线的第二端延伸;以及与所述一个或多个电引线正交布置的多个线夹支撑构件,其中所述多个支撑构件和所述引线支撑构件被配置和布置成接触所述裸片附接结构。
可选地,多个线夹支撑构件可以布置在裸片连接部分上。
可选地,多个线夹支撑构件布置在裸片连接部分和引线支撑构件之间的一个或多个电引线上。
根据实施例,引线框架组件可以可选地还包括横跨一个或多个电引线正交地延伸的坝条(dam bar),其中,线夹支撑构件中的每一个整体地形成在坝条的相应端部处。
可选地,线夹框架结构由单个整片的导电材料形成。
根据实施例,引线框架组件可以可选地还包括布置在裸片连接部分上的散热片构件。
根据第二方面,提供了一种半导体器件,包括根据第一方面的引线框架组件,并且还包括布置在裸片附接结构上的半导体裸片和封装半导体裸片的模制材料。
可选地,使用接合材料将裸片连接部分连接到半导体裸片的顶侧接触部分。
可选地,接合材料的厚度在接合区域上实质上相等,和/或其中裸片连接部分实质上平行于半导体裸片的顶侧。
根据实施例,散热片构件的顶表面与模制材料的顶表面实质上共面。
可选地,使用接合材料将散热片构件附接至裸片连接部分,和/或使用接合材料将裸片附接结构附接至半导体裸片的背侧接触部分。
根据第三方面,提供了一种制造半导体器件的方法,所述方法包括:提供裸片附接结构;将半导体裸片固定到裸片附接结构;将线夹框架结构附接到所述裸片附接结构和所述半导体裸片;其中,所述线夹框架结构包括:裸片连接部分,所述裸片连接部分被配置和布置用于接触在所述半导体裸片的顶侧上的一个或多个接触端子;一个或多个电引线和引线支撑构件,所述一个或多个电引线在第一端处从所述裸片连接部分延伸,并且所述引线支撑构件从所述一个或多个引线的第二端延伸;以及与所述一个或多个电引线正交布置的多个线夹支撑构件,其中所述多个支撑构件和所述引线支撑构件被配置和布置成接触所述裸片附接结构。
可选地,线夹支撑构件固定地连接到裸片附接结构。
附图说明
在附图和以下描述中,相同的附图标记指代相同的特征。
以下仅通过示例的方式参考附图来进一步描述本发明,在附图中:
图1a示出了根据实施例的裸片附接结构和线夹框架结构的布置,其中单规格(gauge)的线夹框架结构被安装在裸片附接结构上;
图1b示出了根据图1a的裸片附接结构和线夹框架结构的布置的侧视图;
图1c示出了在模制之后的图1a的布置的进一步视图;
图2a是根据实施例的裸片附接结构和线夹框架结构的布置,其中双规格的线夹框架结构被安装在裸片附接结构上;
图2b示出了图2a的平面图的侧视图;
图2c示出了在模制之后的图2a的布置的进一步视图;
图3a示出了根据实施例的完成的半导体器件的平面图;
图3b示出了根据图3a的完成的半导体器件的等距视图;
图4a示出了根据实施例的完成的半导体器件的平面图;
图4b示出了根据图4a的完成的半导体器件的等距视图;
图5a示出了根据实施例的完成的半导体器件的侧视图;
图5b示出了根据实施例的完成的半导体器件的另一侧视图;
图6a示出了根据实施例的裸片附接结构和线夹框架结构的布置,其中双规格的线夹框架结构被安装在裸片附接结构上;
图6b示出了图6a的平面图的侧视图;
图6c示出了在模制之后的图6a的布置的进一步视图;
图7a至图7g示出了根据实施例的用于制造半导体器件的处理流程步骤;以及
图8a至图8d示出了根据实施例的用于制造半导体器件的处理流程步骤。
具体实施方式
总的来说,在图1a和图1b中示出在模制和分割之前并且包括根据实施例的引线框结构的半导体器件100。半导体器件100通常包括构成引线框架组件的裸片附接结构102和线夹框架结构104,以及附接到裸片附接结构102和线夹框架结构104的半导体裸片106。
裸片附接结构102通常被布置用于在其上安装半导体裸片106 并且为线夹框架结构104提供支撑。此外,取决于半导体裸片106的诸如源极、栅极或漏极的接触端子的布置,裸片附接结构102可以提供与半导体裸片106的背部或底部触点的接触。裸片附接结构102通常由诸如铜的金属导电材料形成,从而向半导体裸片106的背部或底部接触端子提供诸如漏极接触的底部外部引线103。如图1c中所示出,底部外部引线103可延伸到半导体器件100的模制材料外部,以形成到半导体裸片106的底部的散热片接头(tab)。线夹框架结构包括散热片部分107,其也用作到半导体裸片106的顶部触点的连接。
半导体裸片106被固定地布置在裸片附接结构102上,并且线夹框架结构104被固定地连接到半导体裸片106和裸片附接结构102。散热片部分107的形状一般可以是矩形的,并且可以将其尺寸设计成使得其实质上与其所附接的半导体裸片106的顶部接触端子110的尺寸相匹配。
如上文所述,半导体裸片106的底部或背部接触端子可固定地附接到裸片附接结构102的裸片附接部分108。半导体裸片106可固定地附接到裸片附接结构,且可使用任何合适的接合材料(例如焊料或导电粘合剂)经由底部接触端子(未图示)将其电连接到裸片附接结构。使用适当的接合材料(例如,焊料或导电粘合剂),将线夹框架结构104固定地附接到布置在半导体裸片106的顶侧上的接触端子110。在图5a和图5b中更清楚地示出了用于连接半导体裸片106的接合材料的布置。
线夹框架结构104还可以包括从其第一侧延伸的一个或多个引线112。在第一端处,一个或多个引线112、116可以与散热片部分107一体地形成。在远离第一端的第二端处,引线112彼此连接并且被布置成形成支撑构件114,其中引线支撑构件114被布置成接触裸片附接结构102并且由裸片附接结构102支撑。一个或多个可选引线116可以被布置成连接到支撑构件114,其中一个或多个可选引线可以连接到另一接触端子118,诸如半导体裸片106的栅极端子。坝条(dam-bar)可以与引线一体地形成并且可以正交地延伸穿过一个或多个引线112、116。引线支撑构件114可以通过适当的接合材料(例如,焊料或导电胶)附接至裸片附接结构102。
在如下文更详细地论述的半导体器件的分割之后,引线112、引线116将与引线支撑构件114分离以形成到半导体裸片106的外部电触点。一个或多个引线112、118可以适用于到诸如印刷电路板(未示出)的载体的连接。
第一线夹支撑构件122可以被布置为从散热片部分107的与引线112、116延伸的侧面相对的一侧延伸。第二线夹支撑构件124也可以从散热片部分107的与第一线夹支撑构件122相对的一侧延伸。第一线夹支撑构件122和第二线夹支撑构件124的功能是为裸片附接结构102上的线夹框架结构104提供支撑,从而防止线夹框架结构104在放置或附接到半导体裸片106期间倾斜。此外,第一线夹支撑构件122和第二线夹支撑构件124在线夹框架结构104上而不是在裸片附接结构102上的布置允许裸片附接结构保持实质上平坦。这允许裸片附接结构102的低成本制造。
第一线夹支撑构件122和第二线夹支撑构件124从散热片部分107延伸以接触裸片附接结构102。可以使用诸如焊料或导电粘合剂的任何合适的接合材料将第一线夹支撑构件122和第二线夹支撑构件124附接至裸片附接结构102。
通过在线夹框架结构104的第一侧处的第一线夹支撑构件122和第二线夹支撑构件124以及在线夹框架结构104的相对侧上的引线支撑构件114的组合,第一线夹支撑构件122和第二线夹支撑构件124和引线支撑构件114防止线夹框架结构104相对于半导体裸片106倾斜。因此,第一线夹支撑构件122和第二线夹支撑构件124和引线支撑构件114支撑线夹框架结构104的对焊料或导电粘合剂的向下作用的重量,并且,以这种方式,线夹框架结构104的散热片部分107被维持为实质上平行于半导体裸片106的顶表面。因此,将线夹框架结构连接到半导体裸片106的接触端子的接合材料的接合线厚度在接触端子的表面区域上实质上相等,如在图1b和下面的图5a和图5b中示出的。
如图1c所示,然后使用模制化合物126封装半导体裸片106和线夹框架结构104。半导体裸片106和线夹框架结构104被模制,使得第一线夹支撑构件122和第二线夹支撑构件124伸出穿过模制化合物126以接触裸片附接结构102。同样地,一个或多个引线112、116和引线支撑构件114也伸出穿过模制化合物126。
线夹框架结构104、散热片部分107、第一线夹支撑构件122和第二线夹支撑构件124、一个或多个引线112、116和引线支撑构件114通常地由单个金属片(诸如铜)形成,其被形成或冲压以产生期望的结构。以这种方式,线夹框架结构104、第一线夹支撑构件122和第二线夹支撑构件124、一个或多个引线112和引线支撑构件114中的每个的厚度将通常是相等的。金属的选择完全是技术人员的选择,并且可以取决于半导体器件100的所需电气特性来选择。
在图2a至图2c的布置中,半导体裸片106被固定地布置在裸片附接结构102上,并且线夹框架结构104被固定地连接到半导体裸片106和裸片附接结构102,如上文参考图1a至图1c所示。图2a至图2c的相同参考标号对应于图1a至图1c的相同特征。然而,在图2a至图2c的布置的情况下,散热片部分107比第一线夹支撑构件122和第二线夹支撑构件124、一个或多个引线112、116和引线支撑构件114更厚。虽然这些特征通常由单个金属片形成,但是散热片部分107形成为比第一线夹支撑构件122和第二线夹支撑构件124、一个或多个引线112、116以及引线支撑构件114更厚。这在图2b中的侧视图中示出,图2b示出了与其他特征相比散热片部分107的增加的厚度。散热片部分107的厚度增加可导致热质量增加并因此导致线夹框架结构的散热能力提高。
如本领域技术人员将认识到的,当与图1a至图1c的实施例相比时,图2a至图2c的散热片107的增加的厚度将导致对焊料或导电粘合剂上向下作用的重量增加。由于对焊料或导电粘合剂向下作用的线夹框架结构的重量增加,因此,第一线夹支撑构件122和第二线夹支撑构件124以及引线支撑构件114防止线夹框架相对于半导体裸片106的倾斜。如上文所论述,这样维持了线夹框架结构实质上平行于半导体裸片106的顶部。因此,将散热片部分107连接到半导体裸片106的接触端子的粘合剂材料的接合线厚度在半导体裸片106的顶部接触端子110的表面区域上是实质上恒定的。
如图2c所示,使用模制化合物126来封装半导体裸片106和线夹框架结构104。半导体裸片106和线夹框架结构104被模制,使得第一线夹支撑构件122和第二线夹支撑构件124伸出穿过模制化合物126。同样地,一个或多个引线112、116和引线支撑构件114也伸出穿过模制化合物126。此外,由于具有散热片部分107的线夹框架结构104的增加的厚度,散热片部分107的顶表面可以被布置成伸出穿过模制化合物126的顶表面并通过模制化合物126的顶表面被暴露。此外,由于散热片部分107实质上平行于半导体裸片106的顶部的上述布置,具有散热片部分107的线夹框架结构104的顶部将与模制化合物126的顶表面实质上等高并且平行。
如上所述,与包括散热片部分107的线夹框架结构104的增加的厚度以及散热片部分107的顶部伸出穿过模制化合物126的顶表面并通过模制化合物126的顶表面被暴露相结合,由于散热片部分107的整个顶表面被暴露并且没有被绝缘模制化合物126覆盖,所以线夹框架结构104引导热量离开有源半导体裸片106的能力增加。
由于线夹框架结构104和散热片部分107与模制化合物126的顶表面的平行和层次性质,线夹框架结构104的暴露的顶表面将没有过多的模具飞边,而对研磨或抛光的需要将被移除或减少。线夹框架结构104和散热片部分107的平行和层次性质通过由线夹框架结构104施加在半导体裸片106的顶侧上的焊料或导电粘合剂上的平衡的(甚至跨越线夹的整个表面)夹持压力来实现,从而实现散热片部分107的顶表面的完全暴露。此外,因为散热片部分107的顶表面实质上没有所谓的模具飞边,所以减少了对完成的半导体器件进行后处理(诸如研磨)以移除模具飞边的需要。
根据图1a至图1b和图2a至图2c的实施例的线夹框架结构可以还包括穿过其中的一个或多个狭缝或孔128,以允许在附接期间任何焊料气体的通风。通过允许气体穿过孔或狭缝128,这些所谓的出气孔防止由于在焊接处理期间产生的气体施加在线夹上的向上压力而导致的线夹倾斜和/或旋转。
在模制半导体器件100之后,通过从引线支撑构件114切断引线112、116并移除坝条128来分割器件。然后通过弯曲成它们的期望形状来形成引线112。第一线夹支撑构件122和第二线夹支撑构件124也被切断,使得它们不再与裸片附接结构102接触。此外,底部外部引线103也与裸片附接结构102分离。
现在参考图3a,示出了根据实施例的分割和完成的半导体器件100,其示出了引线112、118和底部外部引线103。此外,切断的第一线夹支撑构件122和第二线夹支撑构件124保持附接到线夹框架结构104。切断的第一线夹支撑构件122和第二线夹支撑构件124被示出为从半导体器件的模制化合物126突出,然而,取决于分割技术,它们可以与模制化合物126齐平或等高。具有散热片部分107的线夹框架结构104的顶表面伸出并在如上所述的模制化合物126的顶表面处暴露。
图4a和图4b的布置与图3a和图3b的布置相似,除了由于相对较薄的散热片部分107,线夹框架结构104的顶表面不伸出通过模制化合物126的顶表面并且不通过模制化合物126的顶表面被暴露。换句话说,线夹框架结构104和散热片被嵌入模制化合物126内。
根据实施例,第一引线112可以形成到半导体裸片106的顶侧上的源极端子110的源极连接。第二引线116可以形成到也形成在半导体裸片106的顶侧上的栅极端子118的栅极连接。底部外部引线103可形成到形成在半导体裸片106的背侧上的漏极端子的漏极连接。在这方面,半导体裸片106可以是场效应晶体管。
同样地,半导体裸片106可以是双极结型晶体管。第一引线112可以形成到半导体裸片106的顶侧上的集电极端子110的集电极连接。第二引线116可以形成到也形成在半导体裸片108的顶侧上的基极端子118的基极连接。底部外部引线103可以形成到形成在半导体裸片106的背侧上的发射极端子的发射极连接。
图5a示出了线夹框架结构104的增加的厚度的布置,其示出了图2a至图2c、图3a和图3b的散热片部分107。当与图1a至图1c、图4a和图4b中示出的布置相比时,包括由单个金属片形成的散热片部分107的线夹框架结构104的顶表面与模制化合物126的顶部共面,使得具有散热片107的线夹框架结构104通过模制材料126被暴露。如上所述,使用适当的接合材料(例如,焊料或导电粘合剂)将半导体裸片106附接到裸片附接结构102,并且使用类似的接合材料将线夹框架结构104附接至半导体裸片106。通过模制材料126暴露的具有散热片部分107的线夹框架结构104的增加的厚度导致从半导体裸片106的顶侧(例如,源极区)的散热能力增加。
图5b示出了图5a的布置的替代布置,其中线夹框架结构104包括布置在线夹框架结构104上以形成散热片部分107的附加金属结构109。与图5a的布置一样,附加金属结构与模制材料126的顶部共面,使得散热片部分107通过模制材料126暴露。同样地,使用适当的接合材料(例如,焊料或导电粘合剂)将半导体裸片106附接至裸片附接结构102,并且使用类似的接合材料将线夹框架结构104附接至半导体裸片106。使用类似的粘合剂材料将附加金属结构109附接至线夹框架结构104。
图6a至图6c示出了第一线夹支撑构件122和第二线夹支撑构件124的替代布置。在该布置中,第一线夹支撑构件122可以被布置成从线夹框架结构104的与引线112从其延伸的一侧相邻的一侧延伸。第二线夹支撑构件124还可以从线夹框架结构的与第一线夹支撑构件122相对的一侧延伸。第一线夹支撑构件122和第二线夹支撑构件124可以是坝条128的延伸部。与图1a至图1c和图2a至图2c的布置一样,第一线夹支撑构件122和第二线夹支撑构件124的功能是为裸片附接结构102上的线夹框架结构104提供支撑,并且防止线夹框架结构在放置或附接到半导体裸片106期间倾斜。此外,第一线夹支撑构件122和第二线夹支撑构件124在线夹框架结构上而不是在引线框架上的布置允许裸片附接结构被形成为实质上平坦的。这允许裸片附接结构的低成本制造。此外,第一线夹支撑构件122和第二线夹支撑构件124形成为坝条128的延伸部意味着第一线夹支撑构件122 和第二线夹支撑构件124将在引线分割的步骤期间被移除,并且因此,第一线夹支撑构件122和第二线夹支撑构件124在分割之后将不延伸穿过模制材料126。这可以防止从底部外部引线103到线夹框架结构的任何不需要的电流泄漏路径。此外,不需要额外的处理步骤来移除第一线夹支撑构件122和第二线夹支撑构件124,因为它们将在坝条128的移除期间被移除。
虽然图6a至图6b示出了线夹框架结构104的增加的厚度的布置,但是本领域技术人员将理解,其不限于此并且也适用于图1a至图1c或图5a的线夹框架结构104。
图7a至图7g示出了根据实施例的用于制造半导体器件的处理流程步骤。该处理在图7a处开始,由此提供裸片附接结构102。该过程在图7b处继续,由此通过例如丝网印刷(screen printing)来分配诸如焊料或导电胶的接合材料。接合材料被分配在裸片附接结构上以用于以下附接:在裸片附接部分702处的半导体裸片106;线夹框架结构的第一线夹支撑构件122和第二线夹支撑构件124的后面的连接件704;以及支撑构件114的连接件706。如图7c所示,然后将半导体裸片106附接至裸片附接部分702处的接合材料,从而将半导体裸片106的底部触点机械和电连接至裸片附接结构102。在连接半导体裸片106之后,接合材料也被分配在半导体裸片106的一个或多个顶部触点708上。这允许线夹框架结构104电和机械的连接到半导体裸片106的一个或多个顶部触点。
该处理在图7e继续,由此,然后将线夹框架结构附接到裸片附接结构102和半导体裸片106。线夹框架结构104与裸片附接结构102和半导体裸片106对准。因此,线夹框架结构连接到半导体裸片106的接合材料708,从而与其形成电连接。此外,第一线夹支撑构件122和第二线夹支撑构件124连接到裸片附接结构102上的相应接合材料位置704。此外,线夹框架结构104的引线支撑构件114连接到裸片附接结构上的接合材料位置706。在焊接的情况下,裸片附接结构102和线夹框架结构104经历回流处理并且被允许冷却以形成相应的连接。如所提及的,本领域技术人员将理解,接合材料可以是焊料、导电胶或粘合剂材料。在导电胶或粘合剂的情况下,结构被固化以形成相应的连接。从以上讨论中,线夹框架结构104因此被安装在裸片附接结构102和半导体裸片106上。因此,线夹框架结构104被支撑在至少四个位置中,即:在焊接位置706处的引线支撑构件114;在相应的焊接位置704处的第一线夹支撑构件122和第二线夹支撑构件124中的每一个;以及在半导体裸片106上的一个或多个焊接位置708上。
在线夹框架结构104的放置和附接之后,将裸片封装在模制材料126中,如图7g所示。模制处理可以是任何适当的模制处理,诸如,腔模制或膜辅助模制。
在模制之后,如在图7g中示出的,然后使用被称为修整成形分割(trim-form-singulation)的处理来处理该布置以将线夹框架结构104与裸片附接结构102分离。这通过移除坝条128并从支撑构件114修整引线112来实现。接头部分103也与裸片附接结构102分离。第一线夹支撑构件122和第二线夹支撑构件124也被切断以与模制化合物126的侧面一致。然后,将引线112形成为其适当的几何形状,并且可以可选地对引线112进行电镀。
在上述处理流程讨论中,示出了两个裸片附接结构102和两个对应的线夹框架结构104。然而,本领域技术人员将理解,这样的结构的数量或布置不限于此并且仅是说明性的。可以提供结构的任何数量或布置,诸如矩阵或线性阵列。本领域技术人员还将理解,上述过程适用于图1a至图1c或图6a至图6c的布置。然而,在图6a至图6c的布置的情况下,第一线夹支撑构件122和第二线夹支撑构件124将在移除坝条128的同时被移除。
图8a至图8d示出了根据图5b的布置的用于制造半导体器件的处理流程步骤。处理流程与图7a至图7e的处理流程相同。在图7e之后,其中线夹框架结构附接至裸片附接结构102和半导体裸片106,该处理继续到图8a,由此通过例如丝网印刷将焊料802或导电胶分配在半导体裸片106上的线夹框架结构上。如图8b所示,使用焊料802将附加金属结构109固定在线夹框架结构104上。图8c至图8d 的剩余处理与图7f和图7g的处理类似。
考虑到上述内容,本领域技术人员将看到,上述实施例和过程步骤的各个方面可以互换。例如,从坝条128延伸的支撑构件122、支撑构件124的布置可以与图1a至图1c和图5a和图5b的散热片部分107的布置一起使用。
可选地,在模制处理之后,半导体器件的顶部可以被抛光以从暴露的线夹框架结构去除任何过量的模制化合物。
在所附的独立权利要求中阐述了本发明的特定和优选方面。来自从属权利要求和/或独立权利要求的特征的组合可以适当地组合,而不仅仅是如在权利要求中所阐述的。
本公开的范围包括其中明确地或隐含地或其任何一般化所公开的任何新颖特征或特征的组合,而不管其是否涉及所要求保护的发明或阻碍由本发明解决的任何或所有问题。申请人在此通知,在本申请的审查期间或从其中得出的任何这样的另外的申请的审查期间,新的权利要求可以被解释为这样的特征。具体地,参考所附权利要求,来自从属权利要求的特征可以与独立权利要求的特征组合,并且来自相应的独立权利要求的特征可以以任何适当的方式组合,而不仅仅是在权利要求中列举的特定组合中。
在单独的实施例的上下文中描述的特征也可以结合单个实施例被提供。相反地,为了简洁起见,在单个实施例的上下文中描述的各种特征也可以单独地或以任何合适的子组合来提供。
术语“包括”不排除其它元件或步骤,术语“一个”不排除多个。权利要求中的参考符号不应被解释为限制权利要求的范围。
Claims (15)
1.一种用于半导体器件的引线框架组件,所述引线框架组件包括:
裸片附接结构和线夹框架结构;
所述线夹框架结构包括:
裸片连接部分,所述裸片连接部分被配置和布置用于接触半导体裸片的顶侧上的一个或多个接触端子;
一个或多个电引线以及引线支撑构件,所述一个或多个电引线在第一端处从所述裸片连接部分延伸,并且引线支撑构件从所述一个或多个引线的第二端延伸;以及
与所述一个或多个电引线正交布置的多个线夹支撑构件,其中所述多个线夹支撑构件和所述引线支撑构件被配置和布置成接触所述裸片附接结构;
其中,所述多个线夹支撑构件被布置在所述裸片连接部分和所述引线支撑构件之间的所述一个或多个电引线上。
2.根据权利要求1所述的引线框架组件,其中,所述多个线夹支撑构件布置在所述裸片连接部分上。
3.根据权利要求2所述的引线框架组件,还包括横跨所述一个或多个电引线正交地延伸的坝条,其中,所述线夹支撑构件中的每一个整体地形成在所述坝条的相应端部处。
4.根据权利要求1至3中任一项所述的引线框架组件,其中,所述线夹框架结构由单个整片的导电材料形成。
5.根据权利要求1至3中任一项所述的引线框架组件,还包括布置在所述裸片连接部分上的散热片构件。
6.根据权利要求4所述的引线框架组件,还包括布置在所述裸片连接部分上的散热片构件。
7.一种半导体器件,包括根据权利要求1至6中任一项所述的引线框架组件,并且还包括布置在所述裸片附接结构上的半导体裸片和包封所述半导体裸片的模制材料。
8.根据权利要求7所述的半导体器件,其中,使用接合材料将所述裸片连接部分连接到所述半导体裸片的顶侧接触部分。
9.根据权利要求8所述的半导体器件,其中,所述接合材料的厚度在接合的区域上实质上相等。
10.根据权利要求7至9中任一项所述的半导体器件,其中,所述裸片连接部分实质上平行于所述半导体裸片的顶侧。
11.根据权利要求7至9中的任一项所述的半导体器件,其中,当从属于权利要求5或6时,散热片构件的顶表面与所述模制材料的顶表面实质上共面。
12.根据权利要求11所述的半导体器件,其中,使用接合材料将所述散热片构件附接至所述裸片连接部分。
13.根据权利要求7至9中任一项所述的半导体器件,其中,使用接合材料将所述裸片附接结构附接到所述半导体裸片的背侧接触部分。
14.一种制造半导体器件的方法,所述方法包括:
提供裸片附接结构;将半导体裸片固定到所述裸片附接结构;将线夹框架结构附接到所述裸片附接结构和所述半导体裸片;其中,所述线夹框架结构包括:
裸片连接部分,所述裸片连接部分被配置和布置用于接触所述半导体裸片的顶侧上的一个或多个接触端子;
一个或多个电引线以及引线支撑构件,所述一个或多个电引线在第一端处从所述裸片连接部分延伸,并且所述引线支撑构件从所述一个或多个引线的第二端延伸;
以及与所述一个或多个电引线正交布置的多个线夹支撑构件,其中所述多个线夹支撑构件和所述引线支撑构件被配置和布置成接触所述裸片附接结构;
其中,所述多个线夹支撑构件被布置在所述裸片连接部分和所述引线支撑构件之间的所述一个或多个电引线上。
15.根据权利要求14所述的方法,其中,所述线夹支撑构件固定地连接到所述裸片附接结构。
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