CN107305872A - 防止集成电路内的线间多孔电介质过早击穿的新颖保护 - Google Patents
防止集成电路内的线间多孔电介质过早击穿的新颖保护 Download PDFInfo
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Abstract
本发明的实施例涉及防止集成电路内的线间多孔电介质过早击穿的新颖保护。使用堆叠,其包括双钝化(CPSI、CPSS)并且被局部蚀刻以暴露集成电路的位于集成电路的互连部分的最后金属化层级之上的接触垫(PLCT),以保护上述集成电路防止至少一个电介质区域的击穿。至少一个电介质区域至少部分多孔,并且分离集成电路的互连部分的两个导电元件。击穿由上述至少一个电介质区域内的缺陷的存在所辅助的电传导引起。
Description
技术领域
本发明的实现方式和实施例涉及集成电路,具体地涉及CMOS技术方法,并且更具体地涉及防止集成电路的互连部分(通常称为字首组合词BEOL(后端制程))内的线间多孔电介质过早击穿的保护。
背景技术
在传统方式中,集成电路的互连部分包括至少一个金属化层级,并且通常包括若干金属化层级,每个金属化层级包括导线,例如,诸如铜线的金属线,使得集成电路的各个部件可以彼此互连和/或互连至集成电路的输入-输出。
为了补充这个互连,根据本领域的技术人员通常使用的术语,该互连部分还通常包括一个或多个过孔层级,过孔层级位于金属化层级之间并且使得可以将某些金属线链接在一起。
在某些情况下,可能发生分离两个金属线的线间电介质区域的过早击穿,特别是在这两个金属线分开非常小的距离时,例如等于由所使用的CMOS技术节点指示的最小距离。
随着CMOS技术节点变得越来越先进,也就是说当这一最小距离变得越来更小时,这越来越关键。
在根据No.1559337提交的法国专利申请中指出,这一过早击穿现象特别发生在两个金属线之间施加的电势差的存在与水分和/或离子污染渗入到电介质中相结合,特别是当电介质多孔时。
因此,从此推断出,这一过早击穿现象是归因于在电介质中的缺陷(陷阱)的存在所辅助的传导机制。更确切地,然后电子通过位于电介质的禁带中的、被假定为电离中心(电子施主)的状态之间的跳跃而传播。这一效应源自于,在施加电场(线之间的电势差)的情况下这些中心的电离能的下降。这一传导机制之后被称为普尔-夫伦克尔(Poole-Frenkel)电流的电流证明,普尔-夫伦克尔电流使用以通用方式证明电介质内的这种机制的两个人的名字命名。
在前述法国专利申请中,建议通过使用至少一个非多孔电介质阻挡件而提供对这一过早电介质击穿的解决方案,至少一个非多孔电介质阻挡件被插入至少一个电介质区域的多孔部分和两个导电元件(例如,集成电路的互连部分的金属轨道或线或过孔)的至少一个之间,以便保护该集成电路防止上述至少一个电介质区域的击穿,该击穿由在上述至少一个电介质区域内的缺陷的存在所辅助的电传导引起。
换言之,该解决方案旨在尽可能地断裂容易在电介质中长期或多或少存在的传导路径,即通过使用至少一个非多孔电介质阻挡件,尽可能地避免普尔-夫伦克尔类型的漏电流在由该电介质区域分离的两个导电元件之间流动。
尽管如此,发明人已经注意到,某些情况有利于互连部分的多孔电介质区域中水分的出现。这种情况特别是当集成电路位于不断供电的设备(诸如例如TV解码器)内,在这种情况下集成电路的温度可能接近60-70摄氏度。
现在,如在上文指示的,这种水分可能导致在多孔电介质中产生传导路径。
即使前述法国专利申请中描述的解决方案是令人满意的,但仍然存在尽可能减少或甚至消除集成电路的多孔电介质区域内水分出现的需求,并且这将因此减少过早电介质击穿的风险。
发明内容
根据本发明的一个实现方式和实施例,因此建议提供对这个需求的解决方案。
一种集成电路总体上包括上述互连部分(BEOL)、局部蚀刻封装层、通常为TEOS(四乙氧基硅烷)类型的氧化物,氧化物覆盖有经蚀刻的导电层(例如,铝),其旨在用于形成接触垫以使得可以将集成电路与外部连接,并且用于形成金属线,金属线旨在传送供电电压或者用于形成具有特别是在安全芯片中使用的特殊功能的特殊图案。
这一经蚀刻的导电层本身覆盖有绝缘层,通常为填充氧化物,例如也是TEOS类型氧化物。有利地,绝缘层在高密度等离子体(HDP)帮助下被沉积并且使得可以在该电气层的经蚀刻的部分之间插入间隙。
该绝缘层本身覆盖有相对厚的上部钝化层,上部钝化层确保对集成电路的机械保护和化学保护。
绝缘层-钝化层堆叠被蚀刻以暴露接触垫。
在很多研究之后,发明人惊讶地注意到,绝缘层,特别是TEOS氧化物类型的绝缘层形成水分的入口路径,尽管在前述法国专利申请中引用该材料能够借助于非多孔电介质阻挡件被用来尽可能地避免普尔-夫伦克尔类型的漏电流的流动。
换言之,发明人注意到TEOS类型氧化物的这一非多孔特性不足以使得该材料不渗透水分,因此接触垫的层级的堆叠的侧面是水分向集成电路渗透的入口。
因此,特别建议通过使用堆叠提供该问题的解决方案,堆叠包括第一非多孔下部钝化层、电绝缘层和上部钝化层,堆叠被局部蚀刻以便暴露集成电路的上述接触垫,接触垫位于集成电路的互连部分的最后金属化层级之上,从而保护上述集成电路防止至少一个电介质区域的击穿,至少一个电介质区域至少部分多孔,分离集成电路的互连部分的两个导电元件,击穿由上述至少一个电介质区域内的缺陷的存在所辅助的电传导引起。
换言之,代替保护接触垫的层级处的堆叠的侧面,在经蚀刻的导电层和经蚀刻的封装层的一个或多个暴露的部分上,沉积特别是对水分的非多孔下部钝化层(例如氮化硅SiN),以便使用该非多孔下部钝化层补充上述堆叠。
这样的解决方案与CMOS技术方法是高度兼容的,因为其仅要求添加单个方法步骤(下部钝化层的形成),而不要求掩模的任何修改或添加,也不要求对集成电路的布图的任何修改。
另外,这个新型解决方案与在前述法国专利申请中描述的解决方案(在多孔电介质内使用非多孔电介质阻挡件)兼容。
因此,根据一个方面,提议一种用于保护集成电路防止由电介质区域内缺陷的存在所辅助的电传导的方法。电介质区域至少部分多孔,分离集成电路的互连部分的两个导电元件。该方法包括在蚀刻封装层和蚀刻导电层之后,在经蚀刻的导电层和经蚀刻的封装层的一个或多个暴露的部分上形成堆叠,封装层在上述互连部分的最后金属化级之上形成,导电层位于上述经蚀刻的封装层之上并且至少旨在用于形成接触垫,以及局部蚀刻上述堆叠以暴露上述接触垫,堆叠包括非多孔下部钝化层、电绝缘层和上部钝化层。
根据一个实现方式,非多孔下部钝化层由数量比阈值S小的孔隙率表示。
例如,该阈值S等于5%。
换言之,非多孔下部钝化层呈现小于该下部钝化层的总体积的S%的孔隙体积。
该下部钝化层的厚度必须不能太小以便保证它的抗水分阻挡功能,并且必须不能太厚以便能够紧靠(例如,铝的)经蚀刻的导电层的形状。
本领域技术人员将了解如何根据情况调整这一厚度。
尽管如此,通过指示的方式,50nm和150nm之间的下部钝化层的厚度是良好的折衷。
例如,下部钝化层包括氮化硅SiN。尽管如此,可以使用其他材料,例如诸如SixNy类型的任意材料,诸如例如Si3N4。
有利地,上部钝化层比下部钝化层厚并且也可以包括氮化硅SiN。
根据另一方面,提出了一种集成电路,包括:
互连部分(“BEOL”),
封装层,其位于互连部分的最后金属化层级之上,
导电层,其位于上述封装层之上,并且形成至少一个接触垫,至少一个接触垫通过上述封装层接触最后金属化层级的金属轨道,以及
钝化层,其在上述导电层之上和上述封装层的部分之上,上述钝化堆叠拥有与上述接触垫相对地展开的开孔并且包括(例如SiN的)非多孔下部钝化层、电绝缘层(例如TEOS类型氧化物)以及上部钝化层(例如SiN),有利地,上部钝化层比下部钝化层厚。
根据一个实施例,非多孔下部钝化层呈现数量小于阈值的孔隙率,阈值例如等于5%,下部钝化层的厚度可以在50nm和150nm之间。
如之前所指出的,本解决方案(双钝化)可以被组合在与前述法国专利申请No.1559337中描述的解决方案(插入到多孔电介质中的电介质阻挡件)相同的集成电路内。
换言之,根据一个实施例,互连部分包括至少一个金属化层级,金属化层级拥有被电介质区域互相分离的导电元件,并且集成电路包括位于至少一个电介质区域的多孔部分与被上述至少一个电介质区域分离的两个导电元件中的至少一个之间的至少一个非多孔电介质阻挡件。
优选地,上述至少一个非多孔电介质阻挡件具有位于低厚度和高厚度之间的厚度。
低厚度是为获得关于电介质的漏电流的良好的阻挡效果的可接受的极限厚度,同时高厚度被选择以便极度地增大电介质区域的介电常数,电介质区域包括非多孔电介质阻挡件和优选地具有低介电常数的多孔部分。
通过指示,在10nm和30nm之间的非多孔电介质阻挡件的厚度是可接受的。
大量材料可以被用于上述至少一个非多孔电介质阻挡件。例如,可以使用三元氮化物或四乙基氧基硅烷或四乙氧基硅烷(TEOS类型氧化物)。
尽管如此,碳氮化硅(SiCN),非晶的或晶体的,是优选的材料,特别是由于它对电介质区域的多孔中心部分的垂直侧面具有良好的粘附性。
附图说明
通过详细阅读对完全非限制性的实现方式和实施例的详细说明和附图,本发明的其他优点和特性将变得明显,其中:
-图1示意性地图示现有技术的示例性集成电路,以及
-图2到图7示意性地图示本发明的各个实现方式和实施例。
具体实施方式
图1图示根据现有技术的示例性的集成电路IC。在图1中,标记RITX指示集成电路的互连部分(BEOL)。
该互连部分RITX包括若干金属化层级和若干过孔层级。
在该图1中,仅标记了倒数第二金属化层级Mn-1和最后金属化层级Mn。
例如铜的各个金属轨道以及各个过孔被覆盖在电介质材料中,电介质材料通常被本领域的技术人员称为首字母缩略词IMD(金属间电介质)。
标记8在这里指示电介质区域,电介质区域覆盖金属化层级Mn的金属轨道以及金属化层级Mn-1的金属轨道和在该金属化层级处到达顶点的过孔。
在这些区域8中使用的电介质材料是具有低介电常数的多孔材料(低K材料)。例如,使用的材料是掺杂碳的氢化氧化硅(SiOCH),其具有在20和30之间的孔隙率百分比以及等于3的介电常数K。
每个IMD区域8被封装在两个保护层10之间,两个保护层10平行于衬底并且旨在保护金属轨道的金属不被氧化。例如,可以使用碳氮化硅(SiCN),其可以保护铜金属轨道不被氧化并且还防止铜扩散到IMD电介质材料中。
在传统方式中,集成电路IC还包括封装层CCAP,封装层CCAP位于互连部分RITX的最后金属化层级Mn之上。例如,该封装层CCAP由TEOS类型氧化物制成并且被局部蚀刻以允许例如铝的接触垫PLCT接触例如上部金属化层级Mn的金属轨道Pn。
该接触垫PLCT由导电层CC(这里是铝)的蚀刻导致,并且如该图1中所图示,该层CC还能够用于产生铝图案BLC1、BLC2、例如接触其他接触垫的线(未在该图中表示,该线能够被用于传送电源信号)或者用于其他功能(诸如例如并入安全芯片的网状结构的形成)的其他线。
之后,经蚀刻的层CC用绝缘层CIS覆盖。通常,绝缘层CIS是通过高密度等离子体(HDP)沉积的TEOS类型的氧化物,特别地,其使得可以在层CC的图案之间适当地插入间隙。
集成电路IC最后在绝缘层CIS之上包括例如通常5500埃的量级厚的上部钝化层CPSS,其确保对集成电路的机械保护和化学保护。
由绝缘层CIS和上部钝化层CPSS形成的这一堆叠被蚀刻以使得与接触垫PLCT相对地展开开孔。
这样一来,如在上文解释的,这一堆叠EMPL,特别是绝缘层,是水分的进入点,水分之后可能将在多孔电介质8中产生导电路径。
现在更具体地参照图2到图6,其图示根据本发明的一个实现方式的不同步骤,使得有可能最大程度上限制或者甚至消除水分从外部环境进入到芯片中。
在这些附图中,相似元件或者具有与图1描述的那些元件相似功能的元件,具有与图1中它们具有的标记相同的标记。
在图2中描述的是导电层CC,其在被蚀刻之后,已经形成了接触垫PLCT以及图案BLC1和BLC2。
代替直接沉积绝缘层CIS,首先沉积没有上部钝化层CPSS厚的下部钝化层CPSI(通常具有50nm到150nm之间的厚度)(图3)。
该下部钝化层CPSI是非多孔的,特别是对于水分,并且例如可以由氮化硅SiN形成。
之后,沉积例如TEOS类型氧化物的绝缘层CIS(图4),并且然后如图5中所图示的,覆盖整个上部钝化层CPSS。
在蚀刻包含下部钝化层CPSI、绝缘层CIS和上部钝化层CPSS的堆叠EMPL以使得与接触垫PLCT相对地展开开孔OUV之后,获得图6所图示的结构。
该结构因此区别于图1中所图示的现有技术,在于包含双钝化(下部钝化层CPSI和上部钝化层CPSS)的堆叠EMPL。因此,水分从堆叠EMPL的侧面通过绝缘层的可能的迁移将由于非多孔下部绝缘层CPSI的存在而很大程度地阻碍或甚至阻挡。
因此,已经使得可以很大程度地限制或甚至消除水分从外面进入到集成电路IC的多孔电介质中,并且这将因此限制该多孔电介质的过早击穿的风险。
另外,该新方法与传统CMOS方法完美兼容并且只需要添加一个额外步骤,即下部钝化层CPSI的沉积。
图6中所图示的实施例能够与图7中所图示的实施例组合,如在前述法国专利申请No.1559337中描述的,图7中所示的实施例提供对至少一个非多孔电介质阻挡的使用,至少一个非多孔电介质阻挡被插入分离两个金属线的多孔电介质区域中。
图7表示图6的集成电路示例性的底部部分。
更确切地,集成电路IC包括半导体衬底SB,在半导体衬底SB内和半导体衬底SB上已经制作有诸如晶体管的各个部件(为简化的目的,这里未表示)。
这些部件和衬底SB的表面通常覆盖有钝化层1,例如二氧化硅层。
各个部件通过第一电介质区域2与集成电路的互连部分RITX(BEOL)分离,第一电介质区域2通常被本领域的技术人员称为首字母缩略词PMD(金属前电介质)。
如在上文所指示的,互连部分RITX包括若干金属化层级和若干过孔层级。在该示例中,已经表示了三个金属化层级M1、M2和M3与两个相关联的过孔层级V1和V2相关联。
在该示例性实施例中,已经表示了在金属化层级M1内的两个金属轨道或金属线L1和L2以及在第二金属化层级M2的层级处的两个金属轨道L3和L4。
在该示例中,层级M3的金属轨道以及位于过孔层级V1和V2处的过孔位于集成电路的其他位置处,并且因此其未在该图中表示出。
如之前所指示的,(例如铜的)各个金属轨道和过孔被覆盖在IMD(金属间电介质)电介质材料中。
在该图7中,这些电介质区域IMD被标记6、8和11来标记。
平行于衬底并且封装区域IMD 6、8和11的保护层(例如,碳氮化硅(SiCN))被标记为3、7、10和12。
在图7中,看到分离两个金属线L1和L2的线间电介质区域包括多孔中心部分60。多孔中心部分60在这里由SiOCH形成,其两侧为两个电介质阻挡件4和5。两个电介质阻挡件4和5分别位于多孔中心部分60与两个金属线L1和L2之间。
同样地,分离两个线L3和L4的线间电介质区域包括多孔中心部分800。多孔中心部分800由SiOCH形成,其两侧为两个电介质阻挡件90和91。两个电介质阻挡90和91分别位于多孔中心部分800与两个金属线L3和L4之间。
这些电介质阻挡件4、5、90、91由非多孔电介质材料(即,呈现小于5的孔隙率百分比的材料)组成。
在实践中,有利地,使用呈现2到3之间的孔隙率百分比的SiCN作为非多孔电介质阻挡件。
另外,如图7中所看到的,每个金属线本身,例如金属线L4,两侧为两个非多孔电介质阻挡件,即,阻挡件91和阻挡件92。
另外,每个金属线的下部部分不与非多孔电介质阻挡件接触以便允许与下面的过孔的可能的电接触。
在图7右侧部分中,更详细地表示了分离金属线L3和L4的线间电介质区域。
应注意,在该右侧部分中,电介质区域被表示为与实际更加接近的梯形形状,因为该形状由蚀刻方法导致。
如上文所解释的,如果水分或离子污染存在,并且也由于电介质区域的梯形形状,陷阱密度在界面处增加,并且在该界面处离子的增加的存在有助于漏电流Ⅰ(缺陷辅助电流)的产生。这样一来,非多孔电介质阻挡件90和91的存在使得可以中断两个金属线之间的导电路径,并且因此使得很大程度地降低或甚至消除这一漏电流Ⅰ。
因此,特别地结合图6所描述的双钝化使得可以限制或甚至防止水分进入到集成电路中,并且在剩余水分的情况下,非多孔电介质阻挡件的存在使得可以中断两个金属线之间的导电路径,并且因此使得可以很大程度地降低或甚至消除漏电流Ⅰ。
因此,更加有效地保护集成电路不经受线间电介质区域的过早击穿。
Claims (16)
1.一种用于保护集成电路以防电介质区域(8)内存在的缺陷所辅助的电传导的方法,所述电介质区域是至少部分多孔的,分离所述集成电路的互连部分的两个导电元件,所述方法包括:
在蚀刻封装层(CCAP)和蚀刻导电层(CC)之后,在经蚀刻的所述封装层的一个或多个暴露部分和经蚀刻的所述导电层上形成堆叠(EMPL),所述封装层形成在所述互连部分(RITX)的最后金属化层级(Mn)之上,所述导电层位于经蚀刻的所述封装层之上并且至少旨在用于形成接触垫(PLCT),所述堆叠包括非多孔下部钝化层(CPSI)、电绝缘层(CIS)和上部钝化层(CPSS);以及
局部蚀刻所述堆叠(EMPL)以暴露所述接触垫(PLCT)。
2.根据权利要求1所述的方法,其中所述非多孔下部钝化层(CPSI)呈现数量比阈值小的孔隙率。
3.根据权利要求2所述的方法,其中所述阈值等于5%。
4.根据前述权利要求中的一项所述的方法,其中所述下部钝化层(CPSI)的厚度位于50nm和150nm之间。
5.根据前述权利要求中的一项所述的方法,其中所述下部钝化层(CPSI)包括氮化硅SiN或SixNy类型的任何材料。
6.根据前述权利要求中的一项所述的方法,其中所述上部钝化层(CPSS)比所述下部钝化层(CPSI)厚。
7.根据权利要求6所述的方法,其中所述上部钝化层(CPSS)包括氮化硅SiN。
8.包括非多孔下部钝化层(CPSI)、电绝缘层(CIS)和上部钝化层(CPSS)的堆叠(EMPL)的使用方法,并且所述堆叠被局部蚀刻以暴露集成电路的接触垫(PLCT),所述接触垫(PLCT)位于所述集成电路的互连部分(RITX)的最后金属化层级(Mn)之上,以保护所述集成电路以防至少一个电介质区域(8)的击穿,所述至少一个电介质区域是至少部分多孔的,分离所述集成电路的所述互连部分的两个导电元件,击穿由所述至少一个电介质区域内所存在的缺陷辅助的电传导引起。
9.一种集成电路,包括:
互连部分(RITX);
封装层(CCAP),其位于所述互连部分的最后金属化层级(Mn)之上;
导电层(CC),其位于所述封装层之上,并且形成接触垫(PLCT),所述接触垫通过所述封装层接触所述最后金属化层级的金属轨道(Pn);以及
钝化堆叠(EMPL),其在所述导电层(CC)之上和所述封装层(CCAP)的部分之上,所述钝化堆叠拥有与所述接触垫相对地展开的开孔(OUV)并且包括非多孔下部钝化层(CPSI)、电绝缘层(CIS)以及上部钝化层(CPSS)。
10.根据权利要求9所述的集成电路,其中所述非多孔下部钝化层(CPSI)呈现数量比阈值小的孔隙率。
11.根据权利要求10所述的集成电路,其中所述阈值等于5%。
12.根据权利要求9到11中的一项所述的集成电路,其中所述下部钝化层(CPSI)的厚度位于50nm和150nm之间。
13.根据权利要求9到12中的一项所述的集成电路,其中所述下部钝化层(CPSI)包括氮化硅SiN或SixNy类型的任何材料。
14.根据权利要求9到13中的一项所述的集成电路,其中所述上部钝化层(CPSS)比所述下部钝化层(CPSI)厚。
15.根据权利要求14所述的集成电路,其中所述上部钝化层(CPSS)包括氮化硅SiN。
16.根据权利要求9到15中的一项所述的集成电路,其中所述互连部分(RITX)包括至少一个金属化层级,所述金属化层级拥有被电介质区域交替分离的导电元件(L3、L4),并且所述集成电路包括至少一个非多孔电介质阻挡件(90、91),所述至少一个非多孔电介质阻挡件(90、91)位于至少一个电介质区域的多孔部分(800)和两个所述导电元件(L3、L4)中的至少一个之间,两个所述导电元件(L3、L4)被所述至少一个电介质区域分离。
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FR1653451A FR3050318B1 (fr) | 2016-04-19 | 2016-04-19 | Nouvelle protection contre le claquage premature de dielectriques poreux interlignes au sein d'un circuit integre |
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CN201611036400.3A Active CN107305872B (zh) | 2016-04-19 | 2016-11-23 | 防止集成电路内的线间多孔电介质过早击穿的保护 |
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FR3050318B1 (fr) * | 2016-04-19 | 2018-05-11 | Stmicroelectronics (Rousset) Sas | Nouvelle protection contre le claquage premature de dielectriques poreux interlignes au sein d'un circuit integre |
US11211301B2 (en) * | 2020-02-11 | 2021-12-28 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method of manufacture |
CN113725167B (zh) * | 2020-05-25 | 2023-08-15 | 联华电子股份有限公司 | 集成电路元件及其制作方法 |
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US20190172786A1 (en) | 2019-06-06 |
US10229880B2 (en) | 2019-03-12 |
CN107305872B (zh) | 2020-03-31 |
US20170301623A1 (en) | 2017-10-19 |
CN206259338U (zh) | 2017-06-16 |
FR3050318B1 (fr) | 2018-05-11 |
FR3050318A1 (fr) | 2017-10-20 |
US10796992B2 (en) | 2020-10-06 |
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