CN107210222B - 外延涂布的半导体晶圆和生产外延涂布的半导体晶圆的方法 - Google Patents

外延涂布的半导体晶圆和生产外延涂布的半导体晶圆的方法 Download PDF

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CN107210222B
CN107210222B CN201580073919.6A CN201580073919A CN107210222B CN 107210222 B CN107210222 B CN 107210222B CN 201580073919 A CN201580073919 A CN 201580073919A CN 107210222 B CN107210222 B CN 107210222B
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T·米勒
M·格姆利希
F·法勒
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Abstract

本发明涉及外延涂布的半导体晶圆，包含：由单晶硅构成的衬底晶圆；在衬底晶圆的正面上由硅构成的具有抛光表面的外延层，其中抛光表面相对于面积为10μm×10μm的测量窗具有不大于0.055nm的RMS粗糙度；具有不小于6μm且不大于14μm的深度的洁净区；和邻近洁净区且具有可以发展成BMD的BMD核的区域，BMD在离外延层的抛光表面不超过70μm的距离处具有不小于3.5×109cm‑3的峰密度。本发明还涉及用于生产外延涂布的半导体晶圆的方法，包括：在衬底晶圆的正面上沉积由硅构成的外延层；用氧化剂处理外延层；对外延涂布的半导体晶圆进行RTA处理，其中将外延层暴露于由氩和氨组成的气氛中，并且在外延层上形成氧氮化物层；去除氮氧化物层；和抛光外延层。

Description

外延涂布的半导体晶圆和生产外延涂布的半导体晶圆的方法
本发明涉及一种外延涂布的半导体晶圆(wafer)，包含由单晶硅构成的衬底晶圆、在衬底晶圆的正面上由硅构成的抛光外延层、从抛光外延层延伸到衬底晶圆中的洁净区(denuded zone)以及邻近洁净区并具有BMD核的区域。本发明还涉及用于生产外延涂布的半导体晶圆的方法。
洁净区是外延涂布的半导体晶圆的近表面区域，其中不形成被称作BMD(bulkmicro defect，体内微缺陷)的氧沉淀物。所述区域从外延涂布的半导体晶圆的上侧表面延伸到主体中。洁净区通常作为用于容纳电子部件的位置提供。
洁净区与延伸到半导体晶圆主体中并且其中存在BMD核的另外的区域相邻。BMD核通过热处理发展成BMD。BMD作为内部吸着剂(getter)的中心，特别是可以结合金属杂质。在主要用于在洁净区中构建电子部件的热处理过程中BMD核也可发展成BMD。
一种趋势追求的目标是尽可能近地邻近洁净区提供最高可能密度的BMD。另一个趋势追求的目标是将洁净区的深度限制于容纳电子部件必需的量。
已知在具有氮化作用的气氛中半导体晶圆的瞬时快速加热和冷却注入空位并且空位的存在支持半导体晶圆主体中的BMD核的成核。通过瞬时快速加热和冷却的热处理也称作RTA(rapid thermal anneal，快速热退火)处理。
US 2002/0127766 A1描述了一种用于生产半导体晶圆的方法，所述晶圆由包括抛光外延层、洁净区和具有BMD核的区域的单晶硅构成。该方法包括在沉积外延层之后的RTA处理。
RTA处理(特别是施用于外延涂布的半导体晶圆的RTA处理)造成与引起晶格滑移问题相关的热负荷。此外，RTA处理还增加了外延层表面的粗糙度。通常，AFM(原子力显微镜)测定的RMS粗糙度升高，并且检测到被称作LLS缺陷(localized light scatterer，局部光散射体)的相对高数目的散射光中心，其中这些缺陷的密度在外延层表面的边缘区域中特别高。
US2002/0022351 A1提出了在沉积外延层之前在氯化氢气体和硅烷源的存在下对衬底晶圆表面进行光滑化。然而，该方法对其沉积之后损害外延层表面粗糙度的过程没有影响。
因此，本发明的目的是提供一种改进的方法，该方法提供一种外延涂布的半导体晶圆，其由具有关于洁净区和BMD核以及外延层表面粗糙度的特定性能的硅构成。
该目的通过外延涂布的半导体晶圆实现，所述半导体晶圆包含
由单晶硅构成的具有正面且具有背面的衬底晶圆；
在衬底晶圆的正面上由硅构成的具有抛光表面的外延层，其中抛光表面具有相对于面积为10μm×10μm的测量窗不大于0.055nm的RMS粗糙度；
从外延层的抛光表面向衬底晶圆的背面延伸远至一定深度的洁净区，所述深度在半导体晶圆的中心和边缘之间不小于6μm且不大于14μm；和
邻近洁净区且具有可以发展成BMD的BMD核的区域，BMD在离外延层的抛光表面不超过70μm的距离处具有不小于3.5×109cm-3的峰密度。
在外延层表面的中心区域和表面的边缘区域之间在面积为10μm×10μm的测量窗口中通过AFM确定的的RMS粗糙度之差相对于中心区域的粗糙度优选为不大于5％。
例如通过对外延涂布的半导体晶圆的沉淀-热两阶段处理，在750至850℃的温度下持续1至4小时(第一阶段)，和在950℃至1050℃的温度下持续8至20小时(第二阶段)，使BMD核发展成BMD。然而，也可以通过与主要用于构建电子部件目的而进行的相当的外延涂布的半导体晶圆热处理使BMD核发展成BMD。
衬底晶圆优选地具有至少300mm的直径，并且优选由掺杂的单晶硅组成。掺杂剂是n型的，例如磷，或是p型的，例如硼。在n型掺杂的情况下掺杂度优选为n-，在p型掺杂的情况下，优选为p+，在n型掺杂的情况下，对应于5-80Ωcm的电阻率，在p型掺杂的情况下，对应于5-20mΩcm、优选10-20mΩcm的电阻率。
由单晶硅构成的外延沉积并抛光的层覆盖衬底晶圆的正面。正面是衬底晶圆的上侧表面；背面是衬底晶圆的下侧表面。外延沉积层优选同样地被掺杂，特别优选以涉及n/n-或p/p+外延涂布的半导体晶圆的方式。在未抛光状态下，外延沉积层的厚度优选为不小于1μm且不大于12μm。
由于用于生产外延涂布的半导体晶圆的下述方法的实施，BMD核或已发展成的BMD在半导体晶圆的厚度方向上的分布是不对称的。洁净区的深度不小于6μm且不大于14μm。在这种情况下，BMD核或已发展成的BMD的密度以高上升速率上升到峰密度，并且不太陡峭地下降到远至衬底晶圆背面的保持实际上不变的水平。在将BMD核发展成BMD之后，半导体晶圆的中心和边缘之间半径上的BMD的峰密度不小于3.5×109cm-3，并且在离外延层的抛光表面不大于70μm的距离处。在将BMD核发展成BMD之后，在离外延层的抛光表面50μm的距离处的BMD的密度优选不小于峰密度的70％。已发展成的BMD的从离外延层的抛光表面200μm的距离处远至衬底晶圆背面的密度优选不大于峰密度的60％。
本发明还涉及用于生产外延涂布的半导体晶圆的方法，其包括
提供由单晶硅构成具有正面且具有背面的的衬底晶圆；
在衬底晶圆的正面上沉积由硅构成的外延层；
用氧化剂处理外延层；
在不低于1160℃且不高于1185℃的温度范围内的温度下对外延涂布的半导体晶圆进行RTA处理历时不小于15秒且不超过30秒，其中将外延层暴露于由氩和氨组成的气氛中，并且在外延层上形成氮氧化物层；
去除氮氧化物层；和
将外延层抛光。
所需的衬底晶圆的合适来源是由硅构成的单晶，特别是，其是根据CZ方法提拉的。在所述方法中，使硅在由石英组成的坩埚中熔化，并且单晶在浸入所得熔体中并成长的种晶的末端生长。坩埚材料部分地被熔体溶解，以这种方式提供后来用于发展BMD所需的氧。
将衬底晶圆与多个另外的衬底晶圆一起从单晶切片，并进行机械、化学和化学机械加工步骤，优选为了获得其正面和背面尽可能平坦且彼此平行的衬底晶圆。特别优选具有正面和背面的衬底晶圆，其中至少正面处于抛光状态，并且在正面和背面之间具有同样抛光的边缘。
根据New ASTM使用校准因子，衬底晶圆包含浓度优选不小于4.5×1017原子/cm3、优选不大于7.0×1017原子/cm3的晶格间氧。元素碳和氮可以存在于衬底晶圆中，但优选不是以通常只有通过有意添加这些元素才能实现的浓度。因此，碳的浓度优选不超过8.0×1015原子/cm3，氮的浓度优选不超过1.0×1012原子/cm3。虽然有意添加所提到的元素可能有助于BMD核的形成，但是为了限制形成堆垛层错(stacking faults，OSF缺陷)的可能性并且为了不损害衬底晶圆的电性质，不应该这样进行。
衬底晶圆的抛光正面是外延涂布的，优选通过CVD(化学气相沉积)并优选在单晶圆反应器中进行。衬底晶圆在单晶圆反应器中的涂布可以已知的方式进行，例如如US2010/0213168A1中所述。优选的沉积气体包含三氯硅烷作为硅源。沉积温度优选不低于1110℃且不超过1180℃，特别优选1130℃。此外，沉积气体优选包含n型或p型掺杂剂。沉积的外延层的厚度优选不小于1μm且不大于12μm。该方法步骤的结果是由单晶硅构成的外延涂布的半导体晶圆。
为了准备RTA处理，优选清洁所述半导体晶圆并且用氧化外延层的暴露表面的氧化剂处理外延沉积层。所得氧化物层的厚度大于天然氧化物的厚度。优选地，进行RCA清洁，包括首先用包含氢氧化铵、过氧化氢和水的SC-1清洁溶液，然后用包含氯化氢、过氧化氢和水的SC-2清洁溶液处理半导体晶圆。外延沉积层的后续氧化处理优选使用臭氧作为氧化剂进行。
氧化之后的外延涂布的半导体晶圆的RTA处理包括将所述晶圆快速加热至不低于1160℃且不超过1185℃的温度范围内的温度、优选达1170℃的温度，并将外延涂布的半导体晶圆在该温度下保持不小于15秒且不超过30秒的时间。外延涂布的半导体晶圆从起始温度(其优选在550℃至650℃的范围内)以优选不低于20℃/s且不超过100℃/s的升温速率加热。特别优选在35-75℃/s范围内的升温速率。
为了避免发生滑移，RTA处理温度应尽可能低。因此，RTA处理以这样的方式进行，用氧化剂处理的外延层暴露于由氩和氨的混合物组成的气氛中。氩与氨的比率优选为10:1至24:1，特别优选为20：1。在这种气氛中，预期的空位注入可以在比氮气气氛中低的温度下引发。
为了通过RTA处理使外延涂布的半导体晶圆的负载最小化，优选在RTA处理期间外延涂布的半导体晶圆的背面且因此衬底晶圆的背面在RTA处理温度下暴露于没有任何氮化作用的或几乎没有任何氮化作用的气氛。合适的气氛优选由氮气组成。该措施额外地减少了产生滑移的风险。
在RTA处理结束时，外延涂布的半导体晶圆被快速冷却，优选冷却至不高于500℃的温度。为此，关闭RTA装置的辐射加热就足够了。
由于在由氩和氨组成的气氛中对外延涂布的半导体晶圆进行RTA处理，在外延层上由氧化物层形成包含氮氧化硅的层且在下文被称作氮氧化物层。优选通过蚀刻去除氮氧化物层。优选使用包含不少于0.8％且不超过2.0％氟化氢的含水蚀刻剂作为蚀刻剂。由于正面的粗糙度会增加并且会因此产生颗粒，因此不提供通过抛光来除去氮氧化物层。
仅在已经除去氮氧化物层之后才抛光外延沉积层。材料去除不小于0.05μm且不大于0.2μm的化学机械抛光(CMP)是优选的，并且可以通过使用例如由Applied MaterialsInc.提供的抛光工具来进行。在CMP之后，外延涂布的半导体晶圆有利地进行最终清洁。
此外，优选的是，在去除氮氧化物层之后且在CMP之前，首先清洁外延涂布的半导体晶圆，然后用氧化剂、优选用臭氧处理。再次特别优选的是包括首先用SC-1清洁溶液然后用SC-2清洁溶液处理半导体晶圆的RCA清洁。
以下基于实施例并参考附图对本发明进行更详细的说明。
提供由直径为300mm的单晶硅构成的双侧抛光的衬底晶圆。根据实施例B1的衬底晶圆包含浓度为6.1×1017至6.7×1017原子/cm3(New ASTM)的晶格间氧(interstitialoxygen)，并且为p型掺杂的，电阻率为18至19.5mΩcm。根据实施例B2的衬底晶圆包含浓度为5.3×1017原子/cm3至5.6×1017原子/cm3(New ASTM)的晶格间氧，并且为n型掺杂的，电阻率为29至30Ωcm。使用根据本发明的一系列方法步骤处理衬底晶圆以形成具有抛光外延层的半导体晶圆。外延沉积层的厚度分别为4μm(实施例B1)和9μm(实施例B2)。根据实施例B1的半导体晶圆是p/p+外延涂布的半导体晶圆，根据实施例B2的半导体晶圆是n/n-外延涂布的半导体晶圆。外延沉积层的电阻率在29-30Ωcm范围内。
在所有半导体晶圆的情况下，RTA处理的温度为1175℃，在该温度下的RTA处理的持续时间分别为15秒和25秒(实施例B1)和15秒、25秒和30秒(实施例B2)。将所有的半导体晶圆以75℃/s的升温速率加热到1175℃的温度，并在该温度下在比率为20:1的氩和氨的气氛中处理外延沉积层。此后，半导体晶圆以35℃/s的降温速率冷却。
在RTA处理之后，根据本发明进一步处理半导体晶圆以形成具有抛光的外延层的半导体晶圆，并且随后进行热处理以发展BMD。该热处理在氮气下进行，并且包括经3小时的时间将半导体晶圆首先加热至800℃的温度，随后经16小时的时间加热到1000℃的温度。使用来自Raytex Corporation的MO441型检测仪器通过在断裂边缘处的激光散射进行BMD检测。
关于确定的洁净区深度和确定的BMD密度的数据见下表1。数据具有以下含义：
“HZ”表示在RTA处理温度下RTA处理的持续时间；
“DZ1av.”是指在半导体晶圆半径上平均的洁净区深度；
“BMD av.”是指在半导体晶圆半径上平均的BMD密度；
“BMD峰”是指在半导体晶圆中心确定的BMD的峰密度；和
“BMD 50μm”是指在半导体晶圆的径向中心50μm深度处发现的BMD的密度。
表1
Figure BDA0001354612970000061
表1中关于“DZ av.”的数据表明，洁净区的深度随着RTA处理的持续时间的增加而减小，关于“BMD 50μm”的数据表明，随着RTA处理的持续时间增加，相对于在50μm深度处的峰密度的差异变得越来越小。实际上在所有情况下，洁净区的深度至少对应于外延层的厚度。
图1到图3以代表性的方式示出了根据实施例B1的半导体晶圆在径向中心(r＝0mm)、半径r＝75mm和半径r＝140mm的BMD的深度分布
表2
Figure BDA0001354612970000071
表2包含相对于面积为10μm×10μm的测量窗的RMS粗糙度的值。数据表明，如果根据本发明去除氮氧化物层，则特别是在外延涂布的半导体晶圆的边缘区域中的RMS粗糙度得到改善。标准偏差σ不大于5％。
根据本发明的氮氧化物层的去除对于在抛光外延层之后在抛光表面上发现的LLS缺陷的数目也是特别有利的。表3包含关于散射光中心数目的指示，这些散射光中心在RTA处理之前和在CMP之后在两个外延涂布的半导体晶圆的外延层表面上发现且尺寸为120nm或更大。根据本发明已经生产了半导体晶圆之一，而另一个以几乎相同的方式，但没有去除氮氧化物层。
表3
Figure BDA0001354612970000072

Claims (4)

1.外延涂布的半导体晶圆，包含
由单晶硅构成的具有正面且具有背面的衬底晶圆；
在衬底晶圆的正面上由硅构成的具有抛光表面的外延层，其中抛光表面具有相对于面积为10μm×10μm的测量窗为不大于0.055nm的RMS粗糙度；
从外延层的抛光表面向衬底晶圆的背面延伸远至一定深度的洁净区，所述深度在半导体晶圆的中心和边缘之间，不小于6μm且不大于14μm；
邻近洁净区且具有能发展成BMD的BMD核的区域，BMD在离外延层的抛光表面不超过70μm的距离处具有不小于3.5×109cm-3的峰密度；及
能发展成BMD的BMD核，BMD的从离外延层的抛光表面200μm距离处远至衬底晶圆背面的密度不大于峰密度的60％。
2.根据权利要求1所述的外延涂布的半导体晶圆，其具有能发展成BMD的BMD核，BMD在离外延层的抛光表面50μm的距离处的密度不小于峰密度的70％。
3.一种用于生产外延涂布的半导体晶圆的方法，包括
提供由单晶硅构成的具有正面且具有背面的衬底晶圆；
在衬底晶圆的正面上沉积由硅构成的外延层；
用氧化剂处理外延层；
在不低于1160℃且不高于1185℃的温度范围内的温度下对外延涂布的半导体晶圆进行RTA处理历时不小于15秒且不超过30秒，其中将外延层暴露于由氩和氨组成的气氛中，并且在外延层上形成氮氧化物层，其中衬底晶圆的背面暴露于在RTA处理温度下没有任何氮化作用或几乎没有任何氮化作用的气氛；
去除氮氧化物层；和
将外延层抛光。
4.根据权利要求3所述的方法，其中所述氮氧化物层使用包含不少于0.8％且不超过2.0％氟化氢的含水蚀刻剂去除。
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