CN107205320B

CN107205320B - Circuit substrate patterning manufacturing process and circuit substrate

Info

Publication number: CN107205320B
Application number: CN201610227095.XA
Authority: CN
Inventors: 陈文勇; 陈建彰; 吴国玄; 邱建宏
Original assignee: Chipbond Technology Corp
Current assignee: Chipbond Technology Corp
Priority date: 2016-03-17
Filing date: 2016-04-13
Publication date: 2020-03-17
Anticipated expiration: 2036-04-13
Also published as: TW201735753A; JP6255054B2; JP2017168794A; KR101836298B1; TWI595820B; CN107205320A; KR20170108734A

Abstract

The invention relates to a circuit substrate patterning manufacturing process, which comprises the step of providing a circuit substrate to be patterned. The circuit substrate to be patterned is provided with a bottom plate, a bonding layer and a circuit layer, wherein the bonding layer is positioned between the bottom plate and the circuit layer, the bottom plate is provided with an active layer, part of the bonding layer is embedded into the active layer, so that the active layer embedded with the bonding layer is formed into a mixed layer, a photoresist layer is formed on the circuit layer, and the photoresist layer, the circuit layer, the bonding layer and the bottom plate are sequentially patterned to form the patterned circuit substrate.

Description

Circuit substrate patterning manufacturing process and circuit substrate

Technical Field

The present invention relates to a circuit substrate patterning process and a circuit substrate, and more particularly, to a circuit substrate patterning process and a circuit substrate capable of improving the adhesion of an adhesive (e.g., a filling adhesive such as a non-conductive adhesive or a conductive adhesive).

Background

In the conventional circuit substrate manufacturing process, the surface of the substrate is activated to facilitate the formation of circuits in the subsequent manufacturing process, but the activated surface adsorbs impurities, so that an adhesive (e.g., a filling adhesive such as a non-conductive adhesive or a conductive adhesive) is not easily adhered to the surface of the substrate, and the bonding strength between the circuit substrate and the glass substrate is reduced, thereby improving the adhesion of the adhesive to the surface of the substrate.

Disclosure of Invention

The present invention is directed to a circuit substrate patterning process and a circuit substrate thereof, so as to prevent a bottom plate from adsorbing impurities to affect the adhesion strength between an adhesive (e.g., a filling adhesive such as a non-conductive adhesive or a conductive adhesive) and the bottom plate, thereby resulting in poor reliability of a package structure.

The purpose of the invention and the technical problem to be solved are realized by adopting the following technical scheme. According to the present invention, a process for patterning a circuit substrate comprises: providing a circuit substrate to be patterned, wherein the circuit substrate to be patterned is provided with a bottom plate, a bonding layer and a circuit layer, the bonding layer is positioned between the bottom plate and the circuit layer, the bottom plate is provided with an activated layer and an unactivated layer, the bottom plate is subjected to activation treatment to form the activated layer, and part of the bonding layer is embedded into the activated layer, so that the activated layer embedded with the bonding layer is formed into a mixed layer; forming a photoresist layer covering the circuit layer; patterning the photoresist layer to form a plurality of openings exposing the circuit layer; patterning the circuit layer, removing the circuit layer exposed by the opening by using the photoresist layer as a mask to form a plurality of circuits, wherein a first groove is formed between two adjacent circuits, and the bonding layer is exposed by the first groove; removing the photoresist layer; patterning the bonding layer, removing the bonding layer exposed by the first grooves and not embedded in the activation layer by using the circuit as a mask, so that the bonding layer below the circuit forms a plurality of first bearing parts, a second groove is arranged between every two adjacent first bearing parts, and the mixed layer is exposed by the second groove; and patterning the bottom plate, removing the mixed layer exposed by the second grooves by taking the first bearing part as a mask, so that the mixed layer positioned below the first bearing part forms a plurality of second bearing parts, wherein a third groove is arranged between every two adjacent second bearing parts, and the unactivated layer is exposed by the third groove.

The object of the present invention and the technical problems can be further achieved by the following technical measures.

Preferably, in the aforementioned process for patterning a circuit substrate, each of the first supporting portions has a first outer annular surface, each of the second supporting portions has a second outer annular surface, a lateral etching groove is formed between the second outer annular surface and a longitudinally extending line along the first outer annular surface, the lateral etching groove is located below the first supporting portion and is communicated with the third groove, and a first horizontal distance is formed between the second outer annular surface and the longitudinally extending line.

Preferably, in the above-mentioned circuit substrate patterning manufacturing process, after patterning the bottom plate, the circuit is etched, so that the first groove is enlarged to expose the surface of the first carrying portion.

Preferably, in the aforementioned process of manufacturing the circuit substrate by patterning, after the circuit is etched, a connection layer is formed on each circuit, each etched circuit has a third outer ring surface and a top surface, the connection layer covers the third outer ring surface and the top surface, and the connection layer contacts the surface of the first carrying portion, so that each circuit is covered in a space formed by the first carrying portion and the connection layer.

Preferably, in the aforementioned circuit substrate patterning process, the connection layer covering the third outer annular surface has a fourth outer annular surface, and a second horizontal distance is provided between the fourth outer annular surface and the longitudinally extending line.

Preferably, in the process of patterning the circuit substrate, the second horizontal distance is greater than the first horizontal distance.

Preferably, in the aforementioned process of patterning the circuit substrate, the difference between the second horizontal distance and the first horizontal distance is between 28 nm and 158 nm.

Preferably, in the aforementioned process of patterning the circuit substrate, the activation treatment is to activate the region to be activated of the bottom plate with plasma, so that the region to be activated forms the activation layer.

Preferably, in the aforementioned process of patterning the circuit substrate, the bonding layer is formed by sputtering a plurality of metal particles onto the active layer, and a portion of the metal particles is embedded into the active layer to form the mixed layer.

The purpose of the invention and the technical problem to be solved can also be realized by adopting the following technical scheme. The circuit substrate comprises a patterned bottom plate, a plurality of first bearing parts and a plurality of circuits, wherein the first bearing parts are positioned between the patterned bottom plate and the circuits, and the circuits are arranged on the first bearing parts.

The object of the present invention and the technical problems solved thereby can be further achieved by the following technical measures.

Preferably, in the aforementioned circuit substrate, each of the first supporting portions has a first outer annular surface, each of the second supporting portions has a second outer annular surface, a lateral etching groove is formed between the second outer annular surface and a longitudinally extending line along the first outer annular surface, the lateral etching groove is located below the first supporting portion and is communicated with the groove, and a first horizontal distance is formed between the second outer annular surface and the longitudinally extending line.

Preferably, the circuit substrate further includes a connection layer, the connection layer is formed on each of the circuits, each of the circuits has a third outer annular surface and a top surface, the connection layer covers the third outer annular surface and the top surface, and the connection layer contacts the surface of the first carrying portion, so that each of the circuits is covered in a space formed by the first carrying portion and the connection layer.

Preferably, in the aforementioned circuit substrate, the connection layer covering the third outer annular surface has a fourth outer annular surface, and a second horizontal distance is provided between the fourth outer annular surface and the longitudinally extending line.

Preferably, in the aforementioned circuit substrate, the second horizontal distance is greater than the first horizontal distance.

Preferably, the difference between the second horizontal distance and the first horizontal distance is between 28 nm and 158 nm.

By the technical scheme, the circuit substrate patterning manufacturing process and the circuit substrate have the following advantages and beneficial effects:

the mixed layer exposed by the second groove is removed, so that the mixed layer which is easy to adsorb impurities is prevented from influencing the adhesive force of an adhesive (such as filling glue such as non-conductive glue, conductive glue and the like), and therefore, when the circuit substrate and the glass substrate are packaged, the problem that the yield of a packaging structure is reduced due to poor bonding strength between the adhesive and the circuit substrate can be avoided.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention is implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.

Drawings

FIG. 1 is a flow chart of a process flow for patterning a circuit substrate according to an embodiment of the present invention.

Fig. 2 to 13 are schematic views illustrating a process flow of patterning a circuit substrate according to an embodiment of the present invention.

FIG. 14 is a schematic view of bonding a circuit substrate and a glass substrate according to an embodiment of the present invention.

[ description of main element symbols ]

10: line substrate patterning production process 11: providing a circuit substrate to be patterned

12: forming a photoresist layer 13: patterning photoresist layer

14: patterning the wiring layer 15: removing the photoresist layer

16: patterning the bonding layer 17: patterned backplane

18: etching the wiring 19: forming a connecting layer

100: the circuit substrate 100' to be patterned: circuit substrate

110: a bottom plate 110': patterned backplane

110 a: region to be activated 111: active layer

112: non-activated layer 113: mixing layer

114: second bearing portion 114 a: second outer ring surface

115: third groove 120: bonding layer

121: first bearing portion 121 a: first outer annular surface

121 b: surface 122: second groove

130: a circuit: 131 line

131 a: third outer annular surface 131 b: the top surface

132: first groove 140: connecting layer

141: fourth outer annulus 200: the photoresist layer

210: opening 300: adhesive agent

400: glass substrate D1: first horizontal distance

D2: second horizontal distance L: longitudinally extending line

S: side etching groove

Detailed Description

Referring to fig. 1, an embodiment of a circuit substrate patterning process 10 includes providing a circuit substrate 11 to be patterned, forming a photoresist layer 12, a patterned photoresist layer 13, a patterned circuit layer 14, removing the photoresist layer 15, a patterned bonding layer 16, and a patterned base plate 17.

Referring to fig. 1 and 5, in the step 11 of providing a circuit substrate to be patterned, a circuit substrate 100 to be patterned is provided, the circuit substrate 100 to be patterned has a bottom plate 110, a bonding layer 120 and a circuit layer 130, the bonding layer 120 is located between the bottom plate 110 and the circuit layer 130, in this embodiment, the bottom plate 110 is made of Polyimide (PI), the bonding layer 120 is made of nichrome, and the circuit layer 130 is made of copper.

Referring to fig. 2 to 4, which illustrate a process of fabricating the circuit substrate 100 to be patterned, first, referring to fig. 3, the base plate 110 is activated to form an activated layer 111 and an unactivated layer 112, the activated layer 111 can improve the adhesion of the bonding layer 120, in the present embodiment, the activating treatment is to activate the region 110a to be activated of the base plate 110 by plasma so that the region 110a to be activated forms the activated layer 111, and then, referring to fig. 4, the bonding layer 120 is formed on the base plate 110, the bonding layer 120 covers the activated layer 111, and part of the bonding layer 120 is embedded in the activated layer 111, so that the activated layer 111 embedded with the bonding layer 120 forms a mixed layer 113, in the present embodiment, the bonding layer 120 is formed by sputtering a plurality of metal particles on the activated layer 110, and part of the metal particles are embedded in the activated layer 111, to form the mixed layer 113, referring to fig. 5, the circuit layer 130 is formed on the bonding layer 120 to form the circuit substrate 100 to be patterned.

Referring to fig. 1 and 6, in the "forming a photoresist layer" step 12, a photoresist layer 200 is formed on the circuit layer 130, and the photoresist layer 200 covers the circuit layer 130.

Referring to fig. 1 and 7, in the step 13 of "patterning the photoresist layer", a plurality of openings 210 are formed in the photoresist layer 200 by the manufacturing processes of exposure and development, and the circuit layer 130 is exposed from the openings 210.

Referring to fig. 1 and 8, in the step 14 of "patterning the circuit layer", the photoresist layer 200 is used as a mask to remove the circuit layer 130 exposed by the opening 210, so that the circuit layer 130 forms a plurality of circuits 131, wherein a first groove 132 is formed between two adjacent circuits 131, the first groove 132 exposes the bonding layer 120, in this embodiment, the circuit layer 130 is etched by a first etching solution to remove the circuit layer 130 exposed by the opening 210, wherein the main component of the first etching solution includes hydrogen chloride and copper chloride.

Referring to fig. 1 and 9, in the photoresist layer removing step 15, the photoresist layer 200 is removed to expose the circuit 131, in the present embodiment, the photoresist layer 200 is removed by a photoresist stripper containing potassium hydroxide.

Referring to fig. 1 and 10, in a "patterning the bonding layer" step 16, the bonding layer 120 exposed by the first grooves 132 and not embedded in the active layer 111 is removed using the wires 131 as a mask, so that the bonding layer 120 under the wires 131 forms a plurality of first carrying portions 121, a second groove 122 is disposed between two adjacent first carrying portions 121, and the mixed layer 113 is exposed from the second groove 122, in this embodiment, the bonding layer 120 is etched by a second etching solution to remove the bonding layer 120 exposed by the first grooves 132 and not embedded in the active layer 111, wherein the second etching solution mainly comprises hydrogen chloride, a copper compound, a nitric acid inducer, a fatty acid inducer, and an alkylene glycol inducer.

Referring to fig. 1 and 11, in the step 17 of "patterning the bottom plate", the first carrying portion 121 is used as a mask to remove the mixed layer 113 exposed by the second grooves 122, so that the mixed layer 113 under the first carrying portion 121 forms a plurality of second carrying portions 114, and the bottom plate 110 forms a patterned bottom plate 110', wherein a third groove 115 is formed between two adjacent second carrying portions 114, and the third groove 115 exposes the inactive layer 112 of the bottom plate 110.

Referring to fig. 11, the circuit substrate 100 to be patterned is processed in steps 11 to 17 to form a circuit substrate 100 ', the circuit substrate 100 ' includes the patterned bottom plate 110 ', the first carrying portion 121 and the circuit 131, the first carrying portion 121 is located between the patterned bottom plate 110 ' and the circuit 131, the circuit 131 is disposed on the first carrying portion 121, the patterned bottom plate 110 ' includes the second carrying portion 114 and the inactive layer 112, the second carrying portion 114 is located between the first carrying portion 121 and the inactive layer 112, and the second carrying portion 114 is formed on the inactive layer 112.

Referring to fig. 11, in the present embodiment, each of the first supporting portions 121 has a first outer annular surface 121a, each of the second supporting portions 114 has a second outer annular surface 114a, during the patterning of the bottom plate 110, a lateral etching S is formed between the second outer annular surface 114a and a longitudinal extension line L along the first outer annular surface 121a due to isotropic etching, the lateral etching S is located below the first supporting portion 121 and is communicated with the third groove 115, a first horizontal distance D1 is formed between the second outer annular surface 114a and the longitudinal extension line L, and the first horizontal distance D1 is a shortest distance between the second outer annular surface 114a and the longitudinal extension line L.

Referring to fig. 1 and 12, in the present embodiment, an "etching line" step 18 is further included after the bottom plate 110 is patterned (step 17), in the "etching line" step 18, the line 131 is etched to enlarge the first groove 132 to expose the surface 121b of the first carrying portion 121, wherein each etched line 131 has a third outer annular surface 131a and a top surface 131b, in the present embodiment, the line 131 is etched by a third etching solution, and the main component of the third etching solution includes potassium hydrogen sulfate, potassium peroxydisulfate and inorganic hydrochloric acid, or in other embodiments, the third etching solution may be selected from sulfuric acid or hydrogen peroxide.

Referring to fig. 1 and 13, in the present embodiment, after the step of etching the circuit 131 (step 18), a step 19 of "forming a connection layer" is further included, in the step 19 of "forming a connection layer", a connection layer 140 is formed on each circuit 131, the connection layer 140 covers the third outer ring surface 131a and the top surface 131b of each circuit 131, and the connection layer 140 contacts the surface 121b of the first carrying portion 121, so that each circuit 131 is covered in a space formed by the first carrying portion 121 and the connection layer 140 to prevent the circuit 131 from being oxidized, in the present embodiment, the connection layer 140 is made of a tin-copper alloy.

Referring to fig. 13, the connection layer 140 covering the third outer ring surface 131a has a fourth outer ring surface 141, and a second horizontal distance D2 is provided between the fourth outer ring surface 141 and the longitudinally extending line L, wherein the second horizontal distance D2 is a shortest distance between the fourth outer ring surface 141 and the longitudinally extending line L, in the embodiment, the second horizontal distance D2 is greater than the first horizontal distance D1, so as to prevent moisture accumulated in the lateral etching groove S from penetrating into the circuit layer 130 through the bonding layer 120 to generate a short circuit phenomenon, and preferably, a difference between the second horizontal distance D2 and the first horizontal distance D1 is 28-158 nm.

Referring to fig. 14, the circuit substrate 100' of the present invention is packaged with a glass substrate 400 by an adhesive 300 (e.g., a filling adhesive such as a non-conductive adhesive or a conductive adhesive), in the present embodiment, the adhesive 300 is Anisotropic Conductive Film (ACF), so that the adhesive 300 can bond the circuit substrate 100' and the glass substrate 400, and electrically connects the circuit 131 of the circuit substrate 100' and the electrode (not shown) of the glass substrate 400, since the adhesion of the adhesive 300 affects the reliability of the package structure, the present invention removes the exposed mixed layer 113 by patterning the bottom plate 110, so as to prevent the mixed layer 113 from adsorbing impurities to affect the bonding strength between the adhesive 300 and the circuit substrate 100', and in addition, the undercut S generated by isotropic etching is used for accommodating the adhesive 300, thereby further improving the adhesion of the adhesive 300.

Although the present invention has been described with reference to the above embodiments, it should be understood that the present invention is not limited to the above embodiments, but rather, may be embodied in many different forms and modifications without departing from the spirit and scope of the present invention.

Claims

1. A circuit substrate patterning manufacturing process is characterized in that: providing a circuit substrate to be patterned, wherein the circuit substrate to be patterned is provided with a bottom plate, a bonding layer and a circuit layer, the bonding layer is positioned between the bottom plate and the circuit layer, the bottom plate is provided with an activated layer and an unactivated layer, the bottom plate is subjected to activation treatment to form the activated layer, and part of the bonding layer is embedded into the activated layer, so that the activated layer embedded with the bonding layer is formed into a mixed layer;

forming a photoresist layer covering the circuit layer;

patterning the photoresist layer to form a plurality of openings exposing the circuit layer;

patterning the circuit layer, removing the circuit layer exposed by the opening by using the photoresist layer as a mask to form a plurality of circuits, wherein a first groove is formed between two adjacent circuits, and the bonding layer is exposed by the first groove;

removing the photoresist layer;

patterning the bonding layer, removing the bonding layer exposed by the first grooves and not embedded in the activation layer by using the circuit as a mask, so that the bonding layer below the circuit forms a plurality of first bearing parts, a second groove is arranged between every two adjacent first bearing parts, and the mixed layer is exposed by the second groove;

and patterning the bottom plate, removing the mixed layer exposed by the second grooves by taking the first bearing part as a mask, so that the mixed layer positioned below the first bearing part forms a plurality of second bearing parts, wherein a third groove is arranged between every two adjacent second bearing parts, and the unactivated layer is exposed by the third groove.

2. The process of claim 1, wherein each of the first supporting portions has a first outer annular surface, each of the second supporting portions has a second outer annular surface, a lateral etching groove is formed between the second outer annular surface and a longitudinal extending line along the first outer annular surface, the lateral etching groove is located below the first supporting portion and is communicated with the third groove, and a first horizontal distance is formed between the second outer annular surface and the longitudinal extending line.

3. The process of claim 2, wherein after patterning the base plate, the circuit is etched to enlarge the first trench to expose the surface of the first carrier portion.

4. The process of claim 3, wherein after etching the wires, a connecting layer is formed on each wire, each etched wire has a third outer ring surface and a top surface, the connecting layer covers the third outer ring surface and the top surface, and the connecting layer contacts the surface of the first carrier, so that each wire is covered in a space formed by the first carrier and the connecting layer.

5. The process of claim 4, wherein the bonding layer covering the third outer annular surface has a fourth outer annular surface spaced apart from the longitudinally extending line by a second horizontal distance.

6. The process of claim 5, wherein the second horizontal distance is greater than the first horizontal distance.

7. The process of claim 6, wherein the difference between the second horizontal distance and the first horizontal distance is between 28 nm and 158 nm.

8. The process of claim 1, wherein said activation treatment is plasma activation of said to-be-activated region of said substrate, such that said to-be-activated region forms said active layer.

9. The process of claim 1 or 8, wherein the bonding layer is formed by sputtering a plurality of metal particles onto the active layer, and a portion of the metal particles are embedded into the active layer to form the mixed layer.