TW201735753A - Pattering process of circuit substrate and circuit substrate - Google Patents

Abstract

A pattering process of circuit substrate includes providing a waiting-for-patterning circuit substrate, wherein the waiting-for-patterning circuit substrate comprises a basal plate, a circuit layer and a connecting layer located between the basal plate and the circuit layer, the basal plate has a activated layer and the partial connecting layer embedded in the activated layer to lead the activated layer having the connecting layer transform to a mix layer, forming a photoresist layer on the circuit layer, and patterning the photoresist layer, the circuit layer, the connecting layer and the basal plate sequentially to form a patterned circuit substrate.

Description

Circuit substrate patterning process and circuit substrate

The invention relates to a circuit substrate patterning process and a circuit substrate, in particular to a circuit substrate patterning process and a circuit substrate capable of improving the adhesion of an adhesive (for example, a non-conductive adhesive, a conductive adhesive, etc.).

In the conventional circuit substrate process, a surface of a substrate is first activated to facilitate formation of a circuit in a subsequent process, but the surface treated by the activation process adsorbs impurities, such as a non-conductive paste or a conductive paste. The filling glue is not easy to adhere to the surface of the bottom plate, and the bonding strength between the circuit substrate and a glass substrate is lowered. Therefore, how to improve the adhesion of the adhesive to the surface of the bottom plate is a problem to be solved in the art.

The main object of the present invention is to provide a circuit substrate patterning process and a circuit substrate to prevent the substrate from adsorbing impurities and affect the bonding strength between the adhesive (for example, non-conductive adhesive, conductive adhesive, etc.) and the bottom plate, resulting in a package structure. Poor reliability.

A circuit substrate patterning process of the present invention includes: providing a circuit substrate to be patterned, the circuit board to be patterned having a bottom plate, a bonding layer and a circuit layer, wherein the bonding layer is located on the bottom plate and the circuit layer The bottom plate has an active layer and an unactivated layer, the bottom plate is formed by an activation process, and a portion of the bonding layer is embedded in the active layer such that the active layer embedded with the bonding layer is formed as a mixed layer; forming a photoresist layer, the photoresist layer covering the circuit layer; patterning the photoresist layer to form a plurality of openings, the openings revealing the circuit layer; patterning the circuit layer to the light The resist layer is a mask, and the circuit layer exposed by the openings is removed, so that the circuit layer forms a plurality of lines, and a first groove is formed between two adjacent lines, and the first groove exposes the bonding layer Removing the photoresist layer; patterning the bonding layer, using the lines as a mask, removing the bonding layer exposed by the first trenches and not embedded in the active layer, so that the underlying lines The bonding layer forms a plurality of first bearings a second groove between the two adjacent first bearing portions, the second groove revealing the mixed layer; and patterning the bottom plate, the first bearing portion is a mask, and the removing is The mixed layer exposed by the second slots is such that the mixed layer under the first carrying portions forms a plurality of second carrying portions, and the adjacent two of the second carrying portions have a third slot therebetween. The third tank reveals the unactivated layer.

The present invention removes the mixed layer exposed by the second grooves to prevent the mixed layer which easily adsorbs impurities from affecting the adhesion of the adhesive (for example, a non-conductive adhesive, a conductive adhesive, etc.), and thus the circuit substrate When packaging with a glass substrate, it is possible to avoid a decrease in package construction yield due to poor bonding strength between the adhesive and the wiring substrate.

Referring to FIG. 1 , a circuit substrate patterning process 10 includes “providing a circuit substrate to be patterned” 11 , “forming a photoresist layer” 12 , and “patterning a photoresist layer” 13 . "patterned wiring layer" 14, "removal photoresist layer" 15, "patterned bonding layer" 16 and "patterned substrate" 17.

Referring to FIGS. 1 and 5, in the step 11 of providing a circuit board to be patterned, a circuit board 100 to be patterned is provided. The circuit board 100 to be patterned has a bottom plate 110, a bonding layer 120 and a circuit layer. 130, the bonding layer 120 is located between the bottom plate 110 and the circuit layer 130. In this embodiment, the material of the bottom plate 110 is Polyimide (PI), and the bonding layer 120 is made of nickel-chromium alloy. The material of the circuit layer 130 is copper.

Please refer to FIGS. 2 to 4 , which are manufacturing processes of the circuit board 100 to be patterned. First, referring to FIG. 3 , the substrate 110 forms an active layer 111 and an unactivated layer 112 via an activation process. The activation layer 111 can improve the adhesion of the bonding layer 120. Referring to FIG. 2, in the embodiment, the activation process activates one of the substrate 110 to be activated by a plasma to activate the region 110a. Forming the active layer 111. Next, referring to FIG. 4, the bonding layer 120 is formed on the bottom plate 110. The bonding layer 120 covers the active layer 111, and a portion of the bonding layer 120 is embedded in the active layer 111. The active layer 111 embedded with the bonding layer 120 forms a mixed layer 113. In the embodiment, the bonding layer 120 is formed by sputtering a plurality of metal particles on the active layer 110, and some of the layers are formed. Metal particles are embedded in the active layer 111 to form the mixed layer 113. Finally, referring to FIG. 5, the wiring layer 130 is formed on the bonding layer 120 to form the circuit substrate 100 to be patterned.

Referring to FIGS. 1 and 6, in step 12 of forming a photoresist layer, a photoresist layer 200 is formed on the wiring layer 130, and the photoresist layer 200 covers the wiring layer 130.

Referring to FIGS. 1 and 7, in the "patterned photoresist layer" step 13, the photoresist layer 200 is formed into a plurality of openings 210 by exposure and development processes, and the openings 210 expose the circuit layer 130.

Referring to FIGS. 1 and 8, in the "patterned circuit layer" step 14, the photoresist layer 200 is used as a mask to remove the circuit layer 130 exposed by the openings 210, so that the circuit layer 130 forms a plurality a line 131, wherein a first groove 132 is formed between the two adjacent lines 131, and the first groove 132 exposes the bonding layer 120. In this embodiment, the line is etched with a first etching solution. The layer 130 is configured to remove the circuit layer 130 exposed by the openings 210, wherein the main component of the first etching solution comprises hydrogen chloride and copper chloride.

Referring to Figures 1 and 9, in the "Removing the photoresist layer" step 15, the photoresist layer 200 is removed to expose the lines 131. In this embodiment, the glue is removed with potassium hydroxide. The liquid removes the photoresist layer 200.

Referring to FIGS. 1 and 10, in the "patterned bonding layer" step 16, the bonding layer 120 exposed by the first trenches 132 and not embedded in the active layer 111 is removed by using the lines 131 as a mask. The bonding layer 120 under the lines 131 forms a plurality of first carrying portions 121, and a second slot 122 is formed between the two adjacent first carrying portions 121. The second slot 122 reveals the mixing. In the embodiment, the bonding layer 120 is etched by a second etching solution to remove the bonding layer 120 exposed by the first trenches 132 and not embedded in the active layer 111. The main components of the second etching solution include hydrogen chloride, a copper compound, a nitric acid inducer, a fatty acid inducer, and an alkylene glycol inducer.

Referring to FIGS. 1 and 11, in the "patterned bottom plate" step 17, the first carrying portion 121 is used as a mask to remove the mixed layer 113 exposed by the second grooves 122, so as to be located therein. The mixed layer 113 under the first carrying portion 121 forms a plurality of second carrying portions 114, and the bottom plate 110 forms a patterned bottom plate 110', wherein the adjacent two of the second carrying portions 114 have a first a third trench 115 exposing the unactivated layer 112 of the bottom plate 110. In this embodiment, the bottom plate 110 is etched with an isotropic etching solution to remove the exposed portions of the second trench 122. The mixed layer 113, wherein the isotropic etching liquid is selected from potassium permanganate or sodium hydroxide.

Referring to FIG. 11 , the circuit board 100 to be patterned forms a circuit substrate 100 ′ through the processing of steps 11 to 17 , and the circuit substrate 100 ′ includes the patterned substrate 110 ′, the first carrier portions 121 , and the The first carrying portion 121 is located between the patterned bottom plate 110 ′ and the lines 131 , and the lines 131 are disposed on the first carrying portions 121 , and the patterned bottom plate 110 ′ The second carrying portion 114 and the unactivated layer 112 are respectively located between the first carrying portion 121 and the unactivated layer 112, and the second carrying portions 114 are formed at the On the activation layer 112.

Referring to FIG. 11 , in the embodiment, each of the first bearing portions 121 has a first outer annular surface 121 a , and each of the second bearing portions 114 has a second outer annular surface 114 a for patterning the bottom plate 110 . During the process, the isotropic etching forms a side etching S between the second outer annular surface 114a and a longitudinally extending line L along the first outer annular surface 121a, and the lateral etching groove S is located at the first A first horizontal distance D1 is defined between the second outer annular surface 114a and the longitudinally extending line L, and the first horizontal distance D1 is the second outer annular surface 114a and The shortest distance of the longitudinal extension line L.

Referring to FIGS. 1 and 12, in the embodiment, after patterning the substrate 110 (step 17), an "etching line" step 18 is further included. In the "etching line" step 18, the lines 131 are etched. The first groove 132 is enlarged to expose a surface 121b of the first bearing portion 121. The etched line 131 has a third outer ring surface 131a and a top surface 131b. In this embodiment, The lines 131 are etched by a third etching solution, and the main component of the third etching solution comprises potassium hydrogen sulfate, potassium peroxydisulfate and inorganic hydrochloric acid, or in other embodiments, the third etching liquid may be selected from Sulfuric acid or hydrogen peroxide.

Referring to FIGS. 1 and 13, in the present embodiment, after etching the lines 131 (step 18), a "forming layer" step 19 is further included, and in the "forming the layer" step 19, a joint layer is formed. In the line 131, the connecting layer 140 covers the third outer ring surface 131a and the top surface 131b of the line 131, and the connecting layer 140 contacts the surface 121b of the first carrying portion 121 so that each The line 131 is covered in the space formed by the first carrying portion 121 and the connecting layer 140 to prevent oxidation of the lines 131. In the embodiment, the connecting layer 140 is made of tin-copper alloy.

Referring to FIG. 13, the connecting layer 140 covering the third outer annular surface 131a has a fourth outer annular surface 141 having a second horizontal distance D2 between the fourth outer annular surface 141 and the longitudinally extending line L. The second horizontal distance D2 is the shortest distance between the fourth outer annular surface 141 and the longitudinal extension line L. In this embodiment, the second horizontal distance D2 is greater than the first horizontal distance D1 to avoid accumulation. The water vapor in the side etching groove S penetrates into the circuit layer 130 via the bonding layer 120 to generate a short circuit phenomenon. Preferably, the difference between the second horizontal distance D2 and the first horizontal distance D1 is between 28 and 158 nm.

Referring to FIG. 14, the circuit substrate 100' of the present invention is packaged with a glass substrate 400 by an adhesive 300 (for example, a non-conductive adhesive or a conductive adhesive). In this embodiment, the adhesive is used. 300 is an anisotropic conductive adhesive (ACF), so the adhesive 300 can bond the circuit substrate 100' and the glass substrate 400, and electrically connect the lines 131 of the circuit substrate 100' and the electrodes of the glass substrate 400. (Unillustrated), since the adhesion of the adhesive 300 affects the reliability of the package structure, the present invention avoids the adsorption of the mixed layer 113 by patterning the bottom plate 110 to remove the exposed mixed layer 113. The bonding strength between the adhesive 300 and the circuit substrate 100' is affected. In addition, the side etching groove S generated by the isotropic etching of the present invention is used to accommodate the adhesive 300, which can further improve the bonding. The adhesion of the agent 300.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

10‧‧‧Line substrate patterning process
11‧‧‧Providing circuit board to be patterned
12‧‧‧Forming a photoresist layer
13‧‧‧ patterned photoresist layer
14‧‧‧ patterned circuit layer
15‧‧‧Removing the photoresist layer
16‧‧‧patterned bonding layer
17‧‧‧ patterned bottom plate
18‧‧‧ Etched lines
19‧‧‧ forming a tie layer
100‧‧‧ patterned circuit board
100'‧‧‧Line substrate
110‧‧‧floor
110'‧‧‧ patterned bottom plate
110a‧‧‧Activated area
111‧‧‧Active layer
112‧‧‧Unactivated layer
113‧‧‧ mixed layer
114‧‧‧Second load bearing department
114a‧‧‧Second outer annulus
115‧‧‧ third slot
120‧‧‧bonding layer
121‧‧‧First load bearing department
121a‧‧‧First outer annulus
121b‧‧‧ surface
122‧‧‧second trough
130‧‧‧Line layer
131‧‧‧ lines
131a‧‧‧ Third outer annulus
131b‧‧‧ top surface
132‧‧‧first slot
140‧‧‧Linking layer
141‧‧‧Fourth outer annulus
200‧‧‧ photoresist layer
210‧‧‧ openings
300‧‧‧Binder
400‧‧‧ glass substrate
D1‧‧‧first horizontal distance
D2‧‧‧Second horizontal distance
L‧‧‧ longitudinal extension line
S‧‧‧Surface

FIG. 1 is a flow chart showing a circuit board patterning process according to an embodiment of the invention. 2 to 13 are views showing a circuit board patterning process according to an embodiment of the present invention. Figure 14 is a schematic view showing the bonding of a circuit substrate and a glass substrate in accordance with an embodiment of the present invention.

100'‧‧‧ circuit substrate

110’‧‧‧ patterned bottom plate

112‧‧‧Unactivated layer

114‧‧‧Second load bearing department

114a‧‧‧Second outer annulus

115‧‧‧ third slot

121‧‧‧First load bearing department

121a‧‧‧First outer annulus

131‧‧‧ lines

D1‧‧‧first horizontal distance

L‧‧‧ longitudinal extension line

S‧‧‧Surface

Claims (15)

A circuit substrate patterning process includes: providing a circuit substrate to be patterned, the circuit substrate to be patterned having a bottom plate, a bonding layer and a circuit layer, the bonding layer being located between the bottom plate and the circuit layer, The bottom plate has an activation layer and an unactivated layer, the bottom plate is formed by an activation treatment, and a part of the bonding layer is embedded in the activation layer, so that the activation layer embedded with the bonding layer is formed as a mixed layer. Forming a photoresist layer, the photoresist layer covering the circuit layer; patterning the photoresist layer to form a plurality of openings, the openings revealing the circuit layer; patterning the circuit layer, wherein the photoresist layer is Masking, removing the circuit layer exposed by the openings, forming a plurality of lines in the circuit layer, and having a first groove between the two adjacent lines, the first groove revealing the bonding layer; The photoresist layer is patterned, and the lines are masked to remove the bonding layer exposed by the first grooves and not embedded in the active layer, so that the bonding layer under the lines is formed Multiple first load-bearing parts Between the two adjacent first bearing portions, a second groove is formed, the second groove reveals the mixed layer; and the bottom plate is patterned, and the first bearing portions are masked, and the The mixed layer exposed by the two slots forms a plurality of second carrying portions of the mixed layer located under the first carrying portions, and a third slot between the adjacent two of the second carrying portions, the third The groove reveals the unactivated layer. The circuit substrate patterning process of claim 1, wherein each of the first bearing portions has a first outer ring surface, and each of the second bearing portions has a second outer ring surface, the second outer ring Forming a side etching groove between the surface and a longitudinally extending line along the first outer annular surface, the side etching groove is located below the first bearing portion and communicates with the third groove, the second outer annular surface and the longitudinal direction There is a first horizontal distance between the extension lines. The circuit substrate patterning process of claim 2, wherein after patterning the substrate, the lines are etched such that the first groove is enlarged to expose a surface of the first carrier. The circuit substrate patterning process of claim 3, wherein after etching the lines, a bonding layer is formed on each of the lines, and each of the etched lines has a third outer ring surface and a top surface. The connecting layer covers the third outer ring surface and the top surface, and the connecting layer contacts the surface of the first bearing portion, so that each line is covered by the first bearing portion and the connecting layer In the space. The circuit substrate patterning process of claim 4, wherein the bonding layer covering the third outer annular surface has a fourth outer annular surface, and the fourth outer annular surface and the longitudinally extending line have A second horizontal distance. The circuit substrate patterning process of claim 5, wherein the second horizontal distance is greater than the first horizontal distance. The circuit substrate patterning process of claim 6, wherein the difference between the second horizontal distance and the first horizontal distance is between 28 and 158 nm. The circuit substrate patterning process of claim 1, wherein the activation treatment activates a region to be activated of the substrate by plasma, so that the activation region forms the activation layer. The circuit substrate patterning process of claim 1 or 8, wherein the bonding layer is formed by sputtering a plurality of metal particles on the active layer, and a portion of the metal particles are embedded in the active layer. To form the mixed layer. A circuit substrate includes a patterned backplane, a plurality of first carrying portions, and a plurality of lines, the first carrying portions are located between the patterned backplane and the lines, and the lines are disposed on the first carriers And a plurality of second carrying portions and an unactivated layer, the second carrying portions are located between the first carrying portions and the unactivated layer, and the second carrying portions are Formed on the unactivated layer, the second load-bearing portions are formed by a mixed layer of one of the patterned bottom plates, wherein the mixed layer is formed by one of the active layer of the bottom plate and a layer partially embedded in the active layer Formed, there is a groove between the two adjacent second bearing portions, the groove revealing the unactivated layer. The circuit substrate of claim 10, wherein each of the first bearing portions has a first outer annular surface, and each of the second bearing portions has a second outer annular surface, the second outer annular surface and the edge A side etching groove is formed between a longitudinally extending line of the first outer annular surface, the side etching groove is located below the first bearing portion and communicates with the groove, and the second outer annular surface and the longitudinally extending line have A first horizontal distance. The circuit board of claim 11, further comprising a connecting layer formed on each of the lines, each of the lines having a third outer ring surface and a top surface, the connecting layer covering the first a third outer ring surface and the top surface, and the connecting layer contacts a surface of the first bearing portion such that each of the wires is wrapped in a space formed by the first bearing portion and the connecting layer. The circuit substrate of claim 12, wherein the connecting layer covering the third outer annular surface has a fourth outer annular surface, and the fourth outer annular surface and the longitudinally extending line have a second Horizontal distance. The circuit substrate of claim 13, wherein the second horizontal distance is greater than the first horizontal distance. The circuit substrate of claim 14, wherein the difference between the second horizontal distance and the first horizontal distance is between 28 and 158 nm.