JP2007329325A - Method for manufacturing interconnection substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing an interconnection substrate with the surface of the conductive circuit part formed flat. <P>SOLUTION: The method for manufacturing the interconnection substrate comprises a plating resist step for providing the plating resist layer 4 having a pattern opposite of a circuit pattern on the surface of the conductive seed layer 3 provided to an insulating substrate 2, a plating step for providing a conductive circuit part 5 of the circuit pattern by plating on the surface of the conductive seed layer 3 without covered by the plating resist layer 4, a flattening etching step for falttening the surface of the conductive circuit part 5 by etching with the use of a hydrogen peroxide-based etchant or an amine-based etchant as an etchant before removing the plating resist layer 4, a plating resist layer removal step for removing the plating resist layer 4, and a seed layer removal step for removing a part of the conductive seed layer 3 without the conductive circuit part 5 provided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a wiring board in which a conductive circuit portion is formed on a surface of an insulating substrate by plating.

  One of the methods for manufacturing a wiring board is a semi-additive method. This semi-additive method is a method suitable for forming a fine pitch circuit (for example, a pitch of less than 30 μm), and an example of the conventional manufacturing method is disclosed in Patent Document 1. Hereinafter, this manufacturing method will be briefly described.

  First, using the insulating substrate 100 shown in FIG. 4A as a starting material, a thin conductive seed layer 101 is formed on one surface of the insulating substrate 100 as shown in FIG. 4B. . Next, as shown in FIG. 4C, a plating resist layer 102 having a pattern opposite to the circuit pattern is patterned on the conductive seed layer 101. Next, as shown in FIG. 4D, a conductive circuit portion 103 having a desired circuit pattern is grown on the surface of the conductive seed layer 101 not covered with the plating resist layer 102 by plating. Next, as shown in FIG. 4E, before removing the plating resist layer 102, the conductive circuit portion 103 is etched halfway in the thickness direction (half-etching step). In this half-etching process, chemical etching is performed using a known etching solution (for example, copper etching solution), and etching is performed until the height of the conductive circuit portion 103 before etching is 50% to 98% when the height is 100%. Do.

  Next, the plating resist layer 102 is removed to obtain a structure as shown in FIG. Next, as shown in FIG. 5A, the conductive seed layer 101 where the conductive circuit portion 103 is not provided is removed by etching. Finally, as shown in FIG. 5B, a protective layer 104 is formed so as to cover the conductive circuit portion 103 on the insulating substrate 100.

  According to this method for manufacturing a wiring board, after forming the conductive circuit portion 103 by plating, the conductive circuit portion 103 is etched halfway in the thickness direction while leaving the plating resist layer 102, thereby forming a circuit pattern shape. It is intended to make the thickness of the conductive circuit portion 103 in all places almost uniform regardless of the arrangement.

That is, the periphery of the etching solution in the conductive circuit portion 103 in the portion with a high wiring density is better than the periphery of the etching solution in the conductive circuit portion 103 with a low wiring density. By utilizing this, by setting the thickness of the conductive circuit portion 103 in the portion with high wiring density to be thick and setting the thickness of the conductive circuit portion 103 with low wiring density to be small, each conductive circuit portion in the portion with high wiring density is set. While 103 is etched more, a portion of the conductive circuit portion 103 having a lower wiring density is etched less. Therefore, the thickness of the conductive circuit portion 103 in the portion with high wiring density can be made substantially equal to the thickness of the conductive circuit portion 103 in the portion with low wiring density.
JP 2004-37771 A

  However, in the plating step for forming the conductive circuit portion 103, both ends in the width direction of the conductive circuit portion 103 close to the plating resist layer 102 and the central portion in the width direction of the conductive circuit portion 103 that is separated from the plating resist layer 102 Then, the circulation efficiency of the plating bath is different, and the circulation efficiency of both end portions is poor with respect to the central portion of the conductive circuit portion 103. Therefore, the conductive circuit portion 103 has a convex shape whose central portion is thicker than both end portions thereof. If the conductive circuit portion 103 has a convex shape, the terminals of the mounted components placed on the conductive circuit portion 103 are liable to be laterally displaced, and there is a problem that the mountability of the components is poor.

  In particular, in the ACF bonding using the anisotropic conductive adhesive film, the conductive particles of the anisotropic conductive film escape to the side region of the conductive circuit portion 103 during pressing and contact with the conductive circuit portion 103 to function effectively. The number of isotropic particles is reduced, and the connection reliability of the mounted parts is lowered.

  Therefore, an object of the present invention is to provide a method for manufacturing a wiring board having a flat conductive circuit portion surface.

  The present invention relates to a method for manufacturing a wiring board, comprising: a resist patterning process in which a plating resist layer having a pattern opposite to a circuit pattern is provided on an insulating substrate; and a plating treatment in a region not covered with the plating resist layer. The present invention includes a plating process for providing a conductive circuit part of a circuit pattern by a step and a flattening etching process for flattening the surface of the conductive circuit part by etching before removing the plating resist layer. In the planarization etching step, it is preferable to perform etching using a hydrogen peroxide-based or amine-based etching solution. The etching rate is preferably 0.1 to 1 μm / min.

  According to the present invention, in the plating step, a conductive circuit portion having a shape in which the cross-sectional shape in the width direction protrudes at the center is formed, but the surface of the conductive circuit portion is flattened by the next flattening etching step. A wiring board having a flat conductive circuit surface can be manufactured. For this reason, the wiring board manufactured according to the present invention increases the flatness of the surface of the conductive circuit portion, and therefore can improve the connection reliability.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  1 to 3 are cross-sectional views of each manufacturing process of a printed wiring board according to an embodiment of the present invention.

  As shown in FIG. 3B, the printed wiring board 1 includes an insulating base material 2, a conductive seed layer 3 having a predetermined circuit pattern formed on the one surface, and a surface of the conductive seed layer 3. The conductive circuit portion 5 having a predetermined circuit pattern is formed, and a protective layer 6 is provided on the insulating substrate 2 and covers the conductive circuit portion 5.

  Hereinafter, the manufacturing method of this printed wiring board 1 is demonstrated in order. The insulating base material 2 shown in FIG. The insulating base material 2 is formed from, for example, a polyimide resin, an acrylic resin, or the like.

  First, as shown in FIG. 1B, a thin conductive seed layer 3 is formed on one surface of the insulating substrate 2 (seed layer forming step).

  Next, as shown in FIG. 2A, a plating resist layer 4 having a pattern opposite to the desired circuit pattern is formed on the surface of the conductive seed layer 3 (plating resist process). The plating resist layer 4 is formed by applying a resist film on the surface of the conductive seed layer 3, exposing the resist film, and developing the resist film.

  Next, as shown in FIG. 2B, a conductive circuit portion 5 having a desired circuit pattern is formed by plating on the surface of the conductive seed layer 3 not covered with the plating resist layer 4 (plating step). The conductive circuit portion 5 is formed by performing electrolytic plating on a portion not covered with the plating resist layer 4 using the conductive seed layer 3 as an electrolytic layer.

  Next, as shown in FIG. 2C, before removing the plating resist layer 4, the surface of the conductive circuit portion 5 is etched by using a sulfuric acid hydrogen peroxide-based or amine-based etching solution as an etching solution. Planarization (planarization etching process). That is, when a hydrogen peroxide sulfate or amine-based etchant is used as the etchant, both ends of the conductive circuit portion 5 near the plating resist layer 4 are difficult to be etched, and the conductivity away from the plating resist layer 4 is particularly difficult. Since the central part of the circuit part 5 is easily etched, the convex conductive circuit part 5 can be flattened.

  Next, as shown in FIG. 2D, the plating resist layer 4 is removed (plating resist layer removing step).

  Next, as shown in FIG. 3A, the conductive seed layer 3 where the conductive circuit portion 5 is not provided is removed by etching (seed layer removal step).

  Finally, as shown in FIG. 3B, the protective layer 6 is formed on the insulating base material 2 so as to cover the conductive circuit portion 5.

  As described above, in the plating step, the convex conductive circuit portion 5 is formed as shown in FIG. 2B, but the surface of the conductive circuit portion 5 is flattened by the next flattening etching step. Therefore, the printed wiring board 1 in which the surface of the conductive circuit portion 5 is flat can be manufactured. Accordingly, since the terminals of the mounted component placed on the conductive circuit portion 5 are not easily displaced laterally, the mountability of the component is improved. Even in the ACF bonding, the conductive particles of the anisotropic conductive film do not escape to the side region of the conductive circuit portion during pressing, so the number of anisotropic particles that function effectively in contact with the conductive circuit portion 5 is large. Thus, the connection reliability of the mounted parts is improved.

(Example)
Next, specific examples of each process of the manufacturing method described above will be described.

  As the insulating substrate 2, polyimide (manufactured by Toray DuPont; trade name Kapton EN) was used.

In the seed layer forming process, the insulating base material 2 is set in a sputtering chamber, argon gas is used as a plasma gas, and vacuum is 7 × 10 ⁻³ Torr. Conductive seed layer 3 was formed by sputtering deposition of 2000 mm.

  In the plating resist process, a dry film resist (manufactured by Hitachi Chemical Co., Ltd.) is laminated on the surface of the conductive seed layer 3, and a circuit pattern is exposed and developed on the dry film resist to remove the dry film resist in the circuit formation region. Then, the plating resist layer 4 was formed.

  In the plating process, the following copper sulfate plating bath is used, electricity is applied to the conductive seed layer 3 on the insulating base material 2 immersed in the copper sulfate plating bath, and copper is applied to portions not covered with the plating resist layer 4. The conductive circuit part 5 was formed by depositing.

  The copper sulfate plating bath is 75 g / liter (l) of copper sulfate pentahydrate, 190 g / liter of sulfuric acid, 50 mg / liter of hydrochloric acid, 5 ml / liter of cover cream CLX-A (Meltex), cover cream CLX -C (Meltex) is 5 ml / liter.

  In the planarization etching step, an amine-based etching solution is used as the etching solution, and the surface of the conductive circuit portion 5 is etched under the conditions of 28 ° C. and 0.15 MPa.

  In the plating resist layer removing step, the plating resist layer 4 was peeled off using a 3% aqueous sodium hydroxide solution.

  In the seed layer removing step, the conductive seed layer 3 was removed by etching using an etching solution such as iron chloride solution or copper chloride solution.

  The printed wiring board 1 manufactured in this way had a height difference of 0.5 μm or less between the both end portions and the central portion of the conductive circuit portion 5. On the other hand, in the printed wiring board manufactured in the same manufacturing process other than the flattening etching process, the height difference between the both end portions and the central portion of the conductive circuit portion was 1.2 μm at the maximum. From the above, flattening of the conductive circuit portion 5 in the present invention was demonstrated.

(Another specific example of etching liquid in the flattening etching step and etching rate)
(1) Etching solution In the flattening etching step, a hydrogen peroxide sulfate or an amine may be used as the etching solution.

  If a sulfuric acid hydrogen peroxide-based or amine-based etching solution is used, the portion where the circuit is exposed is more easily etched than the portion where the dry film resist is in contact with the circuit, and the circuit shape can be flattened.

(2) Etching rate The etching rate was 0.1 to 1 µm / min. The reason why the etching rate is set to 0.1 to 1 μm / min is that it is difficult to work because it is necessary to control a small amount of etching unless the etching rate is within this range.

  In addition, although the case of the semi-additive construction method by electroplating was demonstrated in the said embodiment, this invention is applicable also to the full additive construction method etc. by electroless plating.

1 shows an embodiment of the present invention, in which (a) is a cross-sectional view of an insulating substrate, and (b) is a cross-sectional view of a printed wiring board in one manufacturing process. 1 shows an embodiment of the present invention, wherein (a) to (d) are cross-sectional views of each manufacturing process of a printed wiring board. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an embodiment of the present invention, in which (a) is a cross-sectional view of one printed wiring board manufacturing process, and (b) is a cross-sectional view of the manufactured printed wiring board. A prior art example is shown, (a) is sectional drawing of an insulating base material, (b)-(f) is sectional drawing of each manufacturing process of a printed wiring board. A conventional example is shown, (a) is a cross-sectional view of one manufacturing process of a printed wiring board, (b) is a cross-sectional view of the manufactured printed wiring board.

Explanation of symbols

1 Printed wiring board (wiring board)
2 Insulating substrate 3 Conductive seed layer 4 Plating resist layer 5 Conductive circuit section

Claims (3)

A resist patterning step of providing a plating resist layer having a pattern opposite to the circuit pattern on the insulating substrate;
A plating step of providing a conductive circuit portion of a circuit pattern by plating in a region not covered with the plating resist layer;
A planarization etching step of planarizing the surface of the conductive circuit portion by etching before removing the plating resist layer;
A method of manufacturing a wiring board, comprising: It is a manufacturing method of the wiring board according to claim 1,
In the flattening etching step, etching is performed using a hydrogen peroxide-based or amine-based etching solution. It is a manufacturing method of the wiring board according to claim 1,
Etching rate is 0.1-1 micrometer / min, The manufacturing method of the wiring board characterized by the above-mentioned.

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