JP2015012115A - Wiring board manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a wiring board which has a small risk in the occurrence of disconnection in a wiring conductor and excellent electrical connection reliability.SOLUTION: A wiring board manufacturing method comprises: exposing a semiconductor element connection pad 7 and a wiring conductor 5 near the semiconductor element connection pad 7 by a solder resist layer 6a in a lower layer and depositing a nickel-gold plating layer 9 on the exposed part; subsequently exposing the semiconductor connection pad 7 on the nickel-gold plating layer 9 and depositing a solder resist layer 7c in an upper layer which covers the nickel-gold plating layer 9 deposited on the wiring conductor 5 near the semiconductor element connection pad 7; forming an etching mask M2 for covering the semiconductor element connection pad in the last state and exposing plated conduction lines 10, 11 and removing the plated conduction lines 10, 11 exposed from the etching mask M2 by etching.

Description

  The present invention relates to a method for manufacturing a wiring board used for mounting a semiconductor element.

  Conventionally, as shown in FIGS. 12A and 12B, a wiring board 40 on which a semiconductor element S in which electrode terminals T are peripherally arranged on the outer periphery of a lower surface is mounted by flip chip connection has a large number of through holes 22. A plurality of core wiring conductors 23 made of copper are deposited from the upper surface to the lower surface of a core insulating layer 21 made of a resin-based insulating material, and the upper and lower surfaces thereof are for build-up made of a resin-based insulating material. A buildup wiring conductor 25 made of a copper plating layer is laminated, and a solder resist layer 26 is deposited on the upper and lower surfaces of the wiring conductor 25 so as to expose a part of the wiring conductor 25. . In FIG. 12B, the wiring conductor 25 on the upper surface side is indicated by a broken line.

  A mounting portion for mounting the semiconductor element S is provided at the center of the upper surface of the wiring board 40, and a large number of semiconductor element connection pads 27 for connecting to the electrodes T of the semiconductor element S are provided on the mounting portion. It is formed by a part of the wiring conductor 25. The semiconductor element S is mounted on the wiring board 40 by bringing the electrodes T of the semiconductor element S into contact with the semiconductor element connection pads 27 and connecting the two via solder.

  The lower surface of the wiring board 40 is an external connection surface for connection to an external electric circuit board, and a large number of external connection pads 28 for connection to the external electric circuit board are provided on the external connection surface. It is formed by a part of the wiring conductor 25. Then, the wiring board 40 is mounted on the external electric circuit board by connecting the external connection pads 28 and the external electric circuit board via solder.

  By the way, in such a wiring board 40, in order to prevent the oxidation of the semiconductor element connection pad 27 and to improve the connection with the electrode T of the semiconductor element S, on the exposed surface of the semiconductor element connection pad 27, In some cases, a nickel-gold plating layer 29 in which a nickel plating layer and a gold plating layer are sequentially applied by electrolytic plating is applied.

  Here, a method of depositing the nickel-gold plating layer 29 on the surface of the semiconductor element connection pad 27 by the electrolytic plating method in the conventional wiring board 40 will be described with reference to FIGS.

  First, as shown in FIGS. 13 (a) and 13 (b), a wiring board panel 40P in which a large number of product areas X to be the wiring boards 40 are integrally formed around the product area X through a margin area Y is formed. prepare. In each product region X, a semiconductor element connection pad 27 is formed on the upper surface. 13 to 19, for the sake of simplicity, one product area X and a surrounding margin area Y are partially shown.

  The wiring board panel 40P is made of copper that extends from some of the wiring conductors 25 in the product region X to the disposal margin region Y and is electrically connected in common in the disposal margin region Y on the insulating layer 24 on the upper surface side. The plating conduction line 30 is provided. The plating conductive line 30 in the disposal margin region Y is exposed from the solder resist layer 26. In addition, some of the different wiring conductors 25 in the product region X are connected by the plating conduction line 31, and a part of the plating conduction line 31 is exposed from the solder resist layer 26.

  Next, as shown in FIGS. 14A and 14B, a plating mask M1 is formed on the upper and lower surfaces of the wiring board panel 40P. The plating mask M <b> 1 on the upper surface side exposes the semiconductor element connection pads 27 and covers the plating conductive lines 30 and 31. The plating mask M1 on the lower surface side covers the external connection pads 28.

  Next, as shown in FIGS. 15A and 15B, a nickel plating layer and a gold plating layer are sequentially deposited on the surface of the semiconductor element connection pad 27 exposed from the mask M1 by an electrolytic plating method. A plating layer 29 is formed. In this case, the electrolytic plating is performed by supplying electric charges for electrolytic plating to the respective semiconductor element connection pads 27 through the plating conductive lines 30 and 31. At this time, the nickel-gold plating layer 29 is not deposited on the external connection pads 28 and the plating conductive lines 30 and 31 covered with the plating mask M1.

  Next, as shown in FIGS. 16A and 16B, the plating mask M1 is removed. As a result, a wiring board panel 40P in which the nickel-gold plating layer 29 is deposited only on the semiconductor element connection pads 27 is obtained.

  Next, as shown in FIGS. 17A and 17B, an etching mask M2 is formed on the upper and lower surfaces of the wiring board panel 40P. The etching mask M2 on the upper surface side exposes the plating conductive lines 30 and 31, and covers the semiconductor element connection pads 27. The etching mask M2 on the lower surface side covers the external connection pads 28.

  Next, as shown in FIGS. 18A and 18B, the plating conductive lines 30 and 31 exposed from the etching mask M2 are removed by etching. Thereby, predetermined ones of the semiconductor element connection pads 27 are electrically independent.

  Finally, as shown in FIGS. 19A and 19B, the etching mask M2 is removed, and then the wiring board panel 40P is cut along the boundaries of the respective product regions X, as shown in FIG. , (B), the wiring substrate 40 is obtained. For the plating mask M1 and the etching mask M2, a dry film resist having photosensitivity is pressure-bonded to the upper and lower surfaces of the wiring board panel 40P, and it is exposed and developed into a predetermined pattern using a photolithography technique. Formed by.

  However, according to such a conventional method of manufacturing the wiring substrate 40, when the plating conductive lines 30 and 31 exposed from the etching mask M2 are removed by etching, the etching mask M2 covering the semiconductor element connection pads 27 is broken. In rare cases, peeling may occur. When such tearing or peeling occurs, as shown in FIG. 20, the etching solution E leaks onto the semiconductor element connection pad 27, which is shown by the semiconductor element connection pad 27 and the solder resist layer 26 indicated by arrows in the drawing. In some cases, the wiring conductor 25 at the boundary between and is locally etched. Since the etching portion of the wiring conductor 25 at the boundary portion between the semiconductor element connection pad 27 and the solder resist layer 26 is covered with the nickel-gold plating layer 29 and the solder resist layer 26, the appearance is as follows. I can't tell. Further, unless the boundary between the semiconductor element connection pad 27 and the solder resist layer 26 is completely disconnected by etching, it is difficult to find even if an electrical continuity check is performed. If such an etched portion is generated in the wiring conductor 25, when a large current flows through the portion or a thermal stress is repeatedly applied, there is a high risk that the portion is disconnected. Therefore, the electrical connection reliability of the wiring board 40 is greatly impaired.

JP 2010-10346 A

  The problem to be solved by the present invention is that there is no local etching on the wiring conductor at the boundary between the semiconductor element connection pad and the solder resist layer, thereby reducing the risk of occurrence of disconnection in the wiring conductor. Another object of the present invention is to provide a method for manufacturing a wiring board having excellent connection reliability.

  In the method for manufacturing a wiring board according to the present invention, a plurality of wiring conductors made of copper having semiconductor element connection pads and a plating conduction wire made of copper for electrically connecting the plurality of wiring conductors are formed on the surface of the insulating layer. And forming a lower layer solder resist layer that exposes the semiconductor element connection pads and the plating conductive lines on the surfaces of the insulating layer and the conductor layer and covers the wiring conductors to the vicinity of the semiconductor element connection pads. Exposing the semiconductor element connection pad and the wiring conductor in the vicinity thereof on the lower solder resist layer and forming a plating mask for covering the plating conductive line, and exposing from the plating mask A step of depositing an electrolytic plating layer made of a metal different from copper on the exposed portion of the wiring conductor; Removing the plating mask from the strike layer; exposing the semiconductor element connection pad and the plating conductive line on the lower solder resist layer and the surrounding insulating layer and the wiring conductor; and the semiconductor element connection pad A step of depositing an upper solder resist layer covering the electroplating genus deposited on the wiring conductor in the vicinity; and the wiring conductor exposed from the upper solder resist layer on the upper solder resist layer Forming an etching mask that covers the plating conduction line and exposing the plating conduction line, etching and removing the plating conduction line exposed from the etching mask, and removing the etching mask from the upper solder resist layer And performing the above.

  According to the method for manufacturing a wiring board of the present invention, when the plating conductive line exposed from the etching mask is removed by etching, the boundary between the semiconductor element connection pad and the upper solder resist layer due to tearing or peeling of the etching mask. Even if the etching solution penetrates into the area, the boundary between the semiconductor element connection pad and the upper solder resist layer in the wiring conductor and the vicinity thereof are covered and protected by the electrolytic plating layer. Is not etched locally. Therefore, it is possible to provide a method for manufacturing a wiring board that has a low risk of disconnection in the wiring conductor and is excellent in electrical connection reliability.

FIG. 1 is a schematic cross-sectional view and a top view showing an example of a wiring board manufactured by the method for manufacturing a wiring board according to the present invention. FIG. 2 is a schematic cross-sectional view and a top view for explaining an embodiment of the method for manufacturing a wiring board of the present invention. FIG. 3 is a schematic cross-sectional view and a top view for explaining an embodiment of the method for manufacturing a wiring board of the present invention. FIG. 4 is a schematic cross-sectional view and a top view for explaining an embodiment of the method for manufacturing a wiring board of the present invention. FIG. 5 is a schematic cross-sectional view and a top view for explaining an embodiment of the method for manufacturing a wiring board of the present invention. FIG. 6 is a schematic cross-sectional view and a top view for explaining an embodiment of the method for manufacturing a wiring board of the present invention. FIG. 7 is a schematic cross-sectional view and a top view for explaining an embodiment of the method for manufacturing a wiring board of the present invention. FIG. 8 is a schematic cross-sectional view and a top view for explaining an embodiment of the method for manufacturing a wiring board of the present invention. FIG. 9 is an enlarged schematic cross-sectional view of a main part for explaining an embodiment of the method for manufacturing a wiring board according to the present invention. FIG. 10 is a schematic cross-sectional view and a top view for explaining an embodiment of the method for manufacturing a wiring board according to the present invention. FIG. 11 is a schematic cross-sectional view and a top view showing an example of a wiring board manufactured by a conventional wiring board manufacturing method. FIG. 12 is a schematic cross-sectional view and a top view for explaining a conventional method of manufacturing a wiring board. FIG. 13 is a schematic cross-sectional view and a top view for explaining a conventional method of manufacturing a wiring board. FIG. 14 is a schematic cross-sectional view and a top view for explaining a conventional method of manufacturing a wiring board. FIG. 15 is a schematic cross-sectional view and a top view for explaining a conventional method of manufacturing a wiring board. FIG. 16 is a schematic cross-sectional view and a top view for explaining a conventional method of manufacturing a wiring board. FIG. 17 is a schematic cross-sectional view and a top view for explaining a conventional method of manufacturing a wiring board. FIG. 18 is a schematic cross-sectional view and a top view for explaining a conventional method of manufacturing a wiring board. FIG. 19 is a schematic cross-sectional view and a top view for explaining a conventional method of manufacturing a wiring board. FIG. 20 is an enlarged schematic cross-sectional view of a main part for explaining a conventional method for manufacturing a wiring board.

  Next, a method for manufacturing a wiring board according to the present invention will be described with reference to the accompanying drawings. 1A and 1B are a cross-sectional view and a top view showing a wiring board 20 manufactured by the method of manufacturing a wiring board according to the present invention. The wiring board 20 is formed by adhering a plurality of core wiring conductors 3 made of copper from the upper surface to the lower surface of the core insulating layer 1 made of a resin-based insulating material having a large number of through holes 2, and further A build-up insulating layer 4 made of a resin-based insulating material and a build-up wiring conductor 5 made of a copper plating layer are laminated on the upper and lower surfaces, and solder resist layers 6a and 6c are sequentially laminated on the upper surface. Is attached, and 6b is attached to the lower surface. In FIG. 1B, the wiring conductor 25 on the upper surface side is indicated by a broken line.

  A mounting portion for mounting the semiconductor element S is provided in the central portion of the upper surface of the wiring board 20, and a large number of semiconductor element connection pads 7 for connecting to the electrodes T of the semiconductor element S are provided on the mounting portion. It is formed by a part of the wiring conductor 5. The semiconductor element S is mounted on the wiring board 20 by bringing the electrodes T of the semiconductor element S into contact with the semiconductor element connection pads 7 and connecting the two via solder.

  The lower surface of the wiring board 20 is an external connection surface for connection to an external electric circuit board, and a large number of external connection pads 8 for connection to the external electric circuit board are provided on the external connection surface. It is formed by a part of the wiring conductor 5. Then, the wiring board 20 is mounted on the external electric circuit board by connecting the external connection pads 8 and the external electric circuit board via solder.

  Further, in this wiring board 20, in order to prevent the oxidation of the semiconductor element connection pad 7 and to improve the connection with the electrode T of the semiconductor element S, the exposed surface of the semiconductor element connection pad 7 is plated with nickel. A nickel-gold plating layer 9 in which gold plating is sequentially deposited by electrolytic plating is applied.

  Now, an embodiment in which the wiring board 20 is manufactured according to the manufacturing method of the present invention will be described with reference to FIGS.

  First, as shown in FIGS. 2 (a) and 2 (b), a wiring board panel 20P in which a large number of product areas X to be the wiring boards 20 are integrally formed around the product area X via a disposal margin area Y is formed. prepare. The wiring board panel 20 </ b> P includes a core insulating layer 1, a core wiring conductor 3, a buildup insulating layer 4, and a buildup wiring conductor 5. In each product region X, the wiring conductor 5 having the semiconductor element connection pad 7 is formed on the surface of the insulating layer 4 on the upper surface side, and the wiring conductor 5 having the external connection pad 8 is formed on the surface of the insulating layer 4 on the lower surface side. To do. Further, a plating conduction line 10 made of copper extending from some of the wiring conductors 5 in the product region X to the disposal margin region Y and electrically connected in common in the disposal margin region Y to the surface of the insulating layer 4 on the upper surface side. A plating conduction line 11 that connects some of the different wiring conductors 5 in the product region X is formed. In FIG. 2 to FIG. 9, for the sake of simplicity, one product area X and the surrounding margin area Y are partially shown.

  Next, as shown in FIGS. 3A and 3B, a solder resist layer 6a is formed on the surfaces of the insulating layer 4 and the wiring conductor 5 on the upper surface side, and the surfaces of the insulating layer 4 and the wiring conductor 5 on the lower surface side. The solder resist layer 6b is formed. The solder resist layer 6 a on the upper surface side exposes the semiconductor element connection pad 7 and the plating conductive lines 10 and 11 and covers the wiring conductor 5 to the vicinity of the semiconductor element connection pad 7. The thickness of the solder resist layer 6 a is about 5 to 10 μm on the wiring conductor 5. Further, the solder resist layer 6b on the lower surface side exposes the external connection pads 8 and covers the remaining portions. The thickness of the solder resist layer 6 b is about 10 to 20 μm on the wiring conductor 5.

  Next, as shown in FIGS. 4A and 4B, a plating mask M1 is formed on the upper and lower surfaces of the wiring board panel 20P. The plating mask M1 on the upper surface side exposes the semiconductor element connection pads 7 and covers the plating conductive lines 10 and 11. The plating mask M1 on the lower surface side covers the external connection pads 8. Such a plating mask M1 is formed by thermally pressing a photosensitive dry film resist onto the upper and lower surfaces of the wiring board panel 20P using a vacuum press, and using a well-known photolithography technique for exposure and development. The

  Next, as shown in FIGS. 5A and 5B, a nickel plating layer and a gold plating layer are sequentially deposited on the surface of the semiconductor element connection pad 7 exposed from the plating mask M1 by an electrolytic plating method. A gold plating layer 9 is formed. In this case, electrolytic plating is performed by supplying electric charges for electrolytic plating to the respective semiconductor element connection pads 7 through the plating conductive lines 10 and 11. At this time, the nickel-gold plating layer 9 is not deposited on the plating conductive lines 10 and 11 and the external connection pads 8 covered with the plating mask M1.

  Next, as shown in FIGS. 6A and 6B, the plating mask M1 is removed. As a result, a wiring board panel 20P in which the nickel-gold plating layer 9 is attached only to the semiconductor element connection pads 7 and the wiring conductors 5 in the vicinity thereof is obtained. The plating mask M1 is removed using an alkaline stripping solution.

  Next, as shown in FIGS. 7A and 7B, a solder resist layer 6 c is formed on the solder resist layer 6 a and the surrounding insulating layer 4 and wiring conductor 5. The solder resist layer 6 c exposes the semiconductor element connection pad 7 and the plating conductive lines 10 and 11 and covers the nickel-gold plating layer 9 deposited on the wiring conductor 5 in the vicinity of the semiconductor element connection pad 7. The thickness of the solder resist layer 6c is about 5 to 10 μm on the solder resist layer 6a. Further, the length L in which the nickel-gold plating layer 9 deposited on the wiring conductor 5 in the vicinity of the semiconductor element connection pad 7 is covered with the solder resist layer 6c is about 5 to 100 μm.

  Next, as shown in FIGS. 8A and 8B, an etching mask M2 is formed on the upper and lower surfaces of the wiring board panel 20P. The etching mask M2 covers the semiconductor element connection pads 7 and the external connection pads 8, and exposes the plating conductive lines 10 and 11. The etching mask M2 is formed by thermally pressing a photosensitive dry film resist on the upper and lower surfaces of the wiring board panel 20P by vacuum press and using a well-known photolithography technique for exposure and development. .

  Next, as shown in FIGS. 9A and 9B, the plating conductive lines 10 and 11 exposed from the etching mask M2 are removed by etching. As the etchant, an etchant that etches only copper and does not etch the nickel-gold plating layer is used. As a result, predetermined ones of the semiconductor element connection pads 7 are electrically independent from each other. At this time, as shown in FIG. 10, even if the etchant E enters the boundary between the semiconductor element connection pad 7 and the solder resist layer 6c due to the tearing or peeling of the etching mask M2, the semiconductor in the wiring conductor 5 Since the boundary between the element connection pad 7 and the solder resist layer 6c and the vicinity thereof are covered and protected by the nickel-gold plating layer 9, wiring at the boundary between the semiconductor element connection pad 7 and the solder resist layer 6c The conductor 5 is not etched locally. Therefore, it is possible to provide a method of manufacturing the wiring board 20 that has a low risk of disconnection in the wiring conductor 5 and is excellent in electrical connection reliability. When the length L of the nickel-gold plating layer 9 deposited on the wiring conductor in the vicinity of the semiconductor element connection pad 7 covered with the solder resist layer 6c is less than 5 μm, the semiconductor element connection pad 7 and the solder resist layer 6c The risk of local etching of the wiring conductor 5 at the boundary increases, and if it exceeds 100 μm, the nickel-gold plating layer 9 is wasted and the manufacturing cost of the wiring board 20 becomes high. . Therefore, the length L in which the nickel-gold plating layer 9 deposited on the wiring conductor near the semiconductor element connection pad 7 is covered with the solder resist layer 6c is preferably in the range of 5 to 100 μm.

  Finally, as shown in FIGS. 11A and 11B, the etching mask M2 is removed, and then the wiring board panel 20P is cut along the boundaries of the product regions X as shown in FIG. Such a wiring board 20 is obtained. Note that an alkaline stripping solution is used to remove the etching mask M2. Note that the present invention is not limited to the above-described embodiment example, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment example, the wiring conductor 5 can be changed. Although the nickel-gold plating layer 9 is deposited on the semiconductor element connection pad 7 and the vicinity thereof, an electrolytic plating layer made of another metal such as electrolytic tin plating may be deposited instead of the nickel-gold plating layer 9. .

DESCRIPTION OF SYMBOLS 1,4 ... Insulation layer 3,5 ... Wiring conductor 6a-6c ... Solder resist layer 7 .... Semiconductor element connection pad 9 .... Electrolysis Plating layer 10, 11 ... Plating conduction line M1 ... Plating mask M2 ... Etching mask

Claims (1)

  Forming a plurality of wiring conductors made of copper having semiconductor element connection pads on the surface of the insulating layer, and a plating conduction line made of copper electrically connecting the plurality of wiring conductors in common; Depositing a lower solder resist layer on the surface of the conductor layer to expose the semiconductor element connection pad and the plating conductive line and to cover the wiring conductor to the vicinity of the semiconductor element connection pad; and the lower layer solder resist Forming a plating mask for exposing the semiconductor element connection pad and the wiring conductor in the vicinity thereof on the layer and covering the plating conductive line; and copper on an exposed portion of the wiring conductor exposed from the plating mask; And a step of depositing an electrolytic plating layer made of different metals, and the plating mask from the lower solder resist layer. And exposing the semiconductor element connection pad and the plating conductive line on the lower solder resist layer and the surrounding insulating layer and the wiring conductor, and covering the wiring conductor in the vicinity of the semiconductor element connection pad. A step of depositing an upper solder resist layer covering the electroplating genus attached, and covering the wiring conductor exposed from the upper solder resist layer on the upper solder resist layer and the plating conductive line A step of forming an etching mask for exposing the etching mask, a step of etching and removing the plating conductive line exposed from the etching mask, and a step of removing the etching mask from the upper solder resist layer. A method for manufacturing a wiring board.

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