JP2009253236A - Method of manufacturing laminated semiconductor circuit board and laminated semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a laminated semiconductor circuit board in which a plated conductive film can be surely embedded, by electrolytic plating, into a through-hole of a laminated semiconductor circuit board having a plurality of circuit boards which are bonded together, and an undesired seed layer can be readily removed after the termination of the electrolytic plating process, and a method of manufacturing a laminated semiconductor device using the same. <P>SOLUTION: Each electrode pad 160 is connected to a nearest seed layer 120b running in a Y direction by the most direct way via patterned seed layers 130. As a result, electrodes 160 of all semiconductor chips 110 are mutually connected via the X directional seed layers 120b and Y directional seed layers 120a, and also connected to right and left feed units 140. Accordingly, if a predetermined voltage is applied to the feed units 140, then the applied voltage is provided to electrode pads 160 of all semiconductor chips 110. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a laminated semiconductor circuit board obtained by bonding a plurality of circuit boards and a method for manufacturing a laminated semiconductor device using the same.

  2. Description of the Related Art Conventionally, in a laminated semiconductor device manufactured by bonding a plurality of semiconductor chips, through holes are provided to electrically connect the laminated semiconductor chips, and a conductive film is formed in the through holes by sputtering or electroless plating. Was embedded.

For example, Patent Document 1 discloses a method of forming a conductive film on the inner surfaces of through holes provided in a plurality of semiconductor chips bonded together with an adhesive by an electroless plating method of gold.
JP 2001-250912 A

  However, in the sputtering method, since the aspect ratio of the through hole (depth of the through hole / diameter of the through hole) is large, it is difficult for the sputtered atoms to reach the vicinity of the bottom of the through hole. For this reason, there exists a problem that the film thickness of a electrically conductive film becomes thin near the bottom part of a through-hole, a void (gap | space) generate | occur | produces, and it becomes easy to disconnect. In addition, when the conductive film is formed by electroless plating, the growth rate of the conductive film changes due to the pretreatment of the base layer on which the conductive film is formed, or the surface of the portion to be plated has catalytic characteristics suitable for the plating solution. There is a problem that the base film is limited because it must be done. Furthermore, since the growth rate of the conductive film is slow, there is a problem that the throughput of the electroless plating process is slow.

  For this reason, it is conceivable to form a conductive film (hereinafter referred to as “plated conductive film”) on the inner surface of the through hole by an electrolytic plating method without such a problem. However, in the electrolytic plating method, since it is necessary to apply a voltage to a place where the plated conductive film is formed, it is necessary to form a seed layer made of the same material as the plated conductive film. This seed layer is usually formed by sputtering after the through holes are formed. However, when the seed layer is formed by sputtering after bonding the semiconductor chips, if the through hole has a large aspect ratio, the thickness of the seed layer near the bottom of the seed layer is reduced. There is a problem that it is impossible to apply an appropriate voltage.

  On the other hand, when the seed layer is formed on the surface of the lower substrate before the formation of the through hole, it is necessary to remove the unnecessary seed layer after the electrolytic plating process is completed. It is difficult to remove. In this case, since the seed layers formed in the respective through holes remain connected to each other, there is a problem that the stacked semiconductor device does not operate normally.

  Therefore, the present invention can reliably embed a plated conductive film in a through hole of a laminated semiconductor circuit board on which a plurality of circuit boards are bonded together by electrolytic plating and an unnecessary seed layer when dicing the laminated semiconductor circuit board. It is an object of the present invention to provide a laminated semiconductor circuit board that can remove the substrate and a method of manufacturing a laminated semiconductor device using the same.

1st invention is the manufacturing method of the laminated semiconductor device which connects between the some circuit boards bonded together by the plating electrically conductive film embedded at the through-hole provided in the said circuit board,
A chip forming step of forming a semiconductor chip having at least one electrode pad on a lower substrate;
A seed layer of the same material as the plated conductive film is formed on the scribe line and the electrode pad around the semiconductor chip of the lower layer substrate, and the seed layer on the electrode pad is used as a seed layer on the scribe line. Forming a seed layer so as to connect and connect the seed layers on the scribe line to each other;
Forming the through-hole at a position corresponding to the electrode pad of the upper substrate composed of at least one circuit substrate laminated on the lower substrate;
A circuit board forming step of forming a laminated semiconductor circuit board by adhering the upper substrate to the lower substrate so that the through hole is located on the electrode pad;
The multilayer circuit board is immersed in an electrolyte solution containing metal ions of the same material as the plated conductive film, and a negative voltage is applied to the seed layers on the scribe lines connected to each other to apply the negative voltage to the through holes. A plating process for embedding a plated conductive film;
Forming a wiring connected to the plated conductive film on the surface of the upper substrate;
And a dicing step of dicing the laminated semiconductor circuit board along the scribe line.

According to a second invention, in the first invention,
In the seed layer forming step, the seed layer on the electrode pad is connected to a seed layer on a scribe line closest to the electrode pad.

According to a third invention, in the first invention,
In the seed layer forming step, at the same time as forming the seed layer, a power feeding portion to which a negative voltage is applied from the outside is formed at an end portion of the lower substrate so as to be connected to the seed layer on the scribe line. And

According to a fourth invention, in the first invention,
The bonding step includes
A pressurizing step in which a positive photosensitive adhesive film is sandwiched between the upper layer substrate and the lower layer substrate to pressurize while heating to a predetermined temperature;
And removing the photosensitive adhesive film inside the through hole by exposing and developing the photosensitive adhesive film with the upper substrate as a mask.

According to a fifth invention, in the first invention,
The upper layer substrate and the lower layer substrate are silicon wafers, and a surface of the upper layer substrate and an inner surface of the through hole are covered with an insulating film.

According to a sixth invention, in the first invention,
The wiring step includes a cleaning step of cleaning the surface of the plated conductive film with an inert atom by sputter etching before forming the wiring.

According to a seventh invention, in the first invention,
The wiring is characterized by comprising two layers of a barrier metal layer and a conductive layer at least on the surface of the plated conductive film.

An eighth invention is a laminated semiconductor circuit substrate that connects a plurality of bonded circuit boards with a plated conductive film embedded in a through-hole provided in the circuit board,
A semiconductor chip having at least one electrode pad, and a seed layer formed on the scribe line around the semiconductor chip and on the electrode pad with the same material as the plated conductive film, the scribe line A lower substrate formed so that the seed layers on the upper and the electrode pads are connected to each other;
An upper substrate composed of at least one circuit board in which the through hole is formed at a position corresponding to the electrode pad of the lower substrate;
An adhesive layer that bonds the upper substrate to the lower substrate such that the through hole is located on the electrode pad;
The plated conductive film embedded in the through hole connecting the electrode pad to the upper substrate;
And a wiring formed on a surface of the upper substrate and connected to the plated conductive film.

In a ninth aspect based on the eighth aspect,
The seed layer on the electrode pad is connected to the seed layer on the scribe line closest to the electrode pad.

In a tenth aspect based on the eighth aspect,
It further comprises a power feeding unit to which a negative voltage is applied to the end of the lower layer substrate from the outside,
The seed layers on the scribe line are connected to each other and connected to the power feeding unit.

  According to the first invention, a negative voltage is applied to the seed layer formed on the scribe line in a state where the seed layer formed on the electrode pad of the lower layer substrate is connected to the seed layer on the scribe line. When electrolytic plating is performed, the seed layer in the through hole becomes a cathode. Therefore, the plated conductive film can be embedded in the through hole without forming defects such as voids. Further, when dicing along the scribe line, the seed layer on the scribe line to which the electrode pads are connected is removed at the same time. For this reason, the seed layers on the electrode pads connected to each other become isolated patterns separated from each other after dicing. Therefore, in the laminated semiconductor device after dicing, each electrode pad is not short-circuited through the seed layer. Thus, according to this manufacturing method, electrolytic plating can be reliably performed on the through hole of the laminated semiconductor device, and an unnecessary seed layer can be removed during dicing.

  According to the second invention, since the seed layer on the electrode pad is connected to the seed layer on the scribe line closest thereto, the seed layer on the electrode pad and the seed layer on the scribe line are surely cut by dicing. be able to.

  According to the third aspect of the present invention, the negative voltage given from the outside in the plating process is applied to the power supply part of the lower substrate, and the seed layer inside all the through holes is reliably connected to the seed layer on the scribe line. A negative voltage can be applied to.

  According to the fourth invention, after the upper substrate and the lower substrate are bonded with the positive photosensitive adhesive layer, the photosensitive adhesive layer inside the through hole can be easily removed simply by exposing and developing from the upper substrate. Thus, the surface of the electrode pad can be exposed.

  According to the fifth invention, by covering the surface of the silicon wafer as the upper layer substrate and the inner surface of the through hole with the insulating film, the wiring formed on the surface of the silicon wafer, the device to be mounted, or the through hole is embedded. It is possible to prevent the plated conductive film from coming into contact with the silicon wafer and short-circuiting.

  According to the sixth invention, by performing sputter etching on the surface of the plated conductive film with inert atoms, it is possible to maintain ohmic contact with the wiring formed on the surface.

  According to the seventh invention, since the barrier metal layer is formed between the plated conductive film and the conductive layer, the atoms constituting the plated conductive film and the atoms constituting the conductive layer are diffused to each other. Can be prevented.

<1. Multilayer Semiconductor Circuit Board>
FIG. 1 is a view showing a silicon wafer 100 (also referred to as “lower layer wafer 100”) used as a lower layer substrate of a laminated semiconductor circuit substrate according to an embodiment of the present invention, and FIG. 2 is a diagram showing the silicon wafer 100 shown in FIG. FIG. As shown in FIG. 1, a plurality of semiconductor chips 110 are arranged in a matrix in the X direction and the Y direction on a silicon wafer 100 as a lower substrate, and are formed in the X direction and the Y direction between the semiconductor chips 110. Patterned seed layers 120a and 120b are formed on the scribe lines 150a and 150b so as to surround the semiconductor chips 110, respectively. These seed layers 120 a and 120 b are connected to each other and to a power feeding unit 140 provided on the left and right of the lower layer wafer 100. Each semiconductor chip 110 is connected to a seed layer 120b in the Y direction by a seed layer 130, as will be described later. In the following description, the seed layer 120a formed on the X-direction scribe line 150a is referred to as the X-direction seed layer, and the seed layer 120b formed on the Y-direction scribe line 150b is referred to as the Y-direction seed layer. There is.

  Referring to FIG. 2, three electrode pads 160 are formed in the vertical direction (Y direction) along the left and right (X direction) ends of each semiconductor chip 110. Each electrode pad 160 is connected to the nearest seed layer 120b in the Y direction by the patterned seed layer 130 at the shortest distance. As a result, the electrode pads 160 of all the semiconductor chips 110 are connected to each other via the seed layer 120b in the Y direction and the seed layer 120a in the X direction, and are also connected to the left and right power supply units 140. Therefore, if a predetermined voltage is applied to the power supply unit 140, the applied voltage is applied to the electrode pads 160 of all the semiconductor chips 110.

  FIG. 3 is a diagram showing a silicon wafer 200 (also referred to as “upper layer wafer 200”) used as an upper layer substrate of the laminated semiconductor circuit substrate according to one embodiment of the present invention, and FIG. 4 is a diagram showing the silicon wafer 200 shown in FIG. FIG. As shown in FIG. 3, a through-hole 210 is formed in the silicon wafer 200 as an upper substrate as will be described later. In addition, notches 220 are provided at the left and right ends of the upper layer wafer 200 in correspondence with the power feeding units. The notch 220 is provided to facilitate connection of a terminal for applying a voltage to the power supply unit 140 when a plated conductive film is formed in the electrolytic plating process. In this embodiment, the size of the upper layer wafer 200 is the same as the size of the lower layer wafer 100.

  As shown in FIG. 4, the upper layer wafer 200 has three electrode pads 160 formed in the vertical direction (Y direction) along the left and right (X direction) ends of the respective semiconductor chips 110 of the lower layer wafer 100. Through holes 210 are provided at corresponding positions.

  FIG. 5 is a cross-sectional view showing a cross section of the laminated semiconductor circuit substrate 300 in which the upper layer wafer 200 and the lower layer wafer 100 are bonded together. As can be seen from FIG. 5, the upper layer wafer 200 and the lower layer wafer 100 are bonded by the photosensitive adhesive resin 170 in a state in which each through hole 210 of the upper layer wafer 200 is positioned on each electrode pad 160 of the lower layer wafer 100. By performing electrolytic plating in this state, the through hole 210 is filled with the plated conductive film 180 from the bottom seed layer 130 to the surface of the upper wafer 200.

  In addition, electrode pads 160 are formed at the chip ends of the respective semiconductor chips 110 formed on the lower wafer 100. Seed layers 130, 120a, 120b are formed on the electrode pad 160 and the scribe lines 150a, 150b, and the seed layer 130 on each electrode pad 160 is connected to the seed layer 120b on the nearest scribe line 150b. On the upper wafer 200, a wiring 250 in which a barrier metal layer 230 and an aluminum layer 240 are laminated is formed on the surface of the plated conductive film 180 by ohmic contact, and the wiring 250 is mounted on the upper wafer 200. Connected to the installed device 260. As a result, the semiconductor chip 110 of the lower wafer 100 is connected to the upper device 260 through the plated conductive film 180 in the through hole 210. Note that the device 260 includes an individual semiconductor, an LSI (Large Scale Integration), a light emitting element, and the like.

  FIG. 6 is an enlarged view showing a state of the lower layer wafer 100 after the laminated semiconductor circuit substrate 300 is diced. When the semiconductor chips 110 are separated by dicing along the scribe lines 150a and 150b in the X direction and the Y direction, the seed layers 130 on the electrode pads 160 are separated from each other and around the electrode pads 160, respectively. Only an isolated pattern remains. For this reason, even if a power supply voltage or an input signal is applied to the electrode pads 160 of the semiconductor chip 110, the electrode pads 160 are not short-circuited via the seed layer 130.

<2. Manufacturing method of laminated semiconductor device>
Next, a manufacturing method of the laminated semiconductor circuit device will be described. 7 to 10 are cross-sectional views illustrating a method for manufacturing a laminated semiconductor device in which the semiconductor chips 110 of the upper layer wafer 200 and the lower layer wafer 100 are bonded together. With reference to FIGS. 7-10, the manufacturing method of a laminated semiconductor device is demonstrated.

  First, a method for manufacturing the lower layer wafer 100 will be described. As shown in FIG. 7A, semiconductor chips 110 are formed in a matrix on the surface of the lower wafer 100. A protective film (passivation film) (not shown) made of a silicon nitride film or the like is formed on the surface of each formed semiconductor chip 110. Next, an opening is formed in the protective film so that an electrode pad 160 for electrically connecting the semiconductor chip 110 to a wiring 250 formed on the surface of the upper layer wafer 200 described later is exposed. The electrode pad 160 is made of aluminum or an alloy obtained by adding silicon, copper, or the like to aluminum. Since the steps up to here are the same as the well-known LSI manufacturing process, a detailed description of the manufacturing process is omitted.

  Then, a barrier layer (not shown) having a thickness of about 100 to 500 nm and a seed layer 120 having a thickness of about 100 to 500 nm are sequentially formed on the surface of the lower wafer 100 by sputtering. The barrier layer is made of titanium (Ti), titanium / tungsten (TiW), chromium (Cr), or the like, and prevents the atoms constituting the plated conductive film 180 and the aluminum atoms of the electrode pad 160 from diffusing each other. In addition, since the seed layer 120 serves as a seed layer for the plated conductive film 180 formed by electrolytic plating, the seed layer 120 needs to be formed of the same material as the plated conductive film 180. Therefore, when the plating conductive film 180 formed by electrolytic plating is copper, the seed layer 120 is also formed of copper, and when the plating conductive film 180 is gold, the seed layer 120 is also formed of gold. Note that the seed layer 120 may be formed by an evaporation method.

  Next, as shown in FIG. 7B, a photoresist is applied to the upper surface of the seed layer 120, and then exposed and developed to form a resist pattern 10 in a portion where the seed layer remains. Then, unnecessary seed layer 120 is removed by etching using resist pattern 10 as a mask. The seed layer 120 is etched by immersing it in a mixed solution of sulfuric acid and hydrogen peroxide solution when the seed layer 120 is copper, and aqua regia or potassium iodide when the seed layer 120 is gold. It is carried out by dipping in a mixed solution of iodine. After removing the unnecessary seed layer 120, the resist pattern 10 is further removed. As a result, patterned seed layers 130, 120a, 120b are formed on each electrode pad 160 and scribe lines 150a, 150b, and the seed layer 130 on each electrode pad 160 is a seed layer on the nearest scribe line 150b. 120b. That is, as described above with reference to FIG. 2, the patterned seed layers 120 a, 120 b, and 130 are formed on the scribe lines 150 a and 150 b around each semiconductor chip 110 and each of the semiconductor chips 110 is formed. It is also formed on the electrode pad 160. The seed layer 130 on each electrode pad 160 is formed to be connected to the closest Y-direction seed layer 120b.

  Next, a method for manufacturing the upper layer wafer 200 will be described. As described with reference to FIGS. 3 and 4, the through-holes 210 are formed at the positions of the upper layer wafer 200 corresponding to the electrode pads 160 of the lower layer wafer 100. The through hole 210 is formed by irradiating the position where the through hole 210 is formed with laser light. Instead of irradiating with laser light, a photoresist is applied on the upper layer wafer 200 to form a resist pattern (not shown) having an opening at the formation position of the through hole, and this resist pattern is used as a mask. The through-hole 210 may be formed by immersing in an alkaline aqueous solution such as potassium hydroxide or performing plasma etching using a tetrafluorinated carbon gas.

  Next, the upper layer wafer 200 in which the through hole 210 is formed is oxidized to form a silicon oxide film (not shown) on at least the surface of the upper layer wafer 200 and the inner surface of the through hole 210. This silicon oxide film is for electrically insulating the device 260 placed on the upper wafer 200, the wiring 250 formed on the upper wafer 200, and the plated conductive film 180 in the through hole from the upper wafer 200, respectively. It is. Note that an insulating film such as a silicon nitride film may be formed instead of the silicon oxide film.

  Next, as shown in FIG. 7C, a photosensitive adhesive resin 170 called a dry film is placed on the lower wafer 100 and heated to about 150 ° C. to 250 ° C.

  As shown in FIG. 8A, the upper layer wafer 200 is placed on the photosensitive adhesive resin 170 so that the through holes 210 are positioned on the corresponding electrode pads 160 of the lower layer wafer 100. Then, a predetermined pressure is applied to press the upper wafer 200 against the lower wafer 100 to bond the upper wafer 200 and the lower wafer 100 together, and then the upper wafer 200 is used as a mask for exposure. Since the photosensitive adhesive resin 170 is mainly composed of a positive photoresist, when exposed and developed, the photosensitive adhesive resin 170 in the through hole 210 is dissolved in the developer and removed. Therefore, as shown in FIG. 8B, the seed layer 130 formed on the electrode pad 160 in the through hole 210 is exposed.

  Next, a plated conductive film 180 is formed in the through hole 210 by electrolytic plating. In the electrolytic plating method, a laminated semiconductor circuit board 300 in which the upper and lower wafers 100 and 200 are bonded together and a metal plate made of the same material as the plating conductive film 180 are immersed in a plating solution, and the power supply unit 140 of the lower wafer 100 is applied to the power supply unit 140. A negative voltage is applied, and a positive voltage is applied to the metal plate. When a copper film is formed as the plating conductive film 180, a copper sulfate aqueous solution, a copper cyanide aqueous solution, or the like is used as a plating solution, and a copper plate is used as a metal plate. When a gold film is formed as the plating conductive film 180, a gold sulfite aqueous solution or a gold cyanide aqueous solution is used as a plating solution, and a gold plate is used as a metal plate.

  As a result, as shown in FIG. 9A, a plated conductive film 180 is formed in the through hole 210 from the seed layer 130 toward the surface of the upper wafer 200. The plated conductive film 180 is preferably formed to be about 1 mm higher than the surface of the upper wafer 200. In this case, since the tip of the plated conductive film 180 has a mushroom shape, the plated conductive film 180 is easily connected to the wiring 250 formed on the upper layer wafer 200 in a later step.

  Next, as shown in FIG. 9B, after the surface of the plated conductive film 180 is sputter-etched with argon (Ar) gas, titanium (Ti), titanium / tungsten (TiW), chromium is formed on the surface of the upper wafer 200. A barrier metal layer 230 such as (Cr) is formed by sputtering, and an aluminum layer 240 is further formed thereon by sputtering. Then, a resist pattern 20 is formed only on the aluminum layer 240 to be the wiring 250 by applying a photoresist on the aluminum layer 240 and exposing and developing the photoresist.

  Then, as shown in FIG. 10A, using the resist pattern 20 as a mask, the aluminum layer 240 and the barrier metal layer 230 are etched in this order by plasma etching, and the aluminum layer 240 and the barrier metal layer 230 are patterned. As a result, on the upper wafer 200, a wiring 250 made of the barrier metal layer 230 and the aluminum layer 240 and connected to the plating conductive film 180 is formed. The device 260 is soldered to a predetermined position on the formed wiring 250.

  The reason why the surface of the plated conductive film 180 is cleaned by sputter etching using an inert gas such as argon gas is to ensure ohmic contact between the plated conductive film 180 and the barrier metal layer 230. Further, the barrier metal layer 230 is formed between the plated conductive film 180 and the aluminum layer 240 so that aluminum atoms and copper atoms or gold atoms of the plated conductive film are not diffused and alloyed with each other. Because. Therefore, the barrier metal layer 230 may be formed at least on the surface of the plated conductive film 180.

  Next, as shown in FIG. 10B, the upper layer wafer 200 and the lower layer wafer 100 are attached to the back surface of the lower layer wafer 100 on the adhesive tape 400, and are diced along the scribe lines 150a and 150b in the X and Y directions. Disconnect. And in order to make it easy to peel the cut | disconnected semiconductor chip 110 from the adhesive tape 400, after extending | stretching the adhesive tape 400 so that it may mutually isolate | separate only a predetermined space | interval, the semiconductor chip 110 is adsorb | sucked one by one with a collet. To peel from the adhesive tape 400.

<3. Effect>
When the laminated semiconductor circuit board 300 of the present invention is manufactured, the seed layers 130 formed on the electrode pads 160 are connected to each other via the Y-direction seed layer 120b formed on the scribe line 150b. In the electrolytic plating process, power can be reliably supplied to the seed layer 130 in the through hole 210. Therefore, the plated conductive film 180 can be embedded in the through hole 210 without causing defects such as voids.

  Further, when dicing the laminated semiconductor circuit board 300, the seed layers 120a and 120b formed on the scribe lines 150a and 150b are also removed at the same time, and the seed layers 130 on the electrode pads 160 are separated from each other by dicing. Become an isolated pattern. Therefore, each electrode pad 160 is not short-circuited through the seed layer 130, and the semiconductor chip operates normally.

<4. Modification>
The laminated semiconductor circuit board 300 is not limited to a laminate of two silicon wafers 100 and 200, and may be a laminate of three or more circuit boards.

  Further, instead of placing the device 260 on the upper layer wafer 200, a semiconductor chip is also formed on the upper layer wafer 200, and the semiconductor chip 110 of the lower layer wafer 100 is attached to the upper layer wafer 200 via the plated conductive film 180 and the wiring 250. You may connect to a semiconductor chip.

  Even if the upper layer wafer 200 is smaller than the lower layer wafer 100, it may be any size as long as the corresponding through holes 210 can be formed on all the electrode pads 160 on the lower layer wafer 100. In this case, if the power supply unit 140 of the lower layer wafer 100 is not covered by the upper layer wafer 200, it is not necessary to provide the notch 220 in the upper layer wafer 200.

  As the upper layer wafer 200, a quartz substrate may be used instead of the silicon wafer. When a quartz substrate is used, it is not necessary to form an insulating film such as an oxide film on the surface because the quartz substrate itself is an insulating substrate.

  In the above-described embodiment, the seed layer 130 formed on the electrode pad 160 is all connected to the seed layer 120b in the Y direction. However, the electrode pad 160 may be disposed along the scribe line 150a in the X direction, and the seed layer 130 may be connected only to the seed layer 120a in the X direction. Further, the electrode pad 160 may be disposed along the scribe lines 150a and 150b in the X direction and the Y direction, and connected to the seed layers 120a and 120b in the X direction and the Y direction.

It is a figure which shows the silicon wafer used as a lower layer board | substrate of the laminated semiconductor circuit board which concerns on one Embodiment of this invention. It is an enlarged view of the silicon wafer shown in FIG. It is a figure which shows the silicon wafer used as an upper layer board | substrate of the laminated semiconductor circuit board which concerns on one Embodiment of this invention. FIG. 4 is an enlarged view of the silicon wafer shown in FIG. 3. It is sectional drawing which shows the cross section of the laminated semiconductor circuit board which bonded the upper layer wafer and the lower layer wafer. It is an enlarged view which shows the state of the lower layer wafer after dicing the laminated semiconductor circuit board. It is sectional drawing which shows the manufacturing process of the laminated semiconductor device of this invention. It is sectional drawing which shows the manufacturing process of the laminated semiconductor device of this invention. It is sectional drawing which shows the manufacturing process of the laminated semiconductor device of this invention. It is sectional drawing which shows the manufacturing process of the laminated semiconductor device of this invention.

Explanation of symbols

100: Silicon wafer (lower layer wafer)
DESCRIPTION OF SYMBOLS 110 ... Semiconductor chip 120a, 120b, 130 ... Seed layer 140 ... Feed part 150a, 150b ... Scribe line 160 ... Electrode pad 170 ... Photosensitive adhesive resin 180 ... Plating conductive film 200 ... Silicon wafer (upper layer wafer)
210 ... through hole 230 ... barrier metal layer 240 ... aluminum layer 250 ... wiring

Claims (10)

A method for manufacturing a laminated semiconductor device, wherein a plurality of bonded circuit boards are connected by a plated conductive film embedded in a through hole provided in the circuit board,
A chip forming step of forming a semiconductor chip having at least one electrode pad on a lower substrate;
A seed layer of the same material as the plated conductive film is formed on the scribe line and the electrode pad around the semiconductor chip of the lower layer substrate, and the seed layer on the electrode pad is used as a seed layer on the scribe line. Forming a seed layer so as to connect and connect the seed layers on the scribe line to each other;
Forming the through-hole at a position corresponding to the electrode pad of the upper substrate composed of at least one circuit substrate laminated on the lower substrate;
A circuit board forming step of forming a laminated semiconductor circuit board by adhering the upper substrate to the lower substrate so that the through hole is located on the electrode pad;
The multilayer circuit board is immersed in an electrolyte solution containing metal ions of the same material as the plated conductive film, and a negative voltage is applied to the seed layers on the scribe lines connected to each other to apply the negative voltage to the through holes. A plating process for embedding a plated conductive film;
Forming a wiring connected to the plated conductive film on the surface of the upper substrate;
And a dicing step of dicing the laminated semiconductor circuit board along the scribe line.   2. The method of manufacturing a stacked semiconductor device according to claim 1, wherein in the seed layer forming step, the seed layer on the electrode pad is connected to a seed layer on a scribe line closest to the electrode pad.   In the seed layer forming step, at the same time as forming the seed layer, a power feeding portion to which a negative voltage is applied from the outside is formed at an end portion of the lower substrate so as to be connected to the seed layer on the scribe line. A method for manufacturing a laminated semiconductor device according to claim 1. The bonding step includes
A pressurizing step in which a positive photosensitive adhesive film is sandwiched between the upper layer substrate and the lower layer substrate to pressurize while heating to a predetermined temperature;
2. The stacked semiconductor according to claim 1, further comprising a removing step of removing the photosensitive adhesive film inside the through hole by exposing and developing the photosensitive adhesive film using the upper substrate as a mask. Device manufacturing method.   2. The method of manufacturing a laminated semiconductor device according to claim 1, wherein the upper layer substrate and the lower layer substrate are silicon wafers, and a surface of the upper layer substrate and an inner surface of the through hole are covered with an insulating film.   2. The stacked semiconductor device according to claim 1, wherein the wiring step includes a cleaning step of cleaning the surface of the plated conductive film with sputter etching using inert atoms before forming the wiring. 3. Production method.   The method for manufacturing a laminated semiconductor device according to claim 1, wherein the wiring includes at least two layers of a barrier metal layer and a conductive layer on the surface of the plated conductive film. A laminated semiconductor circuit board that connects a plurality of bonded circuit boards with a plated conductive film embedded in a through-hole provided in the circuit board,
A semiconductor chip having at least one electrode pad, and a seed layer formed on the scribe line around the semiconductor chip and on the electrode pad with the same material as the plated conductive film, the scribe line A lower substrate formed so that the seed layers on the upper and the electrode pads are connected to each other;
An upper substrate composed of at least one circuit board in which the through hole is formed at a position corresponding to the electrode pad of the lower substrate;
An adhesive layer that bonds the upper substrate to the lower substrate such that the through hole is located on the electrode pad;
The plated conductive film embedded in the through hole connecting the electrode pad to the upper substrate;
A laminated semiconductor circuit board, comprising: a wiring formed on a surface of the upper substrate and connected to the plating conductive film.   9. The stacked semiconductor circuit substrate according to claim 8, wherein the seed layer on the electrode pad is connected to the seed layer on the scribe line closest to the electrode pad. It further comprises a power feeding unit to which a negative voltage is applied to the end of the lower layer substrate from the outside,
9. The laminated semiconductor circuit board according to claim 8, wherein the seed layers on the scribe line are connected to each other and connected to the power feeding unit.

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