JP4868379B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of etching processes for forming a base metal layer in a semiconductor device in which a solder ball is provided on the base metal layer. <P>SOLUTION: A plating resist film 11 is pattern-formed to the upper face of an Ni-Ti layer 7a and a Cu layer 7b formed by sputtering or the like. Next, electrolytic plating of Ni is executed. Then, an Ni plating layer 8 and a solder layer 13 for forming a solder ball are formed on the upper face of the Cu layer 7b in the opening 12 of the plating resist film 11 by executing the electrolytic plating of solder. After that, the plating resist film 11 is peeled off. Then, patterning is executed by etching the Cu layer 7b and the Ni-Ti layer 7a by using the solder layer 13 as a mask. Consequently, the base metal layer composed of the Ni-Ti layer 7a and the Cu layer 7b is formed under the Ni plating layer 8 below the solder layer 13. On that occasion, an etching liquid capable of etching Cu and Ni-Ti together, for example, a mixed liquid composed by mixing 5 wt.% of an acetic acid, 1 wt.% of a hydrogen peroxide solution, 10 wt.% of a nitric acid, and 84 wt.% of purified water is used as the etching liquid. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In a conventional semiconductor element, a base metal layer composed of a Ti—W layer and a Cu layer is provided in a solder ball formation region on a semiconductor substrate, and a by-product containing a plated layer composed of Cu and Ti—W is formed thereon. There is one in which a layer is provided and a solder ball is provided thereon (see, for example, Patent Document 1).

JP 2003-37128 A

  By the way, when manufacturing the above conventional semiconductor element, a Ti—W layer and a Cu layer are formed on a semiconductor substrate by sputtering, a plating resist film having an opening is formed on the Cu layer, and the Cu layer is plated. By performing electrolytic plating of Cu as a current path, a plating layer is formed on the Cu layer in the opening of the plating resist film, the plating resist film is peeled off, and the Cu layer is wet etched using the plating layer as a mask, The Cu layer remains only under the plating layer, and the Ti-W layer is dry-etched using the plating layer as a mask, so that the Ti-W layer remains only under the Cu layer under the plating layer and the surface of the plating layer. A by-product layer containing Ti-W is formed on the solder, and solder balls are formed on the by-product layer.

  However, in the above conventional semiconductor device manufacturing method, the Cu layer is wet etched using the plating layer as a mask, and then the Ti-W layer is dry etched using the plating layer as a mask. there were.

  Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the number of etching steps.

In order to achieve the above object, the present invention provides a semiconductor element in which solder balls are provided on a base metal layer provided on a semiconductor substrate. The semiconductor substrate includes at least a part of a connection pad and the connection pad. protective film exposed is provided, the base metal layer is provided in contact respectively on said connecting pads and the protective film, the underlying metal layer comprises at least Ni-Ti layer and a Cu layer, and, The Ni—Ti layer and the Cu layer are formed by patterning by one etching .

  According to the present invention, for example, when the base metal layer is formed of the lower Ni—Ti layer and the upper Cu layer, these can be etched with the same etching solution, and therefore, the Ni—Ti layer and the Cu layer can be etched. The underlying metal layer forming layer to be formed can be patterned by one etching to form the underlying metal layer, and the number of etching steps can be reduced.

(First embodiment)
FIG. 1 shows a cross-sectional view of a semiconductor device as a first embodiment of the present invention. This semiconductor element includes a silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 1, and a plurality of connection pads 2 made of Al are provided on the periphery of the upper surface so as to be connected to the integrated circuit.

  An insulating film 3 made of silicon nitride or the like is provided on the upper surface of the silicon substrate 1 except for the central portion of the connection pad 2, and the central portion of the connection pad 2 is exposed through an opening 4 provided in the insulating film 3. Yes. A protective film (insulating film) 5 made of polyimide resin or the like is provided on the upper surface of the insulating film 3. In this case, an opening 6 is provided in the protective film 5 at a portion corresponding to the opening 4 of the insulating film 3.

  On the upper surface of the protective film 5 on the connection pad 2, a base metal layer 7 composed of a Ni—Ti layer 7 a and a Cu layer 7 b is provided connected to the connection pad 2 through both openings 4 and 6. A Ni plating layer 8 is provided on the entire upper surface of the base metal layer 7. Solder balls 9 are provided on the upper surface of the Ni plating layer 8.

  Here, the Ni—Ti layer 7a is for improving the adhesion to the connection pad 2 made of Al and the protective film 5 made of polyimide resin or the like. Sex is obtained. The Ni—Ti layer 7 a also has a function of preventing the diffusion of Sn or the like contained in the solder balls 9. The Cu layer 7b serves as a plating current path during electrolytic plating. The Ni plating layer 8 is for preventing the diffusion of Sn or the like contained in the solder balls 9.

  By the way, the Ti content of the Ni—Ti layer 7a is preferably 6.5 to 10 wt%. The reason is that when the Ti content is less than 6.5 wt%, the Ti content is small, the adhesion to the connection pad 2 and the protective film 5 is lowered, and the etching characteristics are changed. This is because if the content exceeds 10 wt%, the Ni—Ti gate gate itself used when forming the Ni—Ti layer by sputtering is likely to break.

(Example of manufacturing method)
Next, an example of a method for manufacturing the semiconductor element shown in FIG. 1 will be described. First, as shown in FIG. 2, a connection pad 2 made of Al, an insulating film 3 made of silicon nitride, and a protective film 5 made of polyimide resin or the like are provided on a silicon substrate (semiconductor substrate) 1 in a wafer state. A connection pad 2 whose central portion is exposed through openings 4 and 6 formed in the insulating film 3 and the protective film 5 is prepared.

  In this case, an integrated circuit (not shown) having a predetermined function is formed in each semiconductor element formation region on the upper surface of the silicon substrate 1 in a wafer state, and the connection pads 2 formed in the peripheral part of the region are respectively It is electrically connected to an integrated circuit formed in the corresponding region.

  Next, as shown in FIG. 3, the Ni—Ti layer 7 a is formed on the entire upper surface of the protective film 5 including the upper surface of the connection pad 2 exposed through both openings 4 and 6 by sputtering or vapor deposition. And Cu layer 7b is continuously formed. In this case, as an example, the thickness of the Ni—Ti layer 7a is about 600 nm, and the thickness of the Cu layer 7b is about 300 nm.

  Next, as shown in FIG. 4, a plating resist film 11 is formed on the upper surface of the Cu layer 7b. In this case, an opening 12 is formed in the plating resist film 11 in a portion corresponding to the Ni plating layer 8 formation region. Next, Ni plating is performed using the Cu layer 7b as a plating current path, thereby forming the Ni plating layer 8 on the upper surface of the Cu layer 7b in the opening 12 of the plating resist film 11.

  Next, as shown in FIG. 5, the solder for forming solder balls is formed on the upper surface of the Ni plating layer 8 in the opening 12 of the plating resist film 11 by performing electrolytic plating of solder using the Cu layer 7b as a plating current path. Layer 13 is formed. Next, the plating resist film 11 is stripped using a resist stripping solution or an asher (oxygen plasma).

Next, when the Cu layer 7b and the Ni—Ti layer 7a are etched and patterned using the solder layer 13 as a mask, the Ni—Ti layer 7a and the Cu layer are formed under the Ni plating layer 8 under the solder layer 13 as shown in FIG. A base metal layer 7 composed of the layer 7b is formed. In this case, as the etching solution, together etchable etchant Cu and Ni-Ti, for example, acetic acid 5 wt%, hydrogen peroxide water 1 wt%, nitric acid 10 wt%, a mixed solution of pure water 84 wt%.

  Then, when the Cu layer 7b is etched using the solder layer 13 as a mask while the mixed solution is kept at a liquid temperature of about 55 ° C., the etching rate is about 250 nm / min, and the film thickness of the Cu layer 7b is about 300 nm. Just etching is performed in about 72 seconds. Subsequently, when the Ni-Ti layer 7a is etched using the solder solution 13 as a mask while the mixed solution is kept at a liquid temperature of about 55 ° C., the etching rate is about 400 nm / min, and the Ni-Ti layer 7a film is formed. When the thickness is about 600 nm, just etching is performed in about 90 seconds.

  Thus, when the above mixed solution is used as the etching solution, both the Cu layer 7b and the Ni—Ti layer 7a can be etched. Therefore, when the base metal layer forming layer composed of the Cu layer 7b and the Ni—Ti layer 7a is patterned by one etching using the solder layer 13 as a mask, the Ni—Ti layer 7a is formed under the Ni plating layer 8 under the solder layer 13. And the base metal layer 7 made of the Cu layer 7b is formed, and the number of etching steps can be reduced.

  Next, when the solder layer 13 is reflowed using a reflow furnace or the like, the solder layer 13 is once melted and then rounded by the surface tension, so that the solder balls 9 are formed on the upper surface of the Ni plating layer 8 as shown in FIG. It is formed. Next, when the lower surface of the silicon substrate 1 is attached to a dicing tape (not shown), the dicing step shown in FIG. 8 is performed, and then peeled off from the dicing tape, a plurality of semiconductor elements shown in FIG. 1 are obtained.

(Other examples of manufacturing methods)
Next, another example of the method for manufacturing the semiconductor element shown in FIG. 1 will be described. In this case, as shown in FIG. 4, after the Ni plating layer 8 is formed, the plating resist film 11 is peeled off. However, since the plating resist film 11 in this case is for forming only the Ni plating layer 8, the thickness does not need to be increased as shown in FIG. The thickness depends on the thickness.

  Next, when the above mixed solution is used as an etchant and the Ni plating layer 8 is used as a mask and the base metal layer forming layer composed of the Cu layer 7b and the Ni—Ti layer 7a is patterned by one etching, as shown in FIG. Then, the base metal layer 7 composed of the Ni—Ti layer 7 a and the Cu layer 7 b is formed under the Ni plating layer 8. Therefore, also in this case, the number of etching steps can be reduced.

  Next, although not shown, when a solder ball is mounted on the upper surface of the Ni plating layer 8 by a solder ball mounting method and undergoes a reflow process and a dicing process, a plurality of semiconductor elements shown in FIG. 1 are obtained.

(Second Embodiment)
FIG. 10 is a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor element is different from the semiconductor element shown in FIG. 1 in that the Ni plating layer 8 is not provided and a solder ball 9 is provided on the upper surface of the Cu layer 7b. In this case, although the Ni plating layer 8 is not provided, the Ni—Ti layer 7 a prevents the diffusion of Sn or the like contained in the solder balls 9, so that no trouble is caused. Since the Ni plating layer 8 is generally high in tension, it is preferable not to have the Ni plating layer 8 if there is a possibility of mechanical damage to the silicon substrate 1 depending on the material of the silicon substrate 1. .

(Example of manufacturing method)
Next, an example of a method for manufacturing the semiconductor element shown in FIG. 10 will be described. In this case, in the example of the manufacturing method of the first embodiment, the step of forming the Ni plating layer 8 shown in FIG. 4 is omitted, and the solder layer 13 is formed on the upper surface of the Cu layer 7b in the opening 12 of the plating resist film 11. (See FIG. 5) may be formed directly.

(Other examples of manufacturing methods)
Next, another example of the method for manufacturing the semiconductor element shown in FIG. 10 will be described. In this case, as shown in FIG. 3, after the Ni—Ti layer 7a and the Cu layer 7b are formed, as shown in FIG. 11, the resist film 21 is formed at a predetermined position on the upper surface of the Cu layer 7b on the connection pad 2. The pattern is formed.

  Next, when the above mixed solution is used as an etching solution and the resist film 21 is used as a mask and the base metal layer forming layer composed of the Cu layer 7b and the Ni—Ti layer 7a is patterned by one etching, as shown in FIG. Then, the base metal layer 7 composed of the Ni—Ti layer 7 a and the Cu layer 7 b is formed under the resist film 21. Therefore, also in this case, the number of etching steps can be reduced.

  Next, the resist film 21 is peeled off. Next, although not shown, when a solder ball is mounted on the upper surface of the Cu layer 7b by a solder ball mounting method and subjected to a reflow process and a dicing process, a plurality of semiconductor elements shown in FIG. 10 are obtained.

(Third embodiment)
FIG. 13 is a sectional view of a semiconductor device as a third embodiment of the present invention. This semiconductor element differs from the semiconductor element shown in FIG. 10 in that the solder layer 9 is provided on the upper surface of the base metal layer 7 made of only the Ni—Ti layer 7a, without the Cu layer 7b. Also in this case, the Ni—Ti layer 7a prevents the Sn and the like contained in the solder ball 9 from diffusing, so that no trouble is caused.

(Example of manufacturing method)
Next, an example of a method for manufacturing the semiconductor element shown in FIG. 13 will be described. In this case, after preparing what is shown in FIG. 2, as shown in FIG. 14, the sputtering method or the like is applied to the entire upper surface of the protective film 5 including the upper surface of the connection pad 2 exposed through both openings 4 and 6. Thus, the Ni—Ti layer 7a is formed to a thickness of about 600 nm.

  Next, a plating resist film 31 is formed on the upper surface of the Ni—Ti layer 7a. In this case, an opening 32 is formed in the plating resist film 31 in a portion corresponding to the base metal layer 7 formation region shown in FIG. Next, the solder layer 13 for forming solder balls is formed on the upper surface of the Ni-Ti layer 7a in the opening 32 of the plating resist film 31 by performing electrolytic plating of solder using the Ni-Ti layer 7a as a plating current path. To do. Next, the plating resist film 31 is peeled off.

  Next, when the mixed liquid is used as an etchant and the base metal layer forming layer made of the Ni—Ti layer 7a is etched and patterned using the solder layer 13 as a mask, as shown in FIG. A base metal layer 7 composed only of the Ni—Ti layer 7a is formed. Therefore, also in this case, the number of etching steps can be reduced. Next, through a reflow process and a dicing process, a plurality of semiconductor elements shown in FIG. 13 are obtained.

(Other examples of manufacturing methods)
Next, another example of the method for manufacturing the semiconductor element shown in FIG. 10 will be described. In this case, after preparing the one shown in FIG. 2, as shown in FIG. 16, the entire upper surface of the protective film 5 including the upper surface of the connection pad 2 exposed through both openings 4 and 6 is sputtered. Thus, the Ni—Ti layer 7a is formed to a thickness of about 600 nm. Next, a resist film 33 is formed in a pattern at a predetermined position on the upper surface of the Ni—Ti layer 7 a on the connection pad 2.

  Next, when the mixed liquid is used as an etchant and the resist film 33 is used as a mask and the base metal layer forming layer made of the Ni—Ti layer 7a is etched and patterned, as shown in FIG. A base metal layer 7 composed only of the Ni—Ti layer 7a is formed. Therefore, also in this case, the number of etching steps can be reduced.

  Next, the resist film 33 is peeled off. Next, although not shown, when a solder ball is mounted on the upper surface of the base metal layer 7 made of only the Ni—Ti layer 7a by a solder ball mounting method and subjected to a reflow process and a dicing process, the semiconductor element shown in FIG. Are obtained.

(Fourth embodiment)
FIG. 18 is a sectional view of a semiconductor device as a fourth embodiment of the present invention. This semiconductor element is greatly different from the semiconductor element shown in FIG. 1 in that it has a structure including a wiring 42 including a base metal layer 41, a columnar electrode 43, a sealing film 44, and a solder ball 45.

That is, the wiring 42 including the base metal layer 41 is provided on the upper surface of the protective film 5 so as to be connected to the connection pad 2 via the openings 4 and 6 of the insulating film 3 and the protective film 5. In this case, the base metal layer 41 is composed of a lower Ni—Ti layer 41a and an upper Cu layer 41b. A wiring 42 made of Cu plating is provided on the entire upper surface of the base metal layer 41.

  A columnar electrode 43 made of Cu plating is provided on the upper surface of the connection pad portion of the wiring 42. A sealing film 44 made of epoxy resin or the like is provided on the upper surface of the protective film 5 including the wiring 42 so that the upper surface is flush with the upper surface of the columnar electrode 43. A solder ball 45 is provided on the upper surface of the columnar electrode 43.

(Production method)
Next, an example of a method for manufacturing a semiconductor device will be described with reference to FIG. In this case, after preparing what is shown in FIG. 2, as shown in FIG. 19, the sputtering method or the like is applied to the entire upper surface of the protective film 5 including the upper surface of the connection pad 2 exposed through both openings 4 and 6. Thus, the Ni—Ti layer 41a and the Cu layer 41b are continuously formed. Also in this case, as an example, the thickness of the Ni—Ti layer 41a is about 600 nm, and the thickness of the Cu layer 41b is about 300 nm.

  Next, a plating resist film 51 is patterned on the upper surface of the Cu layer 41b. In this case, an opening 52 is formed in the plating resist film 51 in a portion corresponding to the wiring 42 formation region. Next, by performing Cu electroplating using the Cu layer 41 b as a plating current path, the wiring 42 is formed on the upper surface of the Cu layer 41 b in the opening 52 of the plating resist film 51. Next, the plating resist film 51 is peeled off.

  Next, as shown in FIG. 20, a plating resist film 53 is patterned on the upper surface of the Cu layer 41 b including the wiring 20. In this case, an opening 54 is formed in the plating resist film 53 in a portion corresponding to the columnar electrode 43 formation region. Next, by performing Cu electrolytic plating using the Cu layer 41 b as a plating current path, the columnar electrode 43 is formed on the upper surface of the connection pad portion of the wiring 42 in the opening 54 of the plating resist film 53.

  Next, the plating resist film 53 is peeled off. Next, when the above mixed solution is used as an etching solution and the wiring layer 42 is used as a mask and the base metal layer forming layer composed of the Cu layer 41b and the Ni—Ti layer 41a is patterned by one etching, as shown in FIG. A base metal layer 41 composed of a Ni—Ti layer 41a and a Cu layer 41b is formed under the wiring. Therefore, also in this case, the number of etching steps can be reduced.

  Next, as shown in FIG. 22, a sealing film 44 made of epoxy resin or the like is formed on the entire upper surface of the protective film 5 including the columnar electrode 43 by screen printing, spin coating, die coating, or the like. It is formed to be thicker than the height of the columnar electrode 43. Therefore, in this state, the upper surface of the columnar electrode 43 is covered with the sealing film 44.

  Next, the upper surface side of the sealing film 44 and the columnar electrode 43 is appropriately polished to expose the upper surface of the columnar electrode 43 and to include the exposed upper surface of the columnar electrode 43 as shown in FIG. The upper surface of the stop film 44 is flattened. Here, the reason why the upper surface side of the columnar electrode 43 is appropriately polished is that there is a variation in the height of the columnar electrode 43 formed by electrolytic plating, so this variation is eliminated and the height of the columnar electrode 43 is made uniform. It is to make it.

  Next, a solder ball is mounted on the upper surface of the columnar electrode 43 by a solder ball mounting method, and after a reflow process, a solder ball 45 is formed on the upper surface of the columnar electrode 43 as shown in FIG. Next, the lower surface of the silicon substrate 1 is attached to a dicing tape (not shown), and after the dicing step shown in FIG. 25, the semiconductor substrate 1 is peeled off from the dicing tape, whereby a plurality of semiconductor elements shown in FIG. 18 are obtained.

(Other embodiments)
In the first to third embodiments, a Cu plating layer may be formed instead of the Ni plating layer 8. In each of the above embodiments, the case where the protective film 5 made of polyimide resin or the like is provided on the upper surface of the insulating film 3 made of silicon nitride or the like has been described. However, the present invention is not limited thereto, and the protective film 5 is not provided. Is also applicable.

1 is a cross-sectional view of a semiconductor element as a first embodiment of the present invention. Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor element shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of a predetermined | prescribed process in the other example of the manufacturing method of the semiconductor element shown in FIG. Sectional drawing of the semiconductor element as 2nd Embodiment of this invention. Sectional drawing of a predetermined | prescribed process in the other example of the manufacturing method of the semiconductor element shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the semiconductor element as 3rd Embodiment of this invention. Sectional drawing of a predetermined | prescribed process in an example of the manufacturing method of the semiconductor element shown in FIG. FIG. 15 is a sectional view of a step following FIG. 14. Sectional drawing of a predetermined | prescribed process in the other example of the manufacturing method of the semiconductor element shown in FIG. FIG. 17 is a cross-sectional view of the process following FIG. 16. Sectional drawing of the semiconductor element as 4th Embodiment of this invention. FIG. 19 is a cross-sectional view of a predetermined step in the example of the method for manufacturing the semiconductor element shown in FIG. FIG. 20 is a cross-sectional view of the process following FIG. 19. FIG. 21 is a cross-sectional view of the process following FIG. 20. FIG. 22 is a sectional view of a step following FIG. 21. FIG. 23 is a sectional view of a step following FIG. 22; FIG. 24 is a sectional view of a step following FIG. 23. FIG. 25 is a sectional view of a step following FIG. 24.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Insulating film 5 Protective film 7 Base metal layer 7a Ni-Ti layer 7b Cu layer 8 Ni plating layer 9 Solder ball 41 Base metal layer 41a Ni-Ti layer 41b Cu layer 42 Wiring 43 Columnar electrode 44 Sealing Stop film 45 Solder ball

Claims (15)

In a semiconductor element in which solder balls are provided on a base metal layer provided on a semiconductor substrate,
The semiconductor substrate is provided with a protective film exposing a connection pad and at least a part of the connection pad,
The base metal layer is provided on and in contact with the connection pad and the protective film,
The base metal layer is composed of at least a Ni—Ti layer and a Cu layer, and is formed by patterning the Ni—Ti layer and the Cu layer by one etching. .   2. The semiconductor element according to claim 1, wherein the Ti content of the Ni—Ti layer is 6.5 to 10 wt%. 3. The semiconductor element according to claim 1 , wherein a plated layer made of Ni or Cu is provided between the Cu layer and the solder ball. In the invention according to any one of claims 1 to 3, wherein the connection pad has an Al, the protective film, a semiconductor device characterized by having a polyimide resin. In the invention of any one of claims 1-4, wherein the base metal layer is a base metal layer for wiring provided to be connected to the connection pad provided on the upper surface of the semiconductor substrate, the underlying metal A wiring is provided on the layer, a columnar electrode is provided on a connection pad portion of the wiring, a sealing film is provided on the semiconductor substrate around the columnar electrode, and the solder ball is provided on the columnar electrode. A semiconductor element characterized in that it is formed. 6. The semiconductor element according to claim 5 , wherein the wiring and the columnar electrode are made of Cu plating. In a method for manufacturing a semiconductor element in which solder balls are provided on a base metal layer provided on a semiconductor substrate,
The semiconductor substrate is provided with a protective film that exposes at least a part of the connection pad and the connection pad,
Forming at least a Ni-Ti layer and a Cu layer on the connection pad and the protective film on the semiconductor substrate to form a base metal layer forming layer including the Ni-Ti layer and the Cu layer ; A method of manufacturing a semiconductor element, wherein the base metal layer forming layer is patterned by one etching to form the base metal layer in contact with the connection pad and the protective film, respectively. 8. The method of manufacturing a semiconductor device according to claim 7 , wherein the Ti content of the Ni—Ti layer is 6.5 to 10 wt%. In the invention of claim 7 or 8, the etching solution used in etching the underlying metal layer forming layer is characterized acetate, hydrogen peroxide water, nitric acid, it is a mixture of pure water semiconductor Device manufacturing method. In the invention of claim 9, wherein the etchant acid 5 wt%, hydrogen peroxide water 1 wt%, nitric acid 10 wt%, a method of manufacturing a semiconductor device which is a mixture of pure water 84 wt%. In the invention according to any one of claims 7 to 10 ,
Forming a plating resist film having an opening in a portion corresponding to the connection pad on the Cu layer;
Forming a plating layer on the Cu layer in the opening of the plating resist film by electrolytic plating of Ni or Cu using the Cu layer as a plating current path;
Forming a solder layer on the plating layer in the opening of the plating resist film by electrolytic plating of solder using the Cu layer as a plating current path;
Removing the plating resist film;
A step of patterning the Cu layer and the Ni—Ti layer by a single etching using the solder layer as a mask to form a base metal layer made of a Ni—Ti layer and a Cu layer under the solder layer. When,
Forming solder balls on the underlying metal layer by reflowing the solder layer;
A method for manufacturing a semiconductor device, comprising: In the invention according to any one of claims 7 to 10 ,
Forming a plating resist film having an opening in a portion corresponding to the connection pad on the Cu layer;
Forming a plating layer on the Cu layer in the opening of the plating resist film by electrolytic plating of Ni or Cu using the Cu layer as a plating current path;
Removing the plating resist film;
Patterning the Cu layer and the Ni—Ti layer by a single etching using the plating layer as a mask to form a base metal layer comprising the Ni—Ti layer and the Cu layer under the plating layer;
Forming solder balls on the underlying metal layer;
A method for manufacturing a semiconductor device, comprising: In the invention according to any one of claims 7 to 10 ,
Forming a plating resist film having an opening in a portion corresponding to the connection pad on the Cu layer;
Forming a solder layer on the Cu layer in the opening of the plating resist film by electrolytic plating of solder using the Cu layer as a plating current path;
Removing the plating resist film;
Patterning the Cu layer and the Ni—Ti layer by one-time etching using the solder layer as a mask to form a base metal layer composed of the Ni—Ti layer and the Cu layer under the solder layer;
Forming solder balls on the underlying metal layer by reflowing the solder layer;
A method for manufacturing a semiconductor device, comprising: In the invention according to any one of claims 7 to 10 ,
Forming a resist film on the Cu layer on the connection pad;
Patterning the Cu layer and the Ni-Ti layer by a single etching using the resist film as a mask to form a base metal layer composed of a Ni-Ti layer and a Cu layer under the resist film;
Removing the resist film;
Forming solder balls on the underlying metal layer;
A method for manufacturing a semiconductor device, comprising: In the invention according to any one of claims 7 to 10 ,
Forming a wiring on the Cu layer by electrolytic plating of Cu;
Forming a columnar electrode on the connection pad portion of the wiring by electrolytic plating of Cu;
Patterning the Cu layer and the Ni-Ti layer by one-time etching using the wiring as a mask to form a base metal layer composed of a Ni-Ti layer and a Cu layer under the wiring;
Forming a sealing film on the protective film around the columnar electrode;
Forming solder balls on the columnar electrodes;
A method for manufacturing a semiconductor device, comprising:

Images