JP4937623B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- JP4937623B2 JP4937623B2 JP2006090441A JP2006090441A JP4937623B2 JP 4937623 B2 JP4937623 B2 JP 4937623B2 JP 2006090441 A JP2006090441 A JP 2006090441A JP 2006090441 A JP2006090441 A JP 2006090441A JP 4937623 B2 JP4937623 B2 JP 4937623B2
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- 239000004065 semiconductor Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 229910000679 solder Inorganic materials 0.000 claims description 56
- 239000010410 layer Substances 0.000 claims description 47
- 239000012792 core layer Substances 0.000 claims description 38
- 230000004888 barrier function Effects 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 239000011347 resin Substances 0.000 claims description 32
- 229920005989 resin Polymers 0.000 claims description 32
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 15
- 229910001080 W alloy Inorganic materials 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 13
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 9
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 6
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 6
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 239000000908 ammonium hydroxide Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000007747 plating Methods 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 235000011118 potassium hydroxide Nutrition 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 235000011121 sodium hydroxide Nutrition 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
本発明は半導体装置の製造方法に関し、とくにコア層と半田層からなる突起電極を形成する方法に関する。 The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a protruding electrode including a core layer and a solder layer.
コア層と半田層からなる突起電極を形成する方法として、たとえば特許文献１の製造方法が提案されている。
特許文献１の突起電極の製造方法は、半導体基板の電極パッドを開口するように絶縁膜をパターニングする。つぎに半導体基板の全面にチタンタングステン合金からなるバリアメタルと銅からなる電極下地膜を順次形成する。その後、感光性樹脂を全面に形成し、電極パッド領域上の電極下地膜が露出する開口を形成するように感光性樹脂をパターニングする。つぎに、電極下地膜をメッキ電極として使用するメッキ処理により感光性樹脂開口内の電極下地膜上にコア層と半田層を形成する。半田層は感光性樹脂の膜厚以上に形成すると、メッキ被膜は等方的に形成され断面形状がマッシュルーム形状となる。つぎに半田層を溶融させるリフロー処理を行なう。その後、感光性樹脂を除去し、さらに電極下地膜とバリアメタルとをエッチングしてコア層に整合した領域に残すようにパターニングする。
As a method for forming a protruding electrode composed of a core layer and a solder layer, for example, a manufacturing method of Patent Document 1 has been proposed.
In the method for manufacturing the protruding electrode of Patent Document 1, the insulating film is patterned so as to open the electrode pad of the semiconductor substrate. Next, a barrier metal made of a titanium tungsten alloy and an electrode base film made of copper are sequentially formed on the entire surface of the semiconductor substrate. Thereafter, a photosensitive resin is formed on the entire surface, and the photosensitive resin is patterned so as to form an opening through which the electrode base film on the electrode pad region is exposed. Next, a core layer and a solder layer are formed on the electrode base film in the photosensitive resin opening by plating using the electrode base film as a plating electrode. When the solder layer is formed to have a thickness greater than that of the photosensitive resin, the plating film is formed isotropically and the cross-sectional shape becomes a mushroom shape. Next, a reflow process for melting the solder layer is performed. Thereafter, the photosensitive resin is removed, and further, the electrode base film and the barrier metal are etched and patterned so as to remain in a region aligned with the core layer.
特許文献１の製造方法によれば、感光性樹脂の残渣発生がなく突起電極が均一に形成され、そのため突起電極高さが揃い実装ばらつきのない、突起電極が得られるという利点を有する。 According to the manufacturing method of Patent Document 1, there is an advantage that a protruding electrode can be obtained in which the protruding electrode is uniformly formed without generation of a residue of the photosensitive resin, and thus the protruding electrode has the same height and no mounting variation.
しかしながら、特許文献１では感光性樹脂が剥離できないという不具合が発生する。特許文献１では、前述のように、半田層を溶融した後、感光性樹脂を剥離する製造方法を採用している。
鉛を含まない半田層、たとえば錫と銀との合金からなる半田層を溶融させるには、温度２６０℃程度に加熱する必要がある。この温度雰囲気にさらされることにより、感光性樹脂は変質し、炭化してしまう。炭化した感光性樹脂は剥離液で剥離することは不可能となる。炭化して剥離できない感光性樹脂がエッチングマスクとして作用し、電極下地膜とバリアメタルをコア層に整合した領域のみにパターニングすることができない。
この結果、突起電極間の領域にも電極下地膜とバリアメタルとが残存し、隣接する突起電極どうしが短絡してしまうという問題点が発生する。
However, in patent document 1, the malfunction that the photosensitive resin cannot be peeled occurs. In Patent Document 1, as described above, a manufacturing method is employed in which the photosensitive resin is peeled after the solder layer is melted.
In order to melt a solder layer not containing lead, for example, a solder layer made of an alloy of tin and silver, it is necessary to heat to a temperature of about 260 ° C. By being exposed to this temperature atmosphere, the photosensitive resin is altered and carbonized. The carbonized photosensitive resin cannot be peeled off with the stripping solution. The photosensitive resin that cannot be carbonized and peeled off acts as an etching mask, and the electrode base film and the barrier metal cannot be patterned only in the region aligned with the core layer.
As a result, the electrode base film and the barrier metal remain in the region between the protruding electrodes, causing a problem that adjacent protruding electrodes are short-circuited.
本発明の目的は上記の不都合を解決して、感光性樹脂を剥離でき、隣接する突起電極どうしの短絡発生がない半導体装置の製造方法を提供することである。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-described inconveniences and that can remove a photosensitive resin and does not cause a short circuit between adjacent protruding electrodes.
上記目的を達成するために、本発明の半導体装置の製造方法においては、半導体基板の電極パッドが開口するように絶縁膜をパターニングし、全面にチタンタングステン合金からなるバリアメタルと電極下地膜を形成し、電極パッド上の電極下地膜が露出する開口を有する感光性樹脂を形成する工程と、感光性樹脂の開口内の電極下地膜上にコア層と半田層を形成する工程と、感光性樹脂を除去し、電極下地膜をエッチングしてコア層に整合した領域に電極下地膜をパターニングする工程と、加熱処理を行ない半田層を溶融させる工程と、過酸化水素からなるエッチャントによってウエットエッチングして前記コア層に整合した領域に前記バリアメタルをパターニングする工程とを、この順序で行うことを特徴とする。 In order to achieve the above object, in the method of manufacturing a semiconductor device of the present invention, an insulating film is patterned so that an electrode pad of a semiconductor substrate is opened, and a barrier metal made of a titanium tungsten alloy and an electrode base film are formed on the entire surface. Forming a photosensitive resin having an opening through which the electrode base film on the electrode pad is exposed, forming a core layer and a solder layer on the electrode base film in the opening of the photosensitive resin, and photosensitive resin And etching the electrode base film to pattern the electrode base film in a region aligned with the core layer, performing a heat treatment to melt the solder layer, and wet etching with an etchant made of hydrogen peroxide. The step of patterning the barrier metal in the region aligned with the core layer is performed in this order .
本発明の半導体装置の製造方法では、感光性樹脂の開口内の電極下地膜上にコア層と半田層を形成する工程と、感光性樹脂を除去し、電極下地膜をエッチングしてコア層に整合した領域に電極下地膜をパターニングする工程と、加熱処理を行ない半田層を溶融させるリフロー工程と、バリアメタルをエッチングしてコア層に整合した領域にバリアメタルをパターニングする工程とを有する。
本発明の製造方法では、半田層のリフロー工程前に感光性樹脂を剥離し除去している。このため感光性樹脂は高温雰囲気にさらされることはなく、感光性樹脂を剥離液で剥離でき、電極下地膜とバリアメタルのエッチング残りが生じることはない。この結果、隣接する突起電極どうしが短絡することは発生しない。
In the method for manufacturing a semiconductor device of the present invention, a step of forming a core layer and a solder layer on the electrode base film in the opening of the photosensitive resin, and removing the photosensitive resin and etching the electrode base film into the core layer There are a step of patterning the electrode base film in the aligned region, a reflow step of performing a heat treatment to melt the solder layer, and a step of patterning the barrier metal in the region aligned with the core layer by etching the barrier metal.
In the manufacturing method of the present invention, the photosensitive resin is peeled and removed before the solder layer reflow process. For this reason, the photosensitive resin is not exposed to a high-temperature atmosphere, and the photosensitive resin can be peeled off with a peeling solution, so that no etching residue of the electrode base film and the barrier metal occurs. As a result, short circuit between adjacent protruding electrodes does not occur.
以下、図面を使用して本発明の実施形態における半導体装置の製造方法を説明する。図１から図６は本発明の実施形態における半導体装置の製造方法を工程順に示す断面図である。 Hereinafter, a semiconductor device manufacturing method according to an embodiment of the present invention will be described with reference to the drawings. 1 to 6 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
はじめに図１に示すように、半導体基板１２上のアルミニウムからなるとともに入出力端子となる電極パッド１４が露出するように絶縁膜１６に開口部を形成する。この絶縁膜１６は酸化シリコン膜や窒化シリコン膜などの無機絶縁膜、またはポリイミド膜などの有機絶縁膜が適用可能である。 First, as shown in FIG. 1, an opening is formed in the insulating film 16 so that the electrode pad 14 made of aluminum on the semiconductor substrate 12 and serving as an input / output terminal is exposed. The insulating film 16 can be an inorganic insulating film such as a silicon oxide film or a silicon nitride film, or an organic insulating film such as a polyimide film.
その後、半導体基板１２上の全面にバリアメタル１７と電極下地膜１８をスパッタリング装置を用いて順次形成する。スパッタリング装置によるバリアメタル１７と電極下地膜１８の形成は、好ましくは減圧雰囲気中で連続して形成し、両被膜間に酸化膜が形成されないようにする。バリアメタル１７と電極下地膜１８を減圧雰囲気中で連続して形成すると、両被膜の密着性が良好となる。
バリアメタル１７は、チタンが５重量％から２０重量％を含み残りがタングステンとするチタンタングステン合金からなり、厚さ０．１μｍ〜０．５μｍで形成する。また電極下地膜１８は、銅からなり、厚さ０．２μｍ〜１μｍで形成する。バリアメタル１７と電極下地膜１８は電極パッド１４と突起電極との接続層の役割と相互拡散を防ぐバリヤ層の役割をもつとともに、コア層と半田層をメッキ法にて形成するときのメッキ電極としての役割ももつ。電極下地膜１８は銅以外にニッケルや、金や、パラジウムや、モリブデン被膜、あるいはこれらの被膜の合金膜も適用可能である。
Thereafter, a barrier metal 17 and an electrode base film 18 are sequentially formed on the entire surface of the semiconductor substrate 12 using a sputtering apparatus. The barrier metal 17 and the electrode base film 18 are preferably formed continuously in a reduced pressure atmosphere by a sputtering apparatus so that an oxide film is not formed between the two films. When the barrier metal 17 and the electrode base film 18 are continuously formed in a reduced-pressure atmosphere, the adhesion between the two films is improved.
The barrier metal 17 is made of a titanium-tungsten alloy containing 5% to 20% by weight of titanium and the rest being tungsten, and is formed with a thickness of 0.1 μm to 0.5 μm. The electrode base film 18 is made of copper and has a thickness of 0.2 μm to 1 μm. The barrier metal 17 and the electrode base film 18 have a role of a connection layer between the electrode pad 14 and the protruding electrode and a role of a barrier layer for preventing mutual diffusion, and a plating electrode when the core layer and the solder layer are formed by a plating method. Also has a role. As the electrode base film 18, nickel, gold, palladium, molybdenum coating, or an alloy film of these coatings can be applied in addition to copper.
その後、電極下地膜１８上の全面に回転塗布法により感光性樹脂２０を形成し、フォトリソグラフィー技術によりコア層と半田層形成領域が開口するように感光性樹脂２０をパターニングする。 Thereafter, the photosensitive resin 20 is formed on the entire surface of the electrode base film 18 by a spin coating method, and the photosensitive resin 20 is patterned by the photolithography technique so that the core layer and the solder layer forming region are opened.
つぎに図２に示すように、感光性樹脂２０開口内の電極下地膜１８上に銅をメッキ法により成長させ、コア層２２を形成する。このコア層２２は５μｍ〜２５μｍの厚さで形成する。コア層２２を感光性樹脂２０の膜厚以上に形成すると、メッキ被膜は等方的に成長し、断面形状はマッシュルーム形状となる。
コア層２２は半田からなる半田層と電極下地膜１８との相互拡散を防ぐ役割をもつ。さらにコア層２２は半田層と機械的および電気的に接合する役割も有し、コア層２２は半田との濡れ性が良好な材料を選択する。コア層２２としては銅以外に、ニッケルや、ニッケル合金も適用可能であるが、メッキ形成のしやすさやコスト的に銅が好ましい。
またコア層２２は、半田層とコア層２２からなる突起電極を形成した半導体装置と、回路基板とを実装するとき、半導体装置と回路基板との間のギャップ寸法を制御する役割ももち、ギャップ寸法に対応してコア層２２のメッキ厚さを調整すればよい。
Next, as shown in FIG. 2, copper is grown by plating on the electrode base film 18 in the opening of the photosensitive resin 20 to form the core layer 22. The core layer 22 is formed with a thickness of 5 μm to 25 μm. When the core layer 22 is formed to have a thickness greater than that of the photosensitive resin 20, the plating film grows isotropically and the cross-sectional shape becomes a mushroom shape.
The core layer 22 has a role of preventing mutual diffusion between the solder layer made of solder and the electrode base film 18. Furthermore, the core layer 22 also has a role of mechanically and electrically joining to the solder layer, and the core layer 22 is selected from a material having good wettability with the solder. In addition to copper, nickel or a nickel alloy can also be used as the core layer 22, but copper is preferable in terms of ease of plating formation and cost.
The core layer 22 also has a role of controlling the gap size between the semiconductor device and the circuit board when the semiconductor device on which the protruding electrode composed of the solder layer and the core layer 22 is formed and the circuit board are mounted. Corresponding to the above, the plating thickness of the core layer 22 may be adjusted.
つぎに図３に示すように、電極下地膜１８をメッキ電極とするメッキ法により、コア層２２上に半田からなる半田層２４を形成する。半田層２４は、前述の半導体装置と回路基板との実装時に、回路基板の回路パターンに濡れ広がって電気的および機械的な接合する役割をもち、厚さ２０μｍ〜４０μｍ形成する。半田層２４は錫と銀からなる。 Next, as shown in FIG. 3, a solder layer 24 made of solder is formed on the core layer 22 by plating using the electrode base film 18 as a plating electrode. The solder layer 24 has a role of being electrically and mechanically bonded to the circuit pattern of the circuit board when the semiconductor device and the circuit board are mounted, and has a thickness of 20 μm to 40 μm. The solder layer 24 is made of tin and silver.
つぎに図４に示すように、コア層２２と半田層２４のメッキ処理におけるメッキ阻止膜として使用した感光性樹脂２０を、レジスト剥離液に浸漬して剥離する。本発明の製造方法では、感光性樹脂２０は高温雰囲気にさらされておらず、レジスト剥離液で残渣が発生することなく完全に感光性樹脂２０を剥離できる。
その後、銅被膜からなる電極下地膜１８を、リン酸を主成分とするエッチング液を用いるウェットエッチングによりパターニングする。前述のように感光性樹脂２０は完全に剥離され残渣発生がないことから、電極下地膜１８はコア層２２に整合した領域のみに形成するようパターニングできる。
Next, as shown in FIG. 4, the photosensitive resin 20 used as a plating prevention film in the plating process of the core layer 22 and the solder layer 24 is immersed in a resist stripping solution and stripped. In the production method of the present invention, the photosensitive resin 20 is not exposed to a high temperature atmosphere, and the photosensitive resin 20 can be completely removed without generating a residue in the resist stripping solution.
Thereafter, the electrode base film 18 made of a copper film is patterned by wet etching using an etchant containing phosphoric acid as a main component. As described above, since the photosensitive resin 20 is completely peeled and no residue is generated, the electrode base film 18 can be patterned so as to be formed only in a region aligned with the core layer 22.
つぎに図５に示すように、半導体基板１２の半田層２４形成した側の全面にフラックスを塗布して、加熱処理を行ない半田を溶融させる。前述のように半田層２４は錫と銀からなり、温度２６０℃に加熱する。溶融した半田は表面張力で丸まりコア層２２表面に球状の半田層２４を形成できる。この結果、半田層２４の半田は銅からなるコア層２２に濡れ半田層２４とコア層２２の機械的および電気的接合は良好となる。またコア層２２の断面形状がマッシュルーム形状となっており、コア層２２の外縁部はひさし状に張り出しているため、半田はコア層２２の上面だけに濡れる。
なお、このときチタンタングステン合金からなるバリアメタル１７が電極下地膜１８形成領域以外の全面で露出しているが、チタンタングステン合金は半田との濡れ性は悪く、半田層２４がバリアメタル１７に濡れ広がることは発生しない。したがって、半田層２４の半田量の変化は発生せず、突起電極の高さばらつきはない。
Next, as shown in FIG. 5, a flux is applied to the entire surface of the semiconductor substrate 12 where the solder layer 24 is formed, and heat treatment is performed to melt the solder. As described above, the solder layer 24 is made of tin and silver and is heated to a temperature of 260 ° C. The molten solder is rounded by surface tension, and a spherical solder layer 24 can be formed on the surface of the core layer 22. As a result, the solder of the solder layer 24 gets wet with the core layer 22 made of copper, and the mechanical and electrical connection between the solder layer 24 and the core layer 22 becomes good. Further, the cross-sectional shape of the core layer 22 is a mushroom shape, and the outer edge portion of the core layer 22 projects in an eaves shape, so that the solder gets wet only on the upper surface of the core layer 22.
At this time, the barrier metal 17 made of titanium tungsten alloy is exposed on the entire surface other than the region where the electrode base film 18 is formed. However, the titanium tungsten alloy has poor wettability with the solder, and the solder layer 24 gets wet with the barrier metal 17. Spreading does not occur. Therefore, the solder amount of the solder layer 24 does not change and there is no variation in the height of the protruding electrodes.
つぎに図６に示すように、チタンタングステン合金からなるバリアメタル１７を、過酸化水素をエッチャントとするウェットエッチングにより、コア層２２に整合する領域にパターニングする。
本発明の製造方法においては、半田層２４のリフロー処理を行なったのち、バリアメタル１７のエッチング処理を行なうことにより、バリアメタル１７のエッチング残渣の発生がなくなる。この理由を以下詳しく説明する。
Next, as shown in FIG. 6, the barrier metal 17 made of a titanium tungsten alloy is patterned in a region aligned with the core layer 22 by wet etching using hydrogen peroxide as an etchant.
In the manufacturing method of the present invention, the etching residue of the barrier metal 17 is eliminated by performing the etching process of the barrier metal 17 after the reflow processing of the solder layer 24. The reason will be described in detail below.
メッキにより形成した半田層２４は錫と銀とは合金化されておらず、半田層２４の表面に錫が偏析している。錫が偏析している状態で過酸化水素を用いてチタンタングステン合金からなるバリアメタル１７をエッチングすると、過酸化水素中の酸素と半田層２４表面の錫とが反応して、錫の酸化物がバリアメタル１７の表面に生成される。錫の酸化物は過酸化水素ではエッチングできず、錫の酸化物がエッチングマスクとなってバリアメタル１７が残存する。
このため半田層２４を溶融していない状態で、バリアメタル１７のエッチング処理を行なうとバリアメタル１７は完全にエッチングされず、残存したバリアメタル１７によって、隣接する突起電極どうしが短絡するという問題点が発生する。
The solder layer 24 formed by plating is not alloyed with tin and silver, and tin is segregated on the surface of the solder layer 24. When the barrier metal 17 made of a titanium-tungsten alloy is etched using hydrogen peroxide in a state where the tin is segregated, oxygen in the hydrogen peroxide reacts with tin on the surface of the solder layer 24, so that the oxide of tin is changed. It is generated on the surface of the barrier metal 17. Tin oxide cannot be etched with hydrogen peroxide, and the barrier metal 17 remains using the tin oxide as an etching mask.
For this reason, if the etching process of the barrier metal 17 is performed in a state where the solder layer 24 is not melted, the barrier metal 17 is not completely etched, and the adjacent barrier metal 17 causes a short circuit between adjacent protruding electrodes. Occurs.
これに対して本発明の製造方法では、半田層２４をリフロー処理して溶融させたのち、チタンタングステン合金からなるバリアメタル１７を、過酸化水素によりパターニングしている。
半田層２４を溶融させると錫と銀とは合金化され、表面に錫が偏析することはなく、過酸化水素を用いたバリアメタル１７のエッチングにおいて、錫の酸化物は生成されず、バリアメタル１７はエッチング残りが発生することなく、完全にエッチング除去できる。したがって、本発明の製造方法においては隣接する突起電極どうしが短絡するという問題点は発生しない。
On the other hand, in the manufacturing method of the present invention, after the solder layer 24 is reflowed and melted, the barrier metal 17 made of a titanium tungsten alloy is patterned with hydrogen peroxide.
When the solder layer 24 is melted, tin and silver are alloyed so that tin does not segregate on the surface, and in the etching of the barrier metal 17 using hydrogen peroxide, no oxide of tin is generated. 17 can be completely removed without etching. Therefore, in the manufacturing method of the present invention, there is no problem that adjacent protruding electrodes are short-circuited.
なお、本発明では銅からなる電極下地膜１８をエッチングしてから半田層２４のリフロー処理を行なっており、電極下地膜１８のエッチング処理前に半田層２４のリフロー処理を行なっていない。この製造方法を採用する理由は、半田層２４をリフローするとき、銅からなる電極下地膜１８は半田との濡れ性がよく、半田層２４が電極下地膜１８に濡れ広がり、半田層２４の半田量のばらつきが発生し、突起電極高さの均一性が得られなくなることを防止するためである。 In the present invention, the solder layer 24 is reflowed after the electrode base film 18 made of copper is etched, and the solder layer 24 is not reflowed before the electrode base film 18 is etched. The reason for adopting this manufacturing method is that when the solder layer 24 is reflowed, the electrode base film 18 made of copper has good wettability with the solder, and the solder layer 24 wets and spreads over the electrode base film 18, so that the solder of the solder layer 24 This is to prevent variation in the amount and the unevenness of the height of the protruding electrode cannot be obtained.
この結果、半田層２４とコア層２２からなる突起電極を、電極下地膜１８とバリアメタル１７を介して電極パッド１４上に形成することができる。
なお、チタンタングステン合金からなるバリアメタル１７のエッチャントである過酸化水素にペーハー（ｐＨ）を調整するために、水酸化アンモニウムを添加してもよい。過酸化水素と水酸化アンモニウムからなるエッチャントを用いると、エッチングの進行が緩やかになり、エッチャントの突沸現象がなくなり、半導体基板１２の割れや欠けの発生を防止できる。また水酸化アンモニウムの代わりに、アンモニア水や水酸化ナトリウムや水酸化カリウムを過酸化水素水に添加してチタンタングステン合金からなるバリアメタル１７をエッチングしても良い。
As a result, the protruding electrode composed of the solder layer 24 and the core layer 22 can be formed on the electrode pad 14 via the electrode base film 18 and the barrier metal 17.
In order to adjust pH (pH) to hydrogen peroxide which is an etchant of the barrier metal 17 made of titanium tungsten alloy, ammonium hydroxide may be added. When an etchant composed of hydrogen peroxide and ammonium hydroxide is used, the progress of etching becomes slow, and the bumping phenomenon of the etchant is eliminated, thereby preventing the semiconductor substrate 12 from being cracked or chipped. Further, instead of ammonium hydroxide, ammonia water, sodium hydroxide, or potassium hydroxide may be added to hydrogen peroxide water to etch the barrier metal 17 made of a titanium tungsten alloy.
１２ 半導体基板
１４ 電極パッド
１６ 絶縁膜
１７ バリアメタル
１８ 電極下地膜
２０ 感光性樹脂
２２ コア層
２４ 半田層
DESCRIPTION OF SYMBOLS 12 Semiconductor substrate 14 Electrode pad 16 Insulating film 17 Barrier metal 18 Electrode base film 20 Photosensitive resin 22 Core layer 24 Solder layer
Claims (3)
前記感光性樹脂の開口内の前記電極下地膜上にコア層と半田層を形成する工程と、
前記感光性樹脂を除去し、前記電極下地膜をエッチングして前記コア層に整合した領域に前記電極下地膜をパターニングする工程と、
加熱処理を行ない前記半田層を溶融させる工程と、
前記バリアメタルを過酸化水素からなるエッチャントによってウエットエッチングして前記コア層に整合した領域に前記バリアメタルをパターニングする工程とを、
この順序で行うことを特徴とする半導体装置の製造方法。 The insulating film is patterned so as to open the electrode pad of the semiconductor substrate, the barrier metal made of titanium tungsten alloy and the electrode base film are formed on the entire surface, and the photosensitive having the opening through which the electrode base film on the electrode pad is exposed Forming a resin;
Forming a core layer and a solder layer on the electrode base film in the opening of the photosensitive resin;
Removing the photosensitive resin, etching the electrode base film, and patterning the electrode base film in a region aligned with the core layer;
Performing a heat treatment to melt the solder layer;
Patterning the barrier metal in a region aligned with the core layer by wet etching the barrier metal with an etchant comprising hydrogen peroxide ;
A method of manufacturing a semiconductor device, which is performed in this order .
The etchant comprising hydrogen peroxide is hydrogen peroxide, an etchant obtained by adding ammonium hydroxide to hydrogen peroxide, or an etchant obtained by adding ammonia water, sodium hydroxide, or potassium hydroxide to hydrogen peroxide. A method for manufacturing a semiconductor device according to claim 1.
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