CN107204312A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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CN107204312A
CN107204312A CN201610756197.0A CN201610756197A CN107204312A CN 107204312 A CN107204312 A CN 107204312A CN 201610756197 A CN201610756197 A CN 201610756197A CN 107204312 A CN107204312 A CN 107204312A
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semiconductor element
ground terminal
face
sealing resin
resin layer
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岩本正次
山崎尚
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

本发明的实施方式提供一种能够抑制电磁波障碍的半导体装置及其制造方法。实施方式的半导体装置的制造方法具备：将被处理体与工辅具以接地端子插入于第一沟槽且信号端子插入于第二沟槽，并且一表面相接于第一面的方式重叠配置的步骤，该被处理体具备：半导体元件；密封树脂层，密封半导体元件；及接地端子及信号端子，与半导体元件电性连接，从密封树脂层的一表面突出，且该接地端子能够与接地电位连接；该工辅具具备：第一面；第二面；第一沟槽，从第一面至第二面为止连续性地露出；及第二沟槽，在第一面露出；及以覆盖密封树脂层的露出部及接地端子的露出部的方式形成导电性屏蔽层而将导电性屏蔽层与接地端子之间电性连接的步骤。

Description

半导体装置的制造方法及半导体装置
[相关申请案]
本申请案享有以日本专利申请案2016-53322号(申请日：2016年3月17日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
实施方式的发明涉及半导体装置的制造方法及半导体装置。
背景技术
作为电子零件之一，周知的是插入安装型的半导体装置。插入安装型的半导体装置具有被密封树脂层密封的半导体元件、及从密封树脂层突出的接地用端子及信号用端子等外部连接端子。将该外部连接端子插入于例如搭载用衬底的插入部而将半导体装置与搭载用衬底电性连接。
在将所述半导体装置用于例如通讯设备等的情况下，为了抑制EMI(ElectroMagnetic Interference，电磁干扰)等电磁波障碍，而使用以导电性屏蔽层覆盖密封树脂层的表面的构造。为了以所述构造获得充分的屏蔽效果，优选将导电性屏蔽层电性连接于接地端子。
发明内容
本发明的实施方式提供能够抑制电磁波障碍的半导体装置及其制造方法。
实施方式的半导体装置的制造方法具备：将被处理体与工辅具以接地端子插入于第一沟槽且信号端子插入于第二沟槽，并且一表面相接于第一面的方式重叠配置的步骤，该被处理体具备：半导体元件；密封树脂层，密封半导体元件；及接地端子及信号端子，与半导体元件电性连接，从密封树脂层的一表面突出，且该接地端子能够与接地电位连接；该工辅具具备：第一面；第二面；第一沟槽，从第一面至第二面为止连续性地露出；及第二沟槽，在第一面露出；及以覆盖密封树脂层的露出部及接地端子的露出部的方式形成导电性屏蔽层而将导电性屏蔽层与接地端子之间电性连接的步骤。
附图说明
图1是用以说明配置步骤的示意图。
图2是用以表示被处理体的构成例的示意图。
图3是用以说明屏蔽步骤的示意图。
图4是用以说明保护层形成步骤的示意图。
具体实施方式
以下，参照图式对实施方式进行说明。图式中记载的各构成要素的厚度与平面尺寸的关系、各构成要素的厚度的比率等存在与实物不同的情况。此外，在实施方式中，对实质上相同的构成要素附上相同的符号并适当地省略说明。
作为半导体装置的制造方法例，对作为单列直插式封装(SIP，Single InlinePackage)的插入安装型的半导体装置的制造方法例进行说明。半导体装置的制造方法例具备配置步骤、及屏蔽步骤。
图1是用以说明配置步骤的示意图。在配置步骤中，如图1所示般，将被处理体10与工辅具20以重叠的方式配置，且搬送至例如进行屏蔽步骤的处理室内。
对被处理体10进行说明。被处理体10为插入安装型的半导体零件，例如为场效晶体管、调节器等离散半导体。并非限定于离散半导体，被处理体10也可为例如仅在密封树脂层的一表面具有多个外部连接端子的其他插入安装型的半导体零件。
图2是表示被处理体10的构成例的示意图。图2所示的被处理体10具备：衬底1，具有外部连接端子1a至1c；半导体元件3；接合线4；及密封树脂层5。
作为衬底1，使用例如引线框架。作为引线框架，列举使用例如铜、铜合金、或42合金等铁与镍的合金等的引线框架等。
外部连接端子1a至1c从密封树脂层5的一表面即面5a(也称为外部连接端子1a至1c的突出面)突出。图2所示的外部连接端子1a至1c例如沿与面5a垂直的方向延伸，但并不限定于此。外部连接端子1a至1c也可在表面具有含有锡等的焊料镀敷层。通过具有焊料镀敷层，可抑制例如外部连接端子1a至1c的氧化。
外部连接端子1a具有作为例如接地端子的功能。此处接地端子是指在将半导体装置与其他电子零件连接时连接于接地电位的预定的能够连接于接地电位的端子。外部连接端子1b具有作为例如输入信号端子的功能。外部连接端子1c具有作为例如输出信号端子的功能。在被处理体10为例如场效晶体管的情况下，外部连接端子1a电性连接于源极及漏极的一者，外部连接端子1b电性连接于栅极，外部连接端子1b电性连接于源极及漏极的另一者。另外，外部连接端子的数量及位置并不限定于图1及图2。外部连接端子1a至1c的位置也可相互调换。此外，也可进而设置有具有作为电源端子的功能的外部连接端子。
也可使用配线衬底作为衬底1。配线衬底具有例如设置在第一面上的包含第一至第三连接焊垫的多个连接焊垫。第一连接焊垫电性连接于例如接地配线。第二连接焊垫电性连接于例如输入信号配线。第三连接焊垫电性连接于例如输出信号配线。外部连接端子1a电性连接于第一连接焊垫，外部连接端子1b电性连接于第二连接焊垫，外部连接端子1c电性连接于第三连接焊垫。
半导体元件3搭载在衬底1上。半导体元件3经由多个接合线4而与外部连接端子1a至外部连接端子1c的各者电性连接。作为半导体元件3，使用例如半导体芯片等。另外，半导体元件3也可具有多个半导体芯片的积层体。作为接合线4，列举例如金线、银线、铜线等。铜线的表面也可被钯膜覆盖。
密封树脂层5以密封半导体元件3的方式设置。此外，通过密封树脂层5而将接合线4、半导体元件3与外部连接端子1a至1c的各者之间的连接部密封。密封树脂层5为具有包含例如面5a的外周面的长方体。密封树脂层5含有SiO2等无机填充材。无机填充材为例如粒状，具有调整密封树脂层5的粘度或硬度等的功能。密封树脂层5中的无机填充材的含量为例如60％以上且90％以下。作为密封树脂层5，能够使用例如无机填充材与绝缘性的有机树脂材料的混合物。作为有机树脂材料，列举例如环氧树脂。
对工辅具20进行说明。工辅具20具备：外周面，包含面21a与面21b；沟槽22a；沟槽22b；及沟槽22c。工辅具20使用例如金属材料或树脂材料等形成。
面21a设置在例如工辅具20的上表面。面21b设置在例如工辅具20的侧面。沟槽22a在面21a露出，且在工辅具20的厚度方向具有特定的深度。此外，沟槽22a具有从面21a至面21b为止连续性地露出的露出部201。沟槽22b及沟槽22c的各者在面21a露出且在工辅具20的厚度方向具有特定的深度。沟槽22a至22c的深度或宽度根据外部连接端子1a至1c的长度或宽度而设计。
在配置步骤中，将被处理体10与工辅具20以如下方式重叠配置，即，将外部连接端子1a插入于沟槽22a，将外部连接端子1b插入于沟槽22b，将外部连接端子1c插入于沟槽22c，并且密封树脂层5的面5a相接于工辅具20的面21a。此时，外部连接端子1a的一部分在露出部201露出。相对于此，外部连接端子1b及外部连接端子1c被密封树脂层5及工辅具20覆盖。
图3是用以说明屏蔽步骤的截面示意图。在屏蔽步骤中，如图3所示般，在密封树脂层5的外周面的露出部及露出部201中的外部连接端子1a的露出部形成导电性屏蔽层7。此时，外部连接端子1a的露出部与密封树脂层5的外周面的露出部连续，因此能够与形成导电性屏蔽层7同时地将外部连接端子1a与导电性屏蔽层7之间电性连接。
导电性屏蔽层7覆盖密封树脂层5的除面5a以外的外周面，且以与在屏蔽步骤中露出的外部连接端子1a的一部分相接的方式经由面5a延伸。当在外部连接端子1a的全体形成导电性屏蔽层7时，会对将半导体装置搭载于衬底时的焊料步骤等产生影响，因此优选仅在外部连接端子1a的一部分形成导电性屏蔽层7。此外，由于外部连接端子1b及1c被工辅具20覆盖，因此未在外部连接端子1b及1c的表面形成导电性屏蔽层7。由此，导电性屏蔽层7与外部连接端子1b及1c隔开且电性分离。
导电性屏蔽层7具有将从半导体元件3等辐射的多余的电磁波阻断而抑制电磁波向外部泄漏的功能。通过将外部连接端子1a与导电性屏蔽层7之间电性连接，而能够使多余的电磁波经由外部连接端子1a逃散至外部。
导电性屏蔽层7优选包含例如铜、镍、钛、金、银、钯、铂、铁、铝、锡或铬等金属、所述金属的合金、不锈钢、或铟锡氧化物(Indium Tin Oxide：ITO)等。通过使用例如铜，能够降低导电性屏蔽层7的电阻率。导电性屏蔽层7也可具有所述材料的复合层或积层。导电性屏蔽层7通过例如溅镀而形成。除溅镀以外，也可使用例如蒸镀法、喷雾法、无电解镀敷等镀敷处理等。
导电性屏蔽层7的厚度优选基于其电阻率而设定。例如，优选以将导电性屏蔽层7的电阻率除以厚度所得的薄片电阻值成为0.5Ω以下的方式设定导电性屏蔽层7的厚度。通过使导电性屏蔽层7的薄片电阻值为0.5Ω以下，能够再现性佳地抑制来自密封树脂层5的多余的电磁波的泄漏。导电性屏蔽层7的厚度优选为例如0.1μm以上且20μm以下。在未达0.1μm的情况下，存在屏蔽效果降低的情况。在超过20μm的情况下，存在导电性屏蔽层7的应力较大而导电性屏蔽层7剥离的情况。在通过溅镀等形成导电性屏蔽层7的情况下，与面5a相接的区域存在较其他区域薄的情况。
在本实施方式的半导体装置的制造方法中，使用具有在多个面连续性地露出的沟槽的工辅具，以覆盖密封树脂层并且延伸至具有作为接地端子的功能的外部连接端子的一部分为止的方式，形成导电性屏蔽层而将接地端子与导电性屏蔽层之间电性连接。
在插入安装型的半导体装置中，将外部连接端子以从密封树脂层突出的方式设置。因此，在不使用工辅具20而通过溅镀或镀敷处理等所述方法形成导电性屏蔽层的情况下，有也在除接地端子以外的外部连接端子形成导电性屏蔽层的一部分而短路的情况。该情况下，为了不在除接地端子以外的外部连接端子形成导电性屏蔽层，必需进行遮蔽等步骤。
在本实施方式的半导体装置的制造方法中，一面将具有作为信号端子的功能的外部连接端子以工辅具覆盖一面形成导电性屏蔽层。由此，能够在屏蔽步骤中抑制除接地端子以外的外部连接端子与导电性屏蔽层的短路。此外，能够与形成导电性屏蔽层同时地将导电性屏蔽层与接地端子之间电性连接。由此，能够抑制步骤数的增加。另外，也可使用具有多个在多个面连续性地露出的沟槽的工辅具对多个被处理体在同一步骤形成导电性屏蔽层。
本实施方式的半导体装置的制造方法也可具备在所述配置步骤之前形成被处理体10的步骤(被处理体形成步骤)。在被处理体形成步骤中，被处理体10的形成方法具备衬底准备步骤、搭载步骤、树脂密封步骤、分离步骤、及镀敷步骤。
衬底准备步骤是准备具有外部连接端子1a至1c的衬底1的步骤。搭载步骤为如下步骤，即，在衬底1上搭载半导体元件3，将半导体元件3与外部连接端子1a之间电性连接，将半导体元件3与外部连接端子1b之间电性连接，且将半导体元件3与外部连接端子1c之间电性连接。在搭载步骤中，进行将半导体元件3与外部连接端子1a至1c的各者之间通过接合线4电性连接的打线。进而，在搭载步骤中，也可在搭载半导体元件3之后进行加热处理。
密封步骤为如下步骤，即，以将衬底1、半导体元件3、半导体元件3与外部连接端子1a之间的连接部、半导体元件3与外部连接端子1b之间的连接部、及半导体元件3与外部连接端子1c之间的连接部密封的方式形成密封树脂层5。作为密封树脂层5的形成方法，列举例如使用无机填充材与有机树脂等的混合物的转注成形法、压缩成形法、射出成形法、片状模塑法、或树脂分配法等。
镀敷步骤是在外部连接端子1a至1c的表面的露出部实施镀敷处理而形成焊料镀敷层的步骤。在镀敷步骤中，使用包含例如锡等的焊料材料进行电镀等镀敷加工。另外，也可进行刻印制品名等制品信息的标记步骤。通过在标记步骤后进行屏蔽步骤而能够使所刻印的文字的视认性提高。以上为被处理体形成步骤的说明。
本实施方式的半导体装置的制造方法也可具备在屏蔽步骤之后形成保护层的步骤。图4是用以说明保护层形成步骤的截面示意图。在保护层形成步骤中，如图4所示般，在导电性屏蔽层7上形成保护层8。此时，保护层8的一部分也可相接于外部连接端子1a的一部分。
保护层8的耐腐蚀性及耐迁移性优异，具有例如使导电性屏蔽层7的耐湿性提高而抑制导电性屏蔽层7的腐蚀的功能。作为保护层8，使用例如金属材料、树脂材料、陶瓷材料等。保护层8包含例如钛、铬、镍、铁、铝、钼、钽、锰、镧或铜等金属、或不锈钢、所述金属的氧化物、所述金属的氮化物、ITO、碳、石墨、类钻碳、ZrB、MoS、TiON、TiAlN、环氧树脂、聚酰亚胺树脂、丙烯酸系树脂、硅酮树脂、聚酰胺树脂等。保护层8也可使用例如能够适用于导电性屏蔽层7的形成的方法而形成。
所述实施方式是作为例而提示的，并未意图限定发明的范围。这些新颖的实施方式能以其他各种方式实施，能够在不脱离发明的要旨的范围进行各种省略、替换、变更。这些实施方式及其变化包含在发明的范围及要旨中，并且包含在权利要求书中所记载的发明及其均等的范围。
[符号的说明]
1：衬底
1a：外部连接端子
1b：外部连接端子
1c：外部连接端子
3：半导体元件
4：接合线
5：密封树脂层
5a：面
7：导电性屏蔽层
8：保护层
10：被处理体
20：工辅具
21a：面
21b：面
22a：沟槽
22b：沟槽
22c：沟槽
201：露出部

Claims (5)

1.一种半导体装置的制造方法，其特征在于具备：
将被处理体与工辅具以所述接地端子插入于所述第一沟槽，所述信号端子插入于所述第二沟槽，并且所述一表面相接于所述第一面的方式重叠配置的步骤，该被处理体具备：半导体元件；密封树脂层，密封所述半导体元件；接地端子，与所述半导体元件电性连接，且从所述密封树脂层的一表面突出，能够与接地电位连接；及信号端子，与所述半导体元件电性连接，且从所述一表面突出；该工辅具具备：第一面；第二面；第一沟槽，从所述第一面至所述第二面为止连续性地露出；及第二沟槽，在所述第一面露出；及
以覆盖所述密封树脂层的露出部及所述接地端子的露出部的方式，形成导电性屏蔽层而将所述导电性屏蔽层与所述接地端子之间电性连接的步骤。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于进而具备如下步骤，即，在配置所述被处理体与所述工辅具的步骤之前形成所述被处理体，且
形成所述被处理体的步骤包含：
在具有所述接地端子与所述信号端子的衬底上搭载半导体元件，将所述半导体元件与所述接地端子之间电性连接，且将所述半导体元件与所述信号端子之间电性连接的步骤；
以将所述半导体元件、所述半导体元件与所述接地端子之间的连接部、及所述半导体元件与所述信号端子之间的连接部密封的方式形成所述密封树脂层的步骤；及
在所述接地端子及所述信号端子的露出部实施镀敷处理而形成镀敷层的步骤。
3.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
所述导电性屏蔽层通过溅镀、喷雾法、蒸镀法、或镀敷处理而形成。
4.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
所述半导体装置为单列直插式封装。
5.一种半导体装置，其特征在于具备：
半导体元件；
密封树脂层，密封所述半导体元件；
接地端子，与所述半导体元件电性连接，且从所述密封树脂层的一表面突出；
信号端子，与所述半导体元件电性连接，且从所述一表面突出；及
导电性屏蔽层，以一方面覆盖所述密封树脂层的除所述一表面以外的面，一方面相接于所述接地端子的一部分的方式经由所述一表面而延伸，且与所述信号端子隔开。
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Application publication date: 20170926