CN107180834B - 半导体存储装置及其制造方法 - Google Patents
半导体存储装置及其制造方法 Download PDFInfo
- Publication number
- CN107180834B CN107180834B CN201710065811.3A CN201710065811A CN107180834B CN 107180834 B CN107180834 B CN 107180834B CN 201710065811 A CN201710065811 A CN 201710065811A CN 107180834 B CN107180834 B CN 107180834B
- Authority
- CN
- China
- Prior art keywords
- memory device
- semiconductor memory
- insulating member
- electrodes
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Landscapes
- Engineering & Computer Science (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
Abstract
Description
Claims (19)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662307087P | 2016-03-11 | 2016-03-11 | |
US62/307,087 | 2016-03-11 | ||
US15/263,464 US10403636B2 (en) | 2016-03-11 | 2016-09-13 | Semiconductor memory device and method for manufacturing the same |
US15/263,464 | 2016-09-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107180834A CN107180834A (zh) | 2017-09-19 |
CN107180834B true CN107180834B (zh) | 2021-11-26 |
Family
ID=59788031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710065811.3A Active CN107180834B (zh) | 2016-03-11 | 2017-02-06 | 半导体存储装置及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10403636B2 (zh) |
CN (1) | CN107180834B (zh) |
TW (1) | TWI645549B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019121717A (ja) | 2018-01-09 | 2019-07-22 | 東芝メモリ株式会社 | 半導体記憶装置 |
JP6976190B2 (ja) * | 2018-02-20 | 2021-12-08 | キオクシア株式会社 | 記憶装置 |
JP2019153612A (ja) * | 2018-02-28 | 2019-09-12 | 東芝メモリ株式会社 | 半導体記憶装置 |
JP2019165132A (ja) * | 2018-03-20 | 2019-09-26 | 東芝メモリ株式会社 | 半導体記憶装置及びその製造方法 |
JP2019220534A (ja) * | 2018-06-18 | 2019-12-26 | キオクシア株式会社 | 半導体記憶装置およびその製造方法 |
US10763431B2 (en) * | 2018-11-16 | 2020-09-01 | International Business Machines Corporation | Film stress control for memory device stack |
JP2020150147A (ja) | 2019-03-14 | 2020-09-17 | キオクシア株式会社 | 半導体記憶装置 |
JP2021028950A (ja) | 2019-08-09 | 2021-02-25 | キオクシア株式会社 | 半導体記憶装置 |
JP2021034591A (ja) | 2019-08-26 | 2021-03-01 | キオクシア株式会社 | 半導体装置およびその製造方法 |
JP2021048302A (ja) * | 2019-09-19 | 2021-03-25 | キオクシア株式会社 | 半導体記憶装置 |
JP2021150296A (ja) * | 2020-03-16 | 2021-09-27 | キオクシア株式会社 | 半導体記憶装置 |
JP2021150524A (ja) * | 2020-03-19 | 2021-09-27 | キオクシア株式会社 | 半導体記憶装置 |
JP2022147748A (ja) | 2021-03-23 | 2022-10-06 | キオクシア株式会社 | 半導体記憶装置 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105374825A (zh) * | 2014-08-13 | 2016-03-02 | 爱思开海力士有限公司 | 半导体器件及其制造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2933802B1 (fr) | 2008-07-10 | 2010-10-15 | Commissariat Energie Atomique | Structure et procede de realisation d'un dispositif microelectronique de memoire 3d de type flash nand. |
JP2010080685A (ja) | 2008-09-26 | 2010-04-08 | Toshiba Corp | 不揮発性記憶装置及びその製造方法 |
JP2011023464A (ja) * | 2009-07-14 | 2011-02-03 | Toshiba Corp | 半導体記憶装置 |
US20120064682A1 (en) * | 2010-09-14 | 2012-03-15 | Jang Kyung-Tae | Methods of Manufacturing Three-Dimensional Semiconductor Memory Devices |
KR101760658B1 (ko) * | 2010-11-16 | 2017-07-24 | 삼성전자 주식회사 | 비휘발성 메모리 장치 |
KR20140024632A (ko) * | 2012-08-20 | 2014-03-03 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 및 그 제조 방법 |
KR102054181B1 (ko) * | 2013-02-26 | 2019-12-10 | 삼성전자주식회사 | 수직형 메모리 장치 및 그 제조 방법 |
US8933457B2 (en) | 2013-03-13 | 2015-01-13 | Macronix International Co., Ltd. | 3D memory array including crystallized channels |
KR20140137632A (ko) * | 2013-05-23 | 2014-12-03 | 에스케이하이닉스 주식회사 | 반도체 장치 |
KR102130558B1 (ko) | 2013-09-02 | 2020-07-07 | 삼성전자주식회사 | 반도체 장치 |
JP2015133458A (ja) | 2014-01-16 | 2015-07-23 | 株式会社東芝 | 不揮発性半導体記憶装置 |
-
2016
- 2016-09-13 US US15/263,464 patent/US10403636B2/en not_active Expired - Fee Related
-
2017
- 2017-01-25 TW TW106102821A patent/TWI645549B/zh not_active IP Right Cessation
- 2017-02-06 CN CN201710065811.3A patent/CN107180834B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105374825A (zh) * | 2014-08-13 | 2016-03-02 | 爱思开海力士有限公司 | 半导体器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN107180834A (zh) | 2017-09-19 |
TW201807812A (zh) | 2018-03-01 |
US10403636B2 (en) | 2019-09-03 |
TWI645549B (zh) | 2018-12-21 |
US20170263634A1 (en) | 2017-09-14 |
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Legal Events
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PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo Patentee after: Kaixia Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. Address after: Tokyo Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo Patentee before: Pangea Co.,Ltd. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20220209 Address after: Tokyo Patentee after: Pangea Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |