CN107170717A - 半导体装置封装和其制造方法 - Google Patents
半导体装置封装和其制造方法 Download PDFInfo
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- CN107170717A CN107170717A CN201710123452.2A CN201710123452A CN107170717A CN 107170717 A CN107170717 A CN 107170717A CN 201710123452 A CN201710123452 A CN 201710123452A CN 107170717 A CN107170717 A CN 107170717A
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Abstract
本揭露提供半导体装置封装,包含一封装衬底、一第一电子装置、一第二电子装置及一第一模封层。所述封装衬底包含一第一表面、相对于所述第一表面的一第二表面以及一边缘。所述第一电子装置位于所述封装衬底上方且通过所述第一表面电连接至所述封装衬底。所述第二电子装置位于所述第一电子装置上方且电连接至所述第一电子装置。所述第一模封层位于所述封装衬底上方,且所述第一模封层包覆所述第一表面之一部分及所述封装衬底之边缘。
Description
相关申请案的交叉参考
本申请案主张2016年3月8日申请的美国临时申请案第62/305,034号的优先权和益处,所述美国临时申请案的内容以全文引用的方式并入本文中。
技术领域
本发明涉及一种半导体装置封装和其制造方法,且更特定来说,涉及具有多个电子装置(例如经堆叠的多个电子装置)的一种半导体装置封装和其制造方法。
背景技术
具有堆叠式电子装置的半导体装置封装,例如2.5D或3D半导体装置封装,由于其非对称结构和相邻层的物理特性间不匹配而可能翘曲。此外,某些堆叠式半导体装置封装的强度不够。
发明内容
根据本发明的实施例,半导体装置封装包含封装衬底、第一电子装置、第二电子装置和第一模封层。封装衬底包含一第一表面、相对于所述第一表面的一第二表面以及一边缘。第一电子装置位于所述封装衬底上方且通过所述第一表面电连接至所述封装衬底。第二电子装置位于所述第一电子装置上方且电连接至所述第一电子装置。第一模封层位于所述封装衬底上方,且所述第一模封层包覆所述封装衬底的第一表面的一部分及所述封装衬底的边缘。
根据本发明的实施例,半导体装置封装包含封装衬底、第一电子装置、第二电子装置和第一模封层。封装衬底包含一第一表面及相对于所述第一表面的一第二表面。第一电子装置位于所述封装衬底上方且通过所述第一表面电连接至所述封装衬底。第二电子装置位于所述第一电子装置上方且电连接至所述第一电子装置。第一模封层位于所述封装衬底上方,且所述第一模封层包覆所述封装衬底的第一表面的一部分。所述半导体装置封装的一翘曲小于8密耳(毫英寸/mil)。
根据本发明的实施例,半导体装置封装的制造方法包含在一载体上方放置多个第一电子装置、在所述多个第一电子装置上方放置多个第二电子装置以形成多个堆叠结构,其中每一所述多个堆叠结构包含至少一所述第一电子装置和至少一所述第二电子装置、分离所述多个堆叠结构、自所述载体移开所述多个堆叠结构、在一封装衬底上方放置所述堆叠结构、和在所述封装衬底上方形成一第一模封层以包覆所述堆叠结构。
附图说明
由以下详细说明与附随图式得以最佳了解本申请案揭示内容的各方面。注意,根据产业的标准实施方式,各种特征并非依比例绘示。实际上,为了清楚讨论,可任意增大或缩小各种特征的尺寸。
图1A为根据本揭露的一些实施例的半导体装置封装的上视图;
图1B为根据本揭露的一些实施例的半导体装置封装沿线A-A'的剖面图;
图2绘示基于一实验结果,半导体装置封装的翘曲与一第二厚度与一第一厚度的一比间的关系,所述实验于室温下进行;
图3A、3B、3C、3D、3E和3F绘示根据本揭露的一些实施例的半导体装置封装的制造方法;
图4为根据本揭露的一些实施例的半导体装置封装的剖面图;
图5为根据本揭露的一些实施例的半导体装置封装的剖面图;
图6为根据本揭露的一些实施例的半导体装置封装的剖面图;
图7为根据本揭露的一些实施例的半导体装置封装的剖面图;
图8为根据本揭露的一些实施例的半导体装置封装的剖面图;
图9绘示基于一实验结果,半导体装置封装的翘曲与一第二厚度与一第一厚度的一比间的关系,所述实验于室温下进行;
图10A、10B、10C、10D和10E绘示根据本揭露的一些实施例的半导体装置封装的制造方法;
图11为根据本揭露的一些实施例的半导体装置封装的剖面图;
图12为根据本揭露的一些实施例的半导体装置封装的剖面图;
图13为根据本揭露的一些实施例的半导体装置封装的剖面图;和
图14为根据本揭露的一些实施例的半导体装置封装的剖面图。
具体实施方式
本揭露提供了数个不同的实施方法或实施例,可用于实现本发明的不同特征。为简化说明起见,本揭露也同时描述了特定零组件与布置的范例。请注意提供这些特定范例的目的仅在于示范,而非予以任何限制。举例来说,在以下说明第一特征如何在第二特征上或上方的叙述中,可能会包含某些实施例,其中第一特征与第二特征为直接接触,而叙述中也可能包含其它不同实施例,其中第一特征与第二特征中间另有其它特征,以致于第一特征与第二特征并不直接接触。此外,本揭露中的各种范例可能使用重复的参考数字和/或文字注记,以使文件更加简单化和明确,这些重复的参考数字与注记不代表不同的实施例与配置之间的关联性。
另外,本揭露在使用与空间相关的叙述词汇,如“在…之上”、“在…之下”、“上”、“左”、“右”、“下”、“顶”、“底”、“垂直”、“水平”、“侧”、“较高”、“较低”、“较下方”、“较上方”、“上方”、“下方”、和类似词汇时,为便于叙述,其用法均在于描述图示中一个元件或特征与另一个(或多个)元件或特征的相对关系。除了图示中所显示的角度方向外,这些空间相对词汇也用来描述所述装置在使用中以及操作时的可能角度和方向。所述装置的角度方向可能不同,而在本揭露所使用的这些空间相关叙述可以同样方式加以解释。
下文叙述一种半导体装置封装。在一些实施例中,半导体装置封装包含一堆栈结构和一模封层。所述堆栈结构放置或位于一封装衬底上方且电连接至所述封装衬底。所述模封层包覆所述封装衬底的一边缘。此可增强半导体装置封装的坚固性(robustness)。下文也叙述一种较不易展现翘曲和/或相较于其他半导体装置封装而言倾向展现较少翘曲的半导体装置封装。下文也叙述一种半导体装置封装的制造方法。
图1A为根据本揭露的一些实施例的半导体装置封装1的上视图,且图1B为根据本揭露的一些实施例的半导体装置封装1沿线A-A'的剖面图。如图1A和图1B所示,半导体装置封装1包括封装衬底10、一或多个第一电子装置20、一或多个第二电子装置30和一第一模封层42。封装衬底10包含一第一表面101、相对于所述第一表面101的一第二表面102以及一边缘10E。边缘10E可为,例如,一表面或一表面的一部分和/或一侧壁或一侧壁的一部分。第一电子装置20位于封装衬底10上方且通过所述第一表面101电连接至所述封装衬底10。第二电子装置30位于所述第一电子装置20上方且电连接至所述第一电子装置20。第一模封层42位于所述封装衬底10上方,且所述第一模封层42包覆所述封装衬底10的第一表面101的一部分及所述封装衬底10的边缘10E的至少一部分。
在一些实施例中,封装衬底10为包括一或多层具有形成于其内部的线和/或导通孔的衬底,其可提供第一表面101和第二表面102间的导电路径。在一些实施例中,封装衬底10包括电路板,例如印刷电路板、半导体衬底或其等同物。
在一些实施例中,第一电子装置20可包括但不限于贯穿(penerating)和/或穿过(traversing)第一电子装置20的通孔(through via)22,且第二电子装置30通过第一电子装置20的通孔22电连接至封装衬底10。例如,第一电子装置20包括中介板(interposer),例如硅中介板,其具有贯穿所述中介板的硅通孔。在一些实施例中,半导体装置封装1还包括第一导电结构24,其位于所述封装衬底10与第一电子装置20间且电连接至封装衬底10及第一电子装置20。在一些实施例中,第一导电结构24可包括导电凸块,例如焊料凸块、锡球、锡膏或其组合或等同物。
在一些实施例中,第一电子装置20包括但不限于有源装置(例如专用IC(ASIC))、存储器装置(例如高带宽存储器(HBM)装置或另一有源装置),和/或无源装置(例如电容器、电感器、电阻器或等同物)。在一些实施例中,半导体装置封装1还包括第二导电结构32,其位于第一电子装置20与第二电子装置30之间且电连接至第一电子装置20和第二电子装置30。在一些实施例中,第二导电结构32可包括导电凸块,例如焊料凸块、锡球、锡膏或其组合或等同物。在一些实施例中,第二导电结构32位于第一电子装置20的第一接合垫21与第二电子装置30的第二接合垫31之间且电连接至第一电子装置20的第一接合垫21和第二电子装置30的第二接合垫31。
第一模封层42的材料包括但不限于模塑料(例如环氧树脂或等同物),以及填充物(例如模塑料中的氧化硅填充物)。第一模封层42包覆封装衬底10的边缘10E,这可改进半导体装置封装1的坚固性,使其增强。在一些实施例中,第一模封层42进一步包覆第一电子装置20的一部分,以及第二电子装置30的一部分,这可有助于保护第一电子装置20和第二电子装置30。在一些实施例中,第一模封层42进一步包覆第一电子装置20的上表面20U和侧壁20S,以及第二电子装置30的上表面30U和侧壁30S。
在一些实施例中,半导体装置封装1还包括第一填胶层52,例如毛细填胶(CUF),其位于封装衬底10与第一电子装置20之间。在一些实施例中,半导体装置封装1还包括第二填胶层54,例如毛细填胶,其第一电子装置20与第二电子装置30之间。在一些实施例中,半导体装置封装1还包括位于封装衬底10的第二表面102下方且电连接至封装衬底10的第二表面102的导体50。在一些实施例中,导体50包含导电凸块,例如焊料凸块、锡球、锡膏或其它导电结构。在一些实施例中,导体50通过封装衬底10电连接至第一电子装置20。在一些实施例中,导体50经配置以允许半导体装置封装1外部连接至外部电子装置。
封装衬底10具有从第一表面101至第二表面102测量的第一厚度t1。第一模封层42具有从封装衬底10的第一表面101至第一模封层42的上表面42U测量的第二厚度t2。在一些实施例中,第二厚度t2与第一厚度t1的比小于或等于约0.7、小于或等于约0.6,或小于或等于约0.5。
在一些实施例中,半导体装置封装1的翘曲小于8密耳,其中1密耳对应于0.001英寸。在一些实施例中,第一模封层42的热膨胀系数(CTE)在低于其转变温度(Tg)的温度范围内,大致上在从约5ppm/℃至约50ppm/℃的范围内。在一些实施例中,第一模封层42的CTE在低于其转变温度的温度范围内,大致上在从约10ppm/℃至约45ppm/℃的范围内、大致上在从约15ppm/℃至约40ppm/℃的范围内、大致上在从约20ppm/℃至约35ppm/℃的范围内,或大致上在从约25ppm/℃至约30ppm/℃的范围内。在一些实施例中,第一模封层42的杨氏模量在低于其转变温度的温度范围内,大致上在从约12GPa至约24GPa的范围内,且在高于其转变温度的温度范围内,大致上在从约0.3GPa至约0.6GPa的范围内。
表1列出在实验中用作第一模封层的材料的三种不同模封材料,其具有所列出的杨氏模量(E)、CTE(α)、转变温度(Tg)和泊松比(V)。
表1
材料类型 | E(GPa) | α(ppm/℃) | Tg(℃) | v |
模封材料A | 24<Tg<0.3 | 10/40 | 131 | 0.30 |
模封材料B | 12<Tg<0.45 | 21/73 | 160 | 0.30 |
模封材料C | 12<Tg<0.6 | 30/81 | 160 | 0.30 |
图2说明基于实验结果,半导体装置封装1的翘曲与半导体装置封装1的第二厚度和第一厚度的比(t2/t1)间的关系,所述实验于室温下进行。测试装置1使用模封材料A作为第一模封层;测试装置2使用模封材料B作为第一模封层;测试装置3使用模封材料C作为第一模封层。测试装置1、2和3各自具有约55mm*约55mm的封装大小,以及约36.02mm*约27.97mm的第一电子装置大小。测试装置4使用模封材料C作为第一模封层。测试装置4具有约47.5mm*约47.5mm的封装大小,以及约27.30mm*约31.35mm的第一电子装置大小。如图2中所展示,半导体装置封装1的翘曲随着t2/t1降低而减小。实验结果展示可通过将t2/t1控制为,例如,小于或等于约0.7,来减轻半导体装置封装1的翘曲。
半导体装置封装1与晶片级芯片规模封装(WLCSP)兼容。第一模封层42围绕封装衬底10的边缘10E,且因此可为半导体装置封装1提供侧壁保护。第一模封层的第二厚度t2和封装衬底10的第一厚度t1可经配置以减轻半导体装置封装1的翘曲。在一些实施例中,第一模封层42的物理特性(例如CTE、杨氏模量和/或转变温度)经配置以进一步减轻半导体装置封装1的翘曲。
图3A、3B、3C、3D、3E和3F说明根据本揭露的一些实施例的半导体装置封装1的制造方法的实例。如图3A中所描绘,在载体70上方放置第一电子装置20。载体70(例如晶片、玻璃衬底或等同物)被配置为用以处置第一电子装置20的暂时性载体。在一些实施例中,使用粘合层72将电子装置20放置于载体70上方。在一些实施例中,粘合层72包括胶带或其它适合的粘合材料。在一些实施例中,第一导电结构24形成于第一电子装置20下方,且电连接至通孔22。在一些实施例中,第一导电结构24是封闭的且受粘合层72支撑。在一些实施例中,第一接合垫21形成于第一电子装置20上方,且电连接至通孔22。在一些实施例中,第二导电结构32形成于第一接合垫21上方。
如图3B中所描绘,在第一电子装置20上方放置第二电子装置30以形成堆叠结构40。每一所述多个堆叠结构40包括至少一所述第一电子装置20和至少一所述第二电子装置30。在一些实施例中,第二接合垫31通过第二导电结构32连接至第一接合垫21,以使得一或多个第二电子装置30电连接至相应第一电子装置20。在一些实施例中,第二导电结构32包含焊料凸块或等同物,且对第二导电结构32执行回焊过程。在一些实施例中,执行清洗过程以清洗助焊剂。
如图3C中所描绘,在第一电子装置20与第二电子装置30之间形成第二填胶层54。在一些实施例中,在第一电子装置20与第二电子装置30之间施配第二填胶层54且接着进行热固化。如图3D中所描绘,分离堆叠结构40,且自载体70移开堆叠结构40。接着在封装衬底10上方放置所分离的堆叠结构40,其包含至少一个第一电子装置20和至少一个第二电子装置30。在一些实施例中,堆叠结构40与封装衬底10通过第一导电结构24连接。在一些实施例中,第一导电结构24包含焊料凸块或等同物,且对第一导电结构24执行回焊过程。在一些实施例中,执行清洗过程以清洗助焊剂。
如图3E中所描绘,在封装衬底10与第一电子装置20之间形成第一填胶层52。在一些实施例中,在封装衬底10与第一电子装置20之间施配第一填胶层52且接着进行热固化。如图3F中所描绘,第一模封层42形成于封装衬底10上方,且包覆封装衬底10的第一表面101的一部分和边缘10E。在一些实施例中,第一模封层42进一步包覆第一电子装置20的一部分,以及第二电子装置30的一部分,且保护第一电子装置20和第二电子装置30。在一些实施例中,在封装衬底10的第二表面102上方形成导体50以完成半导体装置封装1。
本揭露的半导体装置封装和制造方法不限于上述实施例,且可根据其它实施例实施。为简化以下描述且为方便本揭露的各种实施例之间的比较,用与在上文所使用编号相同的编号标记每一以下实施例中的类似于上文所描述的组件的组件,且可省略对那些组件的描述。
图4为根据本揭露的一些实施例的半导体装置封装2的剖面图。如图4中所展示,与对于半导体装置封装1的一些实施例的情况不同的是,通过,例如,磨削使第一模封层42变薄,以暴露第二电子装置30的上表面30U。在一些实施例中,半导体装置封装2还包括具有良好导热率的散热器60,其位于第二电子装置30的上表面30U上方。在一些实施例中,散热器60与所暴露的第二电子装置30接触以提高散热。在一些实施例中,散热器60通过粘合剂粘合到所暴露的第二电子装置30。
图5为根据本揭露的一些实施例的半导体装置封装3的剖面图。如图5中所展示,与对于半导体装置封装1的一些实施例的情况不同的是,省略第一填胶层52。半导体装置封装3的第一模封层42进一步位于封装衬底10与第一电子装置20之间,且被配置为模封填胶(MUF)。在一些实施例中,第一模封层42可暴露第二电子装置30的上表面30U。在一些实施例中,散热器(未示出)可形成于第二电子装置30的上表面30U上方以提高散热能力。
图6为根据本揭露的一些实施例的半导体装置封装4的剖面图。如图6中所展示,与对于半导体装置封装1的一些实施例的情况不同的是,省略第二填胶层54。半导体装置封装4的第一模封层42进一步位于第一电子装置20与第二电子装置30之间,且被配置为模封填胶(MUF)。在一些实施例中,第一模封层42可暴露第二电子装置30的上表面30U。在一些实施例中,散热器(未示出)可形成于第二电子装置30的上表面30U上方以提高散热能力。
图7为根据本揭露的一些实施例的半导体装置封装5的剖面图。如图7中所展示,与对于半导体装置封装1的一些实施例的情况不同的是,省略第一填胶层52和第二填胶层54。半导体装置封装5的第一模封层42进一步位于封装衬底10与第一电子装置20之间以及第一电子装置20与第二电子装置30之间,且被配置为模封填胶(MUF)。在一些实施例中,第一模封层42可暴露第二电子装置30的上表面30U。在一些实施例中,散热器(未示出)可形成于第二电子装置30的上表面30U上方以提高散热能力。
图8为根据本揭露的一些实施例的半导体装置封装6的剖面图。如图8中所展示,与对于半导体装置封装1的一些实施例的情况不同的是,半导体装置封装6还包括位于第一电子装置20上方的第二模封层44。在一些实施例中,第二模封层44包覆第一电子装置20的上表面20U的一部分以及第二电子装置30的上表面30U的一部分和侧壁30S。第二模封层44的材料包括但不限于模塑料(例如环氧树脂或等同物),以及填充物(例如模塑料中的氧化硅填充物)。在一些实施例中,第二模封层44的侧壁44S被第一模封层42围绕。在一些实施例中,第二模封层44的上表面44U与第一模封层42的上表面42U基本上共面。在一些实施例中,第一模封层42和第二模封层44包含相同材料。
在一些实施例中,半导体装置封装6的翘曲小于8密耳。在一些实施例中,第一模封层42和第二模封层44的CTE在低于其转变温度(Tg)的温度范围内,大致上在从约5ppm/℃至约50ppm/℃的范围内。在一些实施例中,第一模封层42和第二模封层44的CTE在低于其转变温度的温度范围内,大致上在从约10ppm/℃至约45ppm/℃的范围内、大致上在从约15ppm/℃至约40ppm/℃的范围内、大致上在从约20ppm/℃至约35ppm/℃的范围内,或大致上在从约25ppm/℃至约30ppm/℃的范围内。在一些实施例中,第一模封层42和第二模封层44的杨氏模量在低于其转变温度的温度范围内,大致上在从约12GPa至约24GPa的范围内,且在高于其转变温度的温度范围内,大致上在从约0.3GPa至约0.6GPa的范围内。
图9说明基于实验结果,半导体装置封装6的翘曲与半导体装置封装6的第二厚度和第一厚度的比(t2/t1)间的关系,所述实验于室温下进行。测试装置5使用模封材料A作为第一模封层,且使用模封材料B作为第二模封层;测试装置6使用模封材料A作为第一模封层,且使用模封材料C作为第二模封层;测试装置7使用模封材料C作为第一模封层,且使用模封材料A作为第二模封层;测试装置8使用模封材料C作为第一模封层,且使用模封材料B作为第二模封层。测试装置5、6、7和8各自具有约55mm*约55mm的封装大小,以及约36.02mm*约27.97mm的第一电子装置大小。测试装置9使用模封材料C作为第一模封层,且使用模封材料A作为第二模封层。测试装置9具有约47.5mm*约47.5mm的封装大小,以及约27.30mm*约31.35mm的第一电子装置大小。如图9中所展示,半导体装置封装6的翘曲随着t2/t1降低而减小。实验结果展示可通过将t2/t1控制为,例如,小于或等于约0.7,来减轻半导体装置封装6的翘曲。
半导体装置封装6与晶片级芯片规模封装(WLCSP)兼容。第一模封层42围绕封装衬底10的边缘10E,且因此可为半导体装置封装6提供侧壁保护。第一模封层的第二厚度t2和封装衬底10的第一厚度t1可经配置以减轻半导体装置封装6的翘曲。在一些实施例中,第一模封层42和第二模封层44的物理特性(例如CTE、杨氏模量和/或转变温度)经配置以减轻半导体装置封装6的翘曲。
图10A、10B、10C、10D和10E说明根据本揭露的一些实施例的半导体装置封装6的制造方法的实例。如图10A中所描绘,在载体70上方放置第一电子装置20。接着,在第一电子装置20上方放置第二电子装置30以形成堆叠结构40。在一些实施例中,在第一电子装置20与第二电子装置30之间形成第二填胶层54。
如图10B中所描绘,在分离堆叠结构40之前,在堆叠结构40上方形成第二模封层44。在一些实施例中,第二模封层44包覆至少一个第一电子装置20的上表面20U的一部分以及至少一个第二电子装置30的上表面30U的一部分和侧壁30S。如图10C中所描绘,分离堆叠结构40,且自载体70移开堆叠结构40。所分离的堆叠结构40包含至少一个第一电子装置20,且接着在封装衬底10上方放置至少一个第二电子装置30。如图10D中所描绘,在封装衬底10与第一电子装置20之间形成第一填胶层52。
如图10E中所描绘,第一模封层42形成于封装衬底10上方,且包覆封装衬底10的第一表面101的一部分和边缘10E。在一些实施例中,第一模封层42围绕第二模封层44的侧壁44S。在一些实施例中,第二模封层44的上表面44U与第一模封层42的上表面42U基本上共面。在一些实施例中,在封装衬底10的第二表面102上方形成导体50,以完成如图8中所展示的半导体装置封装6。
图11为根据本揭露的一些实施例的半导体装置封装7的剖面图。如图11中所展示,与对于半导体装置封装6的一些实施例的情况不同的是,通过,例如,磨削使第二模封层44变薄,以暴露第二电子装置30的上表面30U。在一些实施例中,半导体装置封装7还包括具有良好导热率的散热器60,其位于第二电子装置30的上表面30U上方。在一些实施例中,散热器60与所暴露的第二电子装置30接触以提高散热能力。在一些实施例中,散热器60通过粘合剂粘合到所暴露的第二电子装置30。
图12为根据本揭露的一些实施例的半导体装置封装8的剖面图。如图12中所展示,与对于半导体装置封装6的一些实施例的情况不同的是,省略第一填胶层52。半导体装置封装8的第二模封层44进一步位于封装衬底10与第一电子装置20之间,且被配置为模封填胶(MUF)。在一些实施例中,第二模封层44可暴露第二电子装置30的上表面30U。在一些实施例中,散热器(未示出)可形成于第二电子装置30的上表面30U上方以提高散热能力。
图13为根据本揭露的一些实施例的半导体装置封装9的剖面图。如图13中所展示,与对于半导体装置封装6的一些实施例的情况不同的是,省略第二填胶层54。半导体装置封装9的第二模封层44进一步位于第一电子装置20与第二电子装置30之间,且被配置为模封填胶(MUF)。在一些实施例中,第二模封层44可暴露第二电子装置30的上表面30U。在一些实施例中,散热器(未示出)可形成于第二电子装置30的上表面30U上方以提高散热能力。
图14为根据本揭露的一些实施例的半导体装置封装10的剖面图。如图14中所展示,与对于半导体装置封装6的一些实施例的情况不同的是,省略第一填胶层52和第二填胶层54。半导体装置封装10的第二模封层44进一步位于封装衬底10与第一电子装置20之间以及第一电子装置20与第二电子装置30之间,且被配置为模封填胶(MUF)。在一些实施例中,第二模封层44可暴露第二电子装置30的上表面30U。在一些实施例中,散热器(未示出)可形成于第二电子装置30的上表面30U上方以提高散热能力。
本揭露的各种实施例的半导体装置封装与兼容。经配置以接收电子装置(例如,上面放置有电子装置)的封装衬底的边缘被模封层包覆和保护,且因此增强半导体装置封装的坚固性以防止半导体装置封装被破坏。模封层的厚度和封装衬底的厚度经配置以减轻半导体装置封装的翘曲。模封层的物理特性(例如CTE、杨氏模量和/或转变温度)经配置以减轻半导体装置封装的翘曲。
如本文所用,除非上下文另外明确规定,否则单数术语“一(a/an)”和“所述”可包含复数指示物。
如本文中所使用,术语“导电”、“导电性”和“导电率”是指输送电流的能力。导电性材料通常指示对电流的的流动呈现极少或无对抗的那些材料。电导率的一个度量为西门子/米(S/m)。通常,导电性材料为导电率大于约104S/m(例如至少105S/m或至少106S/m)的材料。材料的导电率有时可随温度变化而变化。除非另外说明,否则在室温下测量材料的导电率。
如本文中所使用,术语“大致”、“基本上”、“大体上”以及“约”用以描述和考量小的变化。当与事件或情形结合使用时,所述术语可指事件或情形明确发生的情况以及事件或情形极近似于发生的情况。举例来说,当结合数值使用时,术语可指小于或等于所述数值的±10%的变化范围,例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%。举例来说,如果两个数值之间的差小于或等于所述值的平均值的±10%(例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%),那么可认为所述两个数值“基本上”相同或相等。举例来说,“基本上”平行可指相对于0°的小于或等于±10°(例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°)的角度变化范围。举例来说,“基本上”垂直可指相对于90°的小于或等于±10°(例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°)的角度变化范围。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm或不大于0.5μm,那么可认为这两个表面是共面的或基本上共面。
另外,有时在本文中按范围格式呈现量、比率和其它数值。应理解,此类范围格式是用于便利和简洁起见,且应灵活地理解,不仅包括明确地指定为范围限制的数值,而且包括涵盖于所述范围内的所有个别数值或子范围,如同明确地指定每一数值和子范围一般。
尽管已参考本揭露的特定实施例描述并说明本揭露,但这些描述和说明并不限制本揭露。所属领域的技术人员应理解,可在不脱离如由所附权利要求书界定的本揭露的真实精神和范围的情况下,作出各种改变且可取代等效物。所述说明可能未必按比例绘制。归因于制造工艺和公差,本揭露中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本揭露的其它实施例。应将本说明书和图式视为说明性的而非限制性的。可做出修改,以使特定情况、材料、物质组成、方法或工艺适应于本揭露的目标、精神和范围。所有此类修改意图在所附权利要求书的范围内。虽然本文中所揭露的方法已参考按特定次序执行的特定操作加以描述,但应理解,可在不脱离本揭露的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此,除非本文中特别指示,否则操作的次序和分组不是对本揭露的限制。
Claims (13)
1.一种半导体装置封装,其包含:
一封装衬底,其包含一第一表面、相对于所述第一表面的一第二表面以及一边缘;
一第一电子装置,其位于所述封装衬底上方且通过所述第一表面电连接至所述封装衬底;
一第二电子装置,其位于所述第一电子装置上方且电连接至所述第一电子装置;和
一第一模封层,其位于所述封装衬底上方,其中所述第一模封层包覆所述封装衬底的第一表面的一部分及所述封装衬底的边缘。
2.根据权利要求1所述的半导体装置封装,其中所述第一电子装置包含多个通孔,且所述第二电子装置通过所述第一电子装置的多个通孔电连接至所述封装衬底。
3.根据权利要求1所述的半导体装置封装,其进一步包含:
多个第一导电结构,其位于所述封装衬底与所述第一电子装置之间且电连接至所述封装衬底和所述第一电子装置;和
多个第二导电结构,其位于所述第一电子装置与所述第二电子装置之间且电连接至所述第一电子装置和所述第二电子装置。
4.根据权利要求1所述的半导体装置封装,其中所述第一模封层进一步包覆所述第一电子装置的一部分及所述第二电子装置的一部分。
5.根据权利要求1所述的半导体装置封装,其进一步包含一第一填胶层,其位于所述封装衬底与所述第一电子装置之间。
6.根据权利要求1所述的半导体装置封装,其进一步包含一第二填胶层,其位于所述第一电子装置与所述第二电子装置之间。
7.根据权利要求1所述的半导体装置封装,其进一步包含位于所述第一电子装置上方的一第二模封层,所述第二模封层包含一侧壁,其中所述第二模封层包覆所述第一电子装置的一部分及所述第二电子装置的一部分,且所述第一模封层围绕所述第二模封层的侧壁。
8.一种半导体装置封装,其包含:
一封装衬底,其包含一第一表面及相对于所述第一表面的一第二表面;
一第一电子装置,其位于所述封装衬底上方且通过所述第一表面电连接至所述封装衬底;
一第二电子装置,其位于所述第一电子装置上方且电连接至所述第一电子装置;和
一第一模封层,其位于所述封装衬底上方,其中所述第一模封层包覆所述封装衬底的第一表面的一部分,
其中所述半导体装置封装的一翘曲小于8密耳。
9.根据权利要求8所述的半导体装置封装,其中所述封装衬底具有一第一厚度,所述第一模封层具有一第二厚度,且所述第二厚度与所述第一厚度的一比小于或等于0.7。
10.根据权利要求8所述的半导体装置封装,其中所述第一模封层的一热膨胀系数(CTE)为从5ppm/℃至50ppm/℃的一范围。
11.一种半导体装置封装的制造方法,其包含:
在一载体上方放置多个第一电子装置;
在所述多个第一电子装置上方放置多个第二电子装置以形成多个堆叠结构,其中每一所述多个堆叠结构包含至少一所述第一电子装置和至少一所述第二电子装置;
分离所述多个堆叠结构;
自所述载体移开所述多个堆叠结构;
在一封装衬底上方放置所述堆叠结构;和
在所述封装衬底上方形成一第一模封层以包覆所述堆叠结构。
12.根据权利要求11所述的方法,其进一步包含移除所述第一模封层的一部分以暴露所述第二电子装置的一上表面。
13.根据权利要求11所述的方法,其进一步包含在分离所述多个堆叠结构前,在所述多个堆叠结构上方形成一第二模封层。
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