CN112086414A - 半导体封装结构 - Google Patents
半导体封装结构 Download PDFInfo
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- CN112086414A CN112086414A CN202010484230.5A CN202010484230A CN112086414A CN 112086414 A CN112086414 A CN 112086414A CN 202010484230 A CN202010484230 A CN 202010484230A CN 112086414 A CN112086414 A CN 112086414A
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- thermal interface
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Abstract
本发明提供了一种半导体封装结构。该半导体封装结构包括:基板,半导体裸晶,成型材料,第一接合层和热接口材料。半导体裸晶被设置在基板的上方。成型材料环绕半导体裸晶。第一接合层被设置在半导体裸晶的上方。热接口材料被设置在成型材料的上方。
Description
相关申请的交叉引用
本申请要求2019年6月14日递交的申请号为62/861,379的美国临时案以及2020年3月5日递交的申请号为62/985,371的美国临时案的优先权,在此合并参考上述申请案的全部内容。
技术领域
本发明涉及一种半导体封装结构,尤其涉及一种具有热接口材料(thermalinterface material)的半导体封装结构。
背景技术
半导体封装结构不仅能够给半导体裸晶(semiconductor die)提供免受环境污染物侵害的保护,而且还能够在封装于其中的半导体裸晶与诸如印刷电路板(printedcircuit board,PCB)的基板之间提供电连接。
在半导体裸晶的操作期间会产生热量。如果没有充分除去热量,则升高的温度会损坏半导体组件,并会导致热应力和半导体封装结构的弯曲(warpage)。
需要将散热装置(heat dissipation device)设置在半导体封装结构中。散热器/散热片(heatsink)通常用于散发热量。热接口材料被设置在半导体裸晶和散热器之间,以促进热量从半导体裸晶传递到散热器。然而,尽管半导体封装结构中的现有散热装置通常能够满足要求,但是它们并不是在各个方面都令人满意,因此,需要进一步的改进以提高散热效率。
发明内容
有鉴于此,本发明的目的之一在于提供一种半导体封装结构,以解决上述问题。
本发明提供了一种半导体封装结构。半导体封装结构的示例性实施例包括:基板,半导体裸晶,成型材料,第一接合层和热接口材料。半导体裸晶被设置在基板的上方。成型材料环绕半导体裸晶。第一接合层被设置在半导体裸晶的上方。热接口材料被设置在成型材料的上方。
在一些实施例中,该半导体封装结构还包括:第一散热器,被设置在该第一接合层的上方。
在一些实施例中,该热接口材料连接该成型材料和该第一散热器。
在一些实施例中,该热接口材料是粘合剂。
在一些实施例中,该热接口材料环绕该第一接合层。
在一些实施例中,该热接口材料和该第一接合层被间隙间隔开。
在一些实施例中,该半导体封装结构还包括:金属层,被设置在该第一接合层和该半导体裸晶之间。
在一些实施例中,该热接口材料具有至少一个凹口。
在一些实施例中,该热接口材料被至少一个缺口切断。
在一些实施例中,该热接口材料部分地环绕该第一接合层。
在一些实施例中,该半导体封装结构还包括:导电组件,被设置在该半导体裸晶和该基板之间。
在一些实施例中,该半导体封装结构还包括:被设置在该基板下方的第二散热器,其中,该第二散热器透过第二接合层接合至该基板。
在一些实施例中,该第二散热器是在接合该第一散热器之前被接合的,以及,该第一接合层的熔点低于该第二接合层的熔点。
在一些实施例中,该第一接合层包括SnBi,SnBiAg或其组合。
在一些实施例中,该热接口材料比该金属层厚并且比该接合层厚。
在一些实施例中,该热接口材料的侧壁与该成型材料的侧壁对准。
本领域技术人员在阅读附图所示优选实施例的下述详细描述之后,可以毫无疑义地理解本发明的这些目的及其它目的。详细的描述将参考附图在下面的实施例中给出。
附图说明
通过阅读后续的详细描述以及参考附图所给的示例,可以更全面地理解本发明。
图1是根据本发明一些实施例的半导体封装结构的截面图。
图2是根据本发明一些其它实施例的半导体封装结构的截面图。
图3A至图3B是根据本发明一些实施例的半导体封装结构的俯视图。
图4是根据本发明一些其它实施例的半导体封装结构的截面图。
图5A至图5C是根据本发明一些实施例的半导体封装结构的俯视图。
图6是根据本发明一些其它实施例的半导体封装结构的截面图。
在下面的详细描述中,为了说明的目的,阐述了许多具体细节,以便本领域技术人员能够更透彻地理解本发明实施例。然而,显而易见的是,可以在没有这些具体细节的情况下实施一个或多个实施例,不同的实施例可根据需求相结合,而并不应当仅限于附图所列举的实施例。
具体实施方式
以下描述为本发明实施的较佳实施例,其仅用来例举阐释本发明的技术特征,而并非用来限制本发明的范畴。在通篇说明书及权利要求书当中使用了某些词汇来指称特定的元件,所属领域技术人员应当理解,制造商可能会使用不同的名称来称呼同样的元件。因此,本说明书及权利要求书并不以名称的差异作为区别元件的方式,而是以元件在功能上的差异作为区别的基准。本发明中使用的术语“元件”、“系统”和“装置”可以是与计算机相关的实体,其中,该计算机可以是硬件、软件、或硬件和软件的结合。在以下描述和权利要求书当中所提及的术语“包含”和“包括”为开放式用语,故应解释成“包含,但不限定于…”的意思。此外,术语“耦接”意指间接或直接的电气连接。因此,若文中描述一个装置耦接于另一装置,则代表该装置可直接电气连接于该另一装置,或者透过其它装置或连接手段间接地电气连接至该另一装置。
参考特定实施例并且参考某些附图描述了本发明,但是本发明不限于此,而是仅由权利要求书限制。所描述的附图仅是示意性的而非限制性的。在附图中,出于说明的目的,一些组件的尺寸可能被放大且未按比例绘制。在本发明的实践中,尺寸和相对尺寸不对应于实际尺寸。文中所用术语“基本”或“大致”系指在可接受的范围内,所属技术领域中具有通常知识者能够解决所要解决的技术问题,基本达到所要达到的技术效果。举例而言,“基本等于”系指在不影响结果正确性时,所属技术领域中具有通常知识者能够接受的与“完全等于”有一定误差的方式。
图1是根据本发明一些实施例的半导体封装结构100的截面图。附加的特征可以被添加至半导体封装结构100。对于不同的实施例,可以替换或消除以下描述的一些特征。为了简化该图,在图1中仅示出了半导体封装结构100的一部分。
如图1所示,根据一些实施例,基板(substrate)102被提供。基板102可以是无核芯/核芯基板(coreless/core substrate)或印刷电路板(PCB)。基板102可以由聚丙烯(polypropylene,PP),聚酰亚胺(Polyimide),BT/环氧树脂(BT/Epoxy),预浸料(Prepreg),ABF,陶瓷材料(ceramic material)或其它合适的材料形成。任何期望的半导体组件(element)可以被形成在基板102之中和之上(in and on)。然而,为了简化附图,仅示出了平坦的(flat)基板102。
半导体封装结构100包括半导体裸晶106,半导体裸晶106被设置在基板102的上方(over)。为了简化起见,根据一些实施例,图1仅示出了一个半导体裸晶106,但本发明并不限于此。例如,在一些实施例中,可以将多个半导体裸晶106设置在基板102的上方且该多个半导体裸晶被并排(side-by-side)布置。在一些实施例中,半导体裸晶106是主动装置(active device)。例如,半导体裸晶106是片上系统(system-on-chip,SOC)裸晶,其可以包括微控制器(microcontroller,MCU),微处理器(microprocessor,MPU),电源管理集成电路(power management integrated circuit,PMIC),全球定位系统(global positioningsystem,GPS)装置,或射频(radio frequency,RF)装置等或其任意组合。可选地,半导体裸晶106可以是模拟裸晶,其可以包括中央处理单元(central processing unit,CPU),图形处理单元(graphics processing unit,GPU),动态随机存取存储器(dynamic randomaccess memory,DRAM)控制器等或其任意组合。在一些其它实施例中,一个或多个无源装置(诸如电阻器,电容器,电感器等或其组合)也可以被接合至(bonded onto)基板102上。
根据一些实施例,半导体封装结构100包括:环绕(surrounding)半导体裸晶106的成型材料(molding material)108。成型材料108邻接(adjoin)半导体裸晶106的侧壁。尽管图1的示例使得半导体裸晶106的上表面被露出,但是,在一些实施例中,半导体裸晶106的上表面也可以被成型材料108覆盖,本发明对此不做限制。
在一些实施例中,成型材料108包括非导电材料,诸如环氧树脂,树脂,可成型聚合物或另一种合适的成型材料。在一些实施例中,成型材料108被作为大量液体(substantialliquid)应用,然后通过化学反应被固化。在一些其它实施例中,成型材料108是作为凝胶或可延展的固体应用的紫外线(an ultraviolet,UV)或热固化的聚合物,然后通过紫外线或热固化工艺来固化。可以用模具(未示出)来固化成型材料108。
如图1所示,根据一些实施例,半导体裸晶106和成型材料108通过导电组件104接合至基板102上。在一些实施例中,导电组件104包括导电球结构,导电柱结构或导电胶结构(conductive paste structures),其在接合工艺(bonding process)中被安装在基板102上并电耦接至基板102。例如,导电组件104可以是触点栅格阵列(land grid array,LGA),球形栅格阵列(ball grid array,BGA)等或它们的组合。
如图1所示,根据一些实施例,半导体封装结构100包括散热器(heatsink)122,散热器122通过热接口材料(thermal interface material)120接合至半导体裸晶106。散热器122可以由Cu,Al等或其组合制成。热接口材料120可包括聚合物,例如,该聚合物为粘合剂(adhesive)。例如,热接口材料120可以是硅酮粘合剂,诸如来自Dow-Corning的SE4450环氧树脂。在其它示例中,热接口材料120还可以包括陶瓷材料,例如晶体氧化物,氮化物或碳化物材料。
然而,在一些实施例中,当仅使用热接口材料120连接散热器122和半导体裸晶106时,会发生副作用(side effects)。通常,具有高粘度的热接口材料120具有低导热率。因此,热接口材料120是半导体裸晶106和散热器122之间的热瓶颈(thermal bottleneck)。因此,本发明提供了解决上述问题的另一实施例。
图2是根据本发明的一些其它实施例的半导体封装结构200的截面图。应当注意,半导体封装结构200包括与图1所示的半导体封装结构100相同或相似的组件,为了简单起见,将不再详细讨论那些组件。与图1(仅通过热接口材料120将散热器122接合至半导体裸晶106)的实施例相比,以下实施例将用接合层(bonding layer)代替热接口材料120的一部分,以提高散热效率。
可以将附加特征添加到半导体封装结构200。对于不同的实施例,可以替换或消除以下描述的一些特征。为了简化该图,在图2中仅示出了半导体封装结构200的一部分。
如图2所示,根据一些实施例,可选的金属层(metal layer)124被设置(isdisposed on)在半导体裸晶106上,以提供用于在其上形成接合层的表面。例如,通过背面金属化(backside metallization,BSM)技术,在半导体裸晶106上形成金属层124。在一些实施例中,金属层124可通过化学气相沉积,溅射沉积,电镀等或其组合形成。金属层124可以包括金,银,铬,钛,钨,钒,镍等,其合金或它们的组合。金属层124还可包括不锈钢(backside metallization,SUS)材料。金属层124可以是单层或多层。
尽管如图所示,半导体裸晶106与成型材料108共平面(coplanar),但是本发明不限于此。例如,在一些实施例中,成型材料108是在形成金属层124之后形成的,以及,成型材料108也环绕金属层124。在这些实施例中,成型材料108与金属层124共平面。
如图2所示,根据一些实施例,接合层126被设置在金属层124上。接合层126可以包括金属或焊接材料(metal or solder material)。例如,接合层126可以是铅,锡,铟,银,铜等,其合金或它们的组合。由于接合层126具有比热接口材料120更好的导热率,例如是热接口材料120的导热率的10倍,因此,通过设置接合层126能够提高散热效率。
然而,如果只有接合层126被用来将散热器122接合至半导体裸晶106,则应力会很高。在这种情况下,在诸如表面安装技术(surface mount technology,SMT)的顺序工艺中,接合层126是易碎的,从而造成产量损失。因此,根据本发明的半导体封装结构200包括热接口材料120和接合层126这两者,从而在不增加应力的情况下提高了散热效率,这对于大功率应用是优选的。因此,热性能、可制造性和可靠性能够被同时提高。
如图2所示,在一些实施例中,热接口材料120位于成型材料108的上方,以及,金属层124和接合层126位于半导体裸晶106的上方。根据一些实施例,散热器122通过热接口材料120连接至成型材料108,以及,散热器122通过金属层124和接合层126连接至半导体裸晶106。热接口材料120被设置在成型材料108的边缘(edge)上。特别地,热接口材料120的侧壁与成型材料108的侧壁对准(align)。
在一些实施例中,热接口材料120与金属层124、接合层126间隔开一间隙(gap),以防止由热接口材料120与金属层124、接合层126的热膨胀系数(CTE)的不同引起的问题。因此,半导体封装结构的可靠性能够被提高。例如,热接口材料120与金属层124、接合层126之间间隔开的该间隙环绕金属层124、接合层126。
在一些实施例中,热接口材料120比金属层124厚并且比接合层126厚,以提供用于在其上接合散热器122的平坦表面(planar surface)。可选地,如上所述,在一些其它实施例中(例如,成型材料108在设置金属层124之后形成的实施例中),成型材料108与金属层124共平面。在这些实施例中,热接口材料120的厚度基本等于接合层126的厚度,以提供用于将散热器122接合在其上的平坦平面。
图3A至图3B是根据本发明一些实施例的半导体封装结构的俯视图(plan view)。应该注意的是,图3A至图3B是从图2所示的半导体封装结构200的顶部看的俯视图,为简洁起见,省略了一些组件。
如图3A所示,根据一些实施例,热接口材料120环绕接合层126。尽管未示出,但是热接口材料120也环绕被设置在接合层126下方的金属层124(参考图2)。热接口材料120被设置在成型材料108的边缘上。热接口材料120的侧壁可以与成型材料108的侧壁对准。
在一些实施例中,热接口材料120与金属层124、接合层126间隔开一间隙,以防止由热接口材料120与金属层124、接合层126的热膨胀系数(CTE)的不同引起的问题。因此,可以提高半导体封装结构的可靠性。
在图3A所示的实施例中,热接口材料120完全围绕接合层126,或者,完全围绕接合层126和金属层124。例如,图3A示出了成型材料120呈类“回”字形的结构示意图,但本发明并不限于此。根据一些实施例,热接口材料120可以部分地环绕(partially surrounds)接合层126,如图3B所示。尽管未示出,但是在一些实施例中,热接口材料120也可以部分地环绕被设置在接合层126下方的金属层124。换句话说,在一些实施例中,热接口材料120被缺口(gap)132切断(cut off)。缺口132可以释放在制造过程中产生的气体。因此,半导体封装结构的可靠性能够被进一步提高。
尽管在图3B中示出了仅一个缺口132,但本发明不限于此。例如,热接口材料120可以被类似于缺口132的多个缺口切断。特别地,热接口材料120可以包括多个分开/分离/独立的部分(separate sections)。
在一些实施例中,代替被缺口132切断,热接口材料120可具有凹口(notch)(未示出)以释放气体。在其它实施例中,热接口材料120被一个或多个缺口132和/或一个或多个凹口切断。在本发明实施例中,热接口材料120具有至少一个缺口/凹口,其中,缺口132和所述凹口的设置均是为了释放制造过程中产生的气体,以进一步提高半导体封装结构的可靠性。
图4是根据本发明一些其它实施例的半导体封装结构300的截面图。应当注意,半导体封装结构300包括与图2所示的半导体封装结构200相同或相似的组件,为了简单起见,将不再详细讨论那些组件。与图2(热接口材料120被设置在成型材料108的边缘上)的实施例相比,热接口材料120被设置在成型材料108的外围(periphery)上。特别地,热接口材料120的侧壁在成型材料108的侧壁的内侧/里面(inside)。或者说,热接口材料120的外侧壁不与成型材料108的外侧壁对准(图2示出了对准的示例)。例如,热接口材料120的外侧壁比成型材料108的外侧壁更靠近里面。
图5A至图5C是根据本发明一些实施例的半导体封装结构的俯视图。应该注意的是,图5A至图5C是从图4所示的半导体封装结构300的顶部看的俯视图,为了简洁起见,一些组件被省略。
如图5A所示,根据一些实施例,热接口材料120环绕接合层126。尽管未示出,但是热接口材料120也可以环绕被设置在接合层126下方的金属层124(参考图4)。热接口材料120可以被设置在成型材料108的外围(periphery)上。
在一些实施例中,热接口材料120与金属层124、接合层126通过间隙间隔开,以防止由热接口材料120与金属层124、接合层126的热膨胀系数(CTE)的不同引起的问题。因此,半导体封装结构的可靠性能够被提高。
如图5B所示,根据一些实施例,热接口材料120部分地环绕接合层126。尽管未示出,但是在一些实施例中,热接口材料120也可以部分地环绕被设置在接合层126下方的金属层124。换句话说,在一些实施例中,热接口材料120被缺口132切断。缺口132可以释放在制造过程中产生的气体。因此,可以进一步提高半导体封装结构的可靠性。
尽管在图5B中示出了仅一个缺口132,但是本发明不限于此。例如,热接口材料120可以被多个缺口切断,如图5C所示。特别地,热接口材料120可以包括多个独立的部分(separate sections)。
在一些实施方式中,代替被缺口切断,热接口材料120具有凹口(未示出)以释放气体。在其它实施例中,热接口材料120被一个或多个缺口132和/或一个或多个凹口切断。
图6是根据本发明一些其它实施例的半导体封装结构400的截面图。应当注意,半导体封装结构400包括与半导体封装结构200相同或相似的部件,为了简单起见,将不再详细讨论那些部件。与图2的(散热器122被设置在基板102的上方)实施例相比,以下实施例还提供了另一散热器,该另一散热器被设置在基板102的下方,以进一步提高散热效率。
如图6所示,根据一些实施例,半导体封装结构400包括:被设置在基板102的相对侧(opposite sides)上的散热器122和散热器130。散热器130通过接合层128接合到至基板102。接合层128可以包括金属或焊接材料。例如,接合层128可以是铅,锡,铟,银,铜等,其合金或它们的组合。尽管仅示出了两个散热器(散热器122和散热器130),但是根据需要,本发明可以包括两个以上的散热器。
在一实施例中,散热器130是在接合散热器122之前被接合的。在该实施例中,如果接合散热器122时的温度高于或基本等于接合层128的熔点(opposite sides),则在诸如回流(reflow)的过程中,接合层128将熔化并导致散热器130掉落。就这一点而言,根据一些实施例,具有比接合层128的熔点低的接合层126(接合层126的熔点低于接合层128的熔点)能够防止该问题。例如,接合层126可以包括SnBi,SnBiAg等或其组合。
类似地,可以基于工艺顺序来调整接合层的组成。例如,如果散热器122是在接合散热器130之前被接合的,则用于接合散热器130的接合层128的熔点低于用于接合散热器122的接合层126的熔点。因此,半导体封装结构400的可靠性能够被提高。
综上,本发明提供了一种半导体封装结构,其包括用于将散热器接合至基板的接合层和热接口材料,从而,能够在不增加应力的情况下提高散热效率。因此,半导体封装结构的热性能,可制造性和可靠性能够被同时提高。
此外,根据一些实施例,热接口材料和接合层通过间隙间隔开以防止CTE不匹配。另外,根据一些实施例,被一个或多个缺口切断的热接口材料和/或具有一个或多个凹口的热接口材料(热接口材料部分围绕接合层126,或者,部分围绕接合层126和金属层124)可以释放在制造过程中产生的气体。
此外,在一些实施例中,半导体封装结构具有位于相对侧上的多个散热器,以进一步提高散热效率。在将一散热器接合至基板之后将另一个散热器接合至半导体裸晶的实施例中,用于前者的接合层的熔点低于用于后者的接合层的熔点是优选的。因此,在工艺期间能够减少散热器掉落的风险,从而提高了半导体封装结构的可靠性。
可以对本发明的实施例做出许多变化和/或修改。根据本发明的一些实施例的半导体封装结构可以用于形成三维(three-dimensional,3D)封装,2.5D封装,扇出式封装或另一种合适的封装。
虽然本发明已经通过示例的方式以及依据优选实施例进行了描述,但是,应当理解的是,本发明并不限于公开的实施例。相反,它旨在覆盖各种变型和类似的结构(如对于本领域技术人员将是显而易见的),例如,不同实施例中的不同特征的组合或替换。因此,所附权利要求的范围应被赋予最宽的解释,以涵盖所有的这些变型和类似的结构。
Claims (15)
1.一种半导体封装结构,包括:
基板;
半导体裸晶,被设置在该基板的上方;
环绕该半导体裸晶的成型材料;
第一接合层,被设置在该半导体裸晶的上方;以及,
热接口材料,被设置在该成型材料的上方。
2.根据权利要求1所述的半导体封装结构,其特征在于,该半导体封装结构还包括:
第一散热器,被设置在该第一接合层的上方。
3.根据权利要求2所述的半导体封装结构,其特征在于,该热接口材料连接该成型材料和该第一散热器。
4.根据权利要求1所述的半导体封装结构,其特征在于,该热接口材料是粘合剂。
5.根据权利要求1所述的半导体封装结构,其特征在于,该热接口材料环绕该第一接合层。
6.根据权利要求1或5所述的半导体封装结构,其特征在于,该热接口材料和该第一接合层被间隙间隔开。
7.根据权利要求1或2所述的半导体封装结构,其特征在于,该半导体封装结构还包括:
金属层,被设置在该第一接合层和该半导体裸晶之间。
8.根据权利要求1所述的半导体封装结构,其特征在于,该热接口材料具有至少一个凹口;或者,该热接口材料被至少一个缺口切断。
9.根据权利要求1所述的半导体封装结构,其特征在于,该热接口材料部分地环绕该第一接合层。
10.根据权利要求1所述的半导体封装结构,其特征在于,该半导体封装结构还包括:
导电组件,被设置在该半导体裸晶和该基板之间。
11.根据权利要求2所述的半导体封装结构,其特征在于,该半导体封装结构还包括:
被设置在该基板下方的第二散热器,其中,该第二散热器透过第二接合层接合至该基板。
12.根据权利要求11所述的半导体封装结构,其特征在于,该第二散热器是在接合该第一散热器之前被接合的,以及,该第一接合层的熔点低于该第二接合层的熔点。
13.根据权利要求1所述的半导体封装结构,其特征在于,该第一接合层包括SnBi,SnBiAg或其组合。
14.根据权利要求7所述的半导体封装结构,其特征在于,该热接口材料比该金属层厚并且比该接合层厚。
15.根据权利要求1所述的半导体封装结构,其特征在于,该热接口材料的侧壁与该成型材料的侧壁对准。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5990550A (en) * | 1997-03-28 | 1999-11-23 | Nec Corporation | Integrated circuit device cooling structure |
CN104716112A (zh) * | 2013-12-16 | 2015-06-17 | 英特尔公司 | 用于多芯片封装的三维(3d)集成散热器 |
CN107170724A (zh) * | 2015-10-09 | 2017-09-15 | 台湾积体电路制造股份有限公司 | 冷却器件、封装的半导体器件和封装半导体器件的方法 |
CN109148397A (zh) * | 2017-06-16 | 2019-01-04 | 日月光半导体制造股份有限公司 | 半导体装置封装 |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5909056A (en) * | 1997-06-03 | 1999-06-01 | Lsi Logic Corporation | High performance heat spreader for flip chip packages |
JP2000114413A (ja) * | 1998-09-29 | 2000-04-21 | Sony Corp | 半導体装置、その製造方法および部品の実装方法 |
WO2001031082A1 (en) * | 1999-10-28 | 2001-05-03 | P1 Diamond, Inc. | Improved diamond thermal management components |
KR100446290B1 (ko) * | 2001-11-03 | 2004-09-01 | 삼성전자주식회사 | 댐을 포함하는 반도체 패키지 및 그 제조방법 |
US6787899B2 (en) * | 2002-03-12 | 2004-09-07 | Intel Corporation | Electronic assemblies with solidified thixotropic thermal interface material |
US6767765B2 (en) | 2002-03-27 | 2004-07-27 | Intel Corporation | Methods and apparatus for disposing a thermal interface material between a heat source and a heat dissipation device |
US7408787B2 (en) * | 2003-07-30 | 2008-08-05 | Intel Corporation | Phase change thermal interface materials including polyester resin |
US7312261B2 (en) * | 2004-05-11 | 2007-12-25 | International Business Machines Corporation | Thermal interface adhesive and rework |
US7015577B2 (en) * | 2004-07-21 | 2006-03-21 | Advanced Semiconductor Engineering, Inc. | Flip chip package capable of measuring bond line thickness of thermal interface material |
US7755184B2 (en) | 2004-12-03 | 2010-07-13 | Chris Macris | Liquid metal thermal interface material system |
JP4155999B2 (ja) | 2006-06-02 | 2008-09-24 | 株式会社ソニー・コンピュータエンタテインメント | 半導体装置および半導体装置の製造方法 |
JP4589269B2 (ja) | 2006-06-16 | 2010-12-01 | ソニー株式会社 | 半導体装置およびその製造方法 |
US7999369B2 (en) | 2006-08-29 | 2011-08-16 | Denso Corporation | Power electronic package having two substrates with multiple semiconductor chips and electronic components |
JP2010103244A (ja) | 2008-10-22 | 2010-05-06 | Sony Corp | 半導体装置及びその製造方法 |
US8232636B2 (en) * | 2010-01-26 | 2012-07-31 | International Business Machines Corporation | Reliability enhancement of metal thermal interface |
WO2011092859A1 (ja) | 2010-02-01 | 2011-08-04 | トヨタ自動車株式会社 | 半導体装置の製造方法および半導体装置 |
US8804331B2 (en) * | 2011-12-02 | 2014-08-12 | Ati Technologies Ulc | Portable computing device with thermal management |
US9041192B2 (en) * | 2012-08-29 | 2015-05-26 | Broadcom Corporation | Hybrid thermal interface material for IC packages with integrated heat spreader |
JP6130696B2 (ja) * | 2013-03-26 | 2017-05-17 | 田中貴金属工業株式会社 | 半導体装置 |
FR3011067B1 (fr) * | 2013-09-23 | 2016-06-24 | Commissariat Energie Atomique | Appareil comportant un composant fonctionnel susceptible d'etre en surcharge thermique lors de son fonctionnement et un systeme de refroidissement du composant |
US9287233B2 (en) | 2013-12-02 | 2016-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Adhesive pattern for advance package reliability improvement |
US10049896B2 (en) * | 2015-12-09 | 2018-08-14 | International Business Machines Corporation | Lid attach optimization to limit electronic package warpage |
WO2017123188A1 (en) * | 2016-01-11 | 2017-07-20 | Intel Corporation | Multiple-chip package with multiple thermal interface materials |
US9918407B2 (en) * | 2016-08-02 | 2018-03-13 | Qualcomm Incorporated | Multi-layer heat dissipating device comprising heat storage capabilities, for an electronic device |
CN106356341A (zh) | 2016-08-31 | 2017-01-25 | 华为技术有限公司 | 一种半导体装置及制造方法 |
US10319609B2 (en) | 2017-06-21 | 2019-06-11 | International Business Machines Corporation | Adhesive-bonded thermal interface structures |
US10483187B2 (en) * | 2017-06-30 | 2019-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heat spreading device and method |
US10431517B2 (en) * | 2017-08-25 | 2019-10-01 | Advanced Micro Devices, Inc. | Arrangement and thermal management of 3D stacked dies |
US11817364B2 (en) | 2018-06-25 | 2023-11-14 | Intel Corporation | BGA STIM package architecture for high performance systems |
DE102018216593A1 (de) | 2018-09-27 | 2020-04-02 | Robert Bosch Gmbh | Leistungshalbleitermodul |
US11088109B2 (en) | 2018-11-21 | 2021-08-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Packages with multi-thermal interface materials and methods of fabricating the same |
CN209029362U (zh) * | 2018-11-23 | 2019-06-25 | 北京比特大陆科技有限公司 | 芯片散热结构、芯片结构、电路板和超算设备 |
-
2020
- 2020-05-22 US US16/881,206 patent/US11621211B2/en active Active
- 2020-06-01 CN CN202010484230.5A patent/CN112086414A/zh active Pending
- 2020-06-02 TW TW109118412A patent/TWI721898B/zh active
- 2020-06-10 EP EP20179156.3A patent/EP3751603B1/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5990550A (en) * | 1997-03-28 | 1999-11-23 | Nec Corporation | Integrated circuit device cooling structure |
CN104716112A (zh) * | 2013-12-16 | 2015-06-17 | 英特尔公司 | 用于多芯片封装的三维(3d)集成散热器 |
CN107170724A (zh) * | 2015-10-09 | 2017-09-15 | 台湾积体电路制造股份有限公司 | 冷却器件、封装的半导体器件和封装半导体器件的方法 |
CN109148397A (zh) * | 2017-06-16 | 2019-01-04 | 日月光半导体制造股份有限公司 | 半导体装置封装 |
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