CN107104081A - 具有高可靠性的半导体封装件 - Google Patents

具有高可靠性的半导体封装件 Download PDF

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Publication number
CN107104081A
CN107104081A CN201710097125.4A CN201710097125A CN107104081A CN 107104081 A CN107104081 A CN 107104081A CN 201710097125 A CN201710097125 A CN 201710097125A CN 107104081 A CN107104081 A CN 107104081A
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Prior art keywords
semiconductor devices
semiconductor
package
underfill fillet
package substrates
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CN201710097125.4A
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CN107104081B (zh
Inventor
黄智焕
朴商植
闵台洪
南杰
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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Abstract

公开了一种半导体封装件。所述半导体封装件包括封装基底、堆叠在封装基底上的多个半导体器件、设置在所述多个半导体器件之间以及封装基底与所述多个半导体器件之间的多个底部填充填角以及至少部分地围绕所述多个半导体器件和所述多个底部填充填角的模制树脂。所述多个底部填充填角包括从所述多个半导体器件中的每个之间或者封装基底和所述多个半导体器件中的每个之间的空间突出的多个突起。所述多个突起中的至少两个相邻的底部填充填角突起形成一个连续结构，在其间没有界面。

Description

具有高可靠性的半导体封装件
本申请要求于2016年2月22日提交到韩国知识产权局的第10-2016-0020695号韩国专利申请的优先权，该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
发明构思涉及一种半导体封装件，更具体地，涉及一种具有高可靠性的半导体封装件。
背景技术
近来，半导体芯片(例如，存储芯片)正变得高度集成。正在对堆叠高度集成的半导体芯片的方法进行研究。
发明内容
发明构思提供了一种具有高可靠性和低制造成本的半导体封装件。
在发明构思的示例性实施例中，半导体封装件包括封装基底、堆叠在封装基底上的多个半导体器件、设置在所述多个半导体器件之间以及封装基底与所述多个半导体器件之间的多个底部填充填角以及至少部分地围绕所述多个半导体器件和所述多个底部填充填角的模制树脂。所述多个底部填充填角包括从所述多个半导体器件中的每个之间或者封装基底和所述多个半导体器件中的每个之间的空间突出的多个突起。所述多个突起中的至少两个相邻的底部填充填角突起形成一个连续结构，在其间没有界面。
在发明构思的示例性实施例中，半导体封装件包括封装基底、堆叠在封装基底上的多个半导体器件、设置在所述多个半导体器件之间以及封装基底与所述多个半导体器件之间的多个底部填充填角以及至少部分地围绕所述多个半导体器件和所述多个底部填充填角的模制树脂。所述多个半导体器件之间以及封装基底和所述多个半导体器件之间的间隔对于更加远离封装基底的半导体器件变得更小。
在发明构思的示例性实施例中，半导体封装件包括：封装基底；堆叠在封装基底上的第一半导体器件和第二半导体器件，其中，第一半导体器件设置在封装基底和第二半导体器件之间；设置在封装基底和第一半导体器件之间的第一底部填充填角以及设置在第一半导体器件和第二半导体器件之间的第二底部填充填角；以及模制树脂，覆盖第一底部填充填角和第二底部填充填角中每个的至少一部分。第一底部填充填角从封装基底和第一半导体器件之间的区域突出，第二底部填充填角从第一半导体器件和第二半导体器件之间的区域突出。第一底部填充填角的突起与第二底部填充填角的突起形成一个连续结构。
附图说明
通过结合附图详细地描述发明构思的示例性实施例，发明构思的以上和其它特征将变得更加明显，在附图中：
图1A是根据发明构思的示例性实施例的半导体封装件的剖视图；
图1B是根据发明构思的示例性实施例制造的半导体封装件的底部填充填角部分的剖视图像；
图1C是根据一种方法制造的半导体封装件的剖视图像；
图2至图9是根据发明构思的示例性实施例的半导体封装件的剖视图；
图10是根据发明构思的示例性实施例制造半导体封装件的方法的流程图；
图11A至图11G是用于顺序地示出根据发明构思的示例性实施例的制造半导体封装件的方法的剖视图；
图12示出根据一种方法用于制造半导体封装件的温度曲线。
具体实施方式
图1A是根据发明构思的示例性实施例的半导体封装件100的剖视图。
参照图1A，多个半导体器件110可以堆叠在封装基底120上。底部填充填角(underfill fillet)130a可以存在于所述多个半导体器件110之间以及封装基底120和所述多个半导体器件110之间。
封装基底120可以是例如印刷电路板(PCB)基底、陶瓷基底或者中介层(interposer)。当封装基底120是PCB时，封装基底120可以包括基底基体以及可以分别形成在基底基体的上表面和下表面上的上焊盘和下焊盘。上焊盘和下焊盘可以被覆盖基底基体的上表面和下表面的阻焊层暴露。基底基体可以包括酚树脂、环氧树脂和/或聚酰亚胺。例如，基底基体可以包括FR4、四官能环氧树脂、聚苯醚、环氧/聚苯撑醚、双马来酰亚胺三嗪(BT)、聚酰胺短纤席材(thermount)、氰酸酯、聚酰亚胺和/或液晶聚合物。上焊盘和下焊盘可以包括铜、镍、不锈钢或铍铜。将上焊盘和下焊盘电连接的内部布线可以形成在基底基体中。上焊盘和下焊盘可以被阻焊层暴露。上焊盘和下焊盘可以是在基底基体的上表面和下表面上通过图案化铜(Cu)箔形成的电路布线的一部分。
当封装基底120是中介层时，封装基底120可以包括包含半导体材料的基底基体以及可以分别形成在基底基体的上表面和下表面上的上焊盘和下焊盘。基底基体可以包括例如硅晶片。内部布线可以形成在上表面上、下表面上或基底基体内部。电连接上焊盘和下焊盘的通孔可以形成在基底基体内部。
外部连接端子126可以附着到封装基底120的下表面上。外部连接端子126可以附着到下焊盘125上。外部连接端子126可以是例如焊球或凸块。外部连接端子126可以将半导体封装件100电连接到外部装置。
所述多个半导体器件110可以包括一个或更多个半导体芯片。在发明构思的示例性实施例中，所述多个半导体器件110可以包括一个或更多个半导体子封装件。在图1中，所述多个半导体器件110可以包括四个半导体器件110a、110b、110c和110d，但是发明构思不限于此。例如，多于四个的半导体器件可以堆叠在彼此上，或者少于四个的半导体器件可以堆叠在彼此上。
可以以倒装芯片的方式堆叠所述多个半导体器件110中最上面的(例如，离封装基底120最远的)半导体器件110d。在半导体器件110d的有效表面119f中，半导体器件110d可以集成有(例如，包括)例如晶体管的半导体器件。多个接合焊盘115a可以设置在有效表面119f上。多个接合焊盘115a可以符合指南(例如，JEDEC标准)。另外，多个接合焊盘115a中的每个可以具有几百纳米(nm)至几微米(μm)的厚度。多个接合焊盘115a可以包括Al、Cu、Ta、Ti、W、Ni和/或Au。
包括在半导体器件110d中的半导体基底111可以包括例如硅(Si)。可选择地，半导体基底111可以包括诸如锗(Ge)的半导体原子或诸如SiC(碳化硅)、GaAs(砷化镓)、InAs(砷化铟)和InP(磷化铟)的化合物半导体。另外，半导体基底111可以包括掩埋氧化物(BOX)层。半导体基底111可以包括导电区，例如，掺杂杂质的阱。半导体基底111可以具有诸如浅沟槽隔离(STI)结构的各种器件隔离结构。
包括各种类型的单独的半导体器件的半导体器件可以形成在半导体器件110d中。多个单独的半导体器件可以包括各种微电子器件，例如，诸如互补金属绝缘体半导体(CMOS)晶体管等的金属氧化物半导体场效应晶体管(MOSFET)、诸如系统大规模集成(LSI)、CMOS图像传感器(CIS)等的图像传感器、微机电系统(MEMS)、有源器件、无源器件等。多个单独的半导体器件可以电连接到半导体基底111的导电区。半导体器件还可包括将单独的半导体器件中的至少两个电连接或者将单独的半导体器件和半导体基底111的导电区电连接的导电布线或导电插塞。多个单独的半导体器件可以通过一个或更多个绝缘层与其它相邻的单独的半导体器件电分离。
半导体器件110d可以是例如存储半导体芯片。存储半导体芯片可以是例如诸如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、相变随机存取存储器(PRAM)、磁阻式随机存取存储器(MRAM)、铁电随机存取存储器(FeRAM)或电阻式随机存取存储器(RRAM)等的易失性存储半导体芯片。
半导体器件110a、110b和110c设置得比半导体器件110d低。例如，半导体器件110a、110b和110c可以设置在封装基底120和半导体器件110d之间。半导体器件110a、110b和110c中的每个可以在它们相应的半导体基底111中具有多个贯通电极113。所述多个贯通电极113可以例如具有几十μm的节距和矩阵布置。该节距可以是相邻贯通电极113的从中心到中心的距离。多个贯通电极113中的每个可以具有例如从几μm到几十μm范围的直径。多个贯通电极113中的每个的直径的值可以小于设置多个贯通电极113的节距。例如，多个贯通电极113可以具有从5μm到15μm范围的直径以及从25μm到50μm范围的节距。
贯通电极113可以形成为穿透硅通孔(TSV)。贯通电极113可以包括布线金属层和围绕布线金属层的阻挡金属层。布线金属层可以包括例如Cu或W。例如，布线金属层可以包括Cu、CuSn、CuMg、CuNi、CuZn、CuPd、CuAu、CuRe、CuW和/或W，但是不限于此。例如，布线金属层还可以包括Al、Au、Be、Bi、Co、Cu、Hf、In、Mn、Mo、Ni、Pb、Pd、Pt、Rh、Re、Ru、Ta、Te、Ti、W、Zn和/或Zr，可以具有单堆叠结构或者包括两个或更多个堆叠元件的结构。阻挡金属层可以包括W、WN、WC、Ti、TiN、Ta、TaN、Ru、Co、Mn、WN、Ni和/或NiB，可以具有单层结构或多层结构。然而，贯通电极113的材料不限于以上材料。
可以在物理气相沉积(PVD)工艺或化学气相沉积(CVD)工艺过程中形成阻挡金属层和布线金属层，但是不限于此。间隔绝缘层可以设置在贯通电极113与包括在多个半导体器件110a、110b和110c的每个中的半导体基底之间。间隔绝缘层可以防止形成在多个半导体器件110a、110b和110c中的半导体器件和贯通电极113彼此直接接触。间隔绝缘层可以包括氧化物层、氮化物层、碳化物层、聚合物或它们的组合。在发明构思的示例性实施例中，可以使用CVD工艺来形成间隔绝缘层。间隔绝缘层可以包括通过亚大气压CVD工艺形成的O3/TEOS(臭氧/正硅酸四乙酯)基高深宽比工艺(HARP)氧化物层。
贯通电极113可以将多个半导体器件110a、110b和110c中每个的有效表面119f和非有效表面119b直接连接，但是不限于此。贯通电极113可以以先通孔结构、中间通孔结构或后通孔结构来形成。
电连接到贯通电极113的前焊盘115a和后焊盘115b可以分别形成在多个半导体器件110a、110b和110c中每个的有效表面119f和非有效表面119b中。前焊盘115a和后焊盘115b可以形成为对应于贯通电极113并且可以电连接到贯通电极113。然而，前焊盘115a和后焊盘115b与贯通电极113的连接构造不限于此。前焊盘115a和后焊盘115b可以形成为远离贯通电极113，并且可以通过重布线层电连接到贯通电极113。前焊盘115a和后焊盘115b可以根据JEDEC标准形成，均可以具有几百nm至几μm的厚度。前焊盘115a和后焊盘115b可以包括Al、Cu、Ta、Ti、W、Ni和/或Au。
半导体器件110a、110b、110c和110d以及封装基底120可以通过连接端子117电连接到彼此。连接端子117可以包括锡(Sn)和银(Ag)的合金，根据需要还可以包括铜(Cu)、钯(Pd)、铋(Bi)、锑(Sb)等。连接端子117可以是焊球或凸块，根据需要还可以包括包含诸如铜、镍和金的金属的柱层。
底部填充填角130a可以填充半导体器件110a和封装基底120之间的空间。额外的底部填充填角130a可以填充半导体器件110b、110c和110d之间的空间。底部填充填角130a可以用来例如增加所述多个半导体器件110的元件组件的粘合强度，以及/或者有助于减少所述多个半导体器件110的物理状况由于元件组件的改变而导致的恶化。在发明构思的示例性实施例中，底部填充填角130a可以设置为例如填充杂质或湿气可以渗透到其中的空间，可以防止所述多个半导体器件110的电迁移。
底部填充填角130a可以从封装基底120和半导体器件110a、110b、110c和110d之间的空间向半导体器件110a、110b、110c和110d的侧表面的外侧突出。此外，从半导体器件110a、110b、110c和110d之间突出的底部填充填角130a可以是整体连续的(例如，作为一个元件连接在一起)。
例如，从封装基底120和半导体器件110a之间的空间突出的底部填充填角130a以及从半导体器件110a和半导体器件110b之间的空间突出的底部填充填角130a可以是整体连续的。从半导体器件110a和半导体器件110b之间的空间突出的底部填充填角130a以及从半导体器件110b和半导体器件110c之间的空间突出的底部填充填角130a也可以是整体连续的。从半导体器件110b和半导体器件110c之间的空间突出的底部填充填角130a以及从半导体器件110c和半导体器件110d之间的空间突出的底部填充填角130a也可以是整体连续的。就这一点而言，表述“底部填充填角130a是整体连续的”可以表示底部填充填角130a从一个空间到另一个空间是连续的，并且在底部填充填角130a中没有边界或界面。
底部填充填角130a的外表面(例如，从半导体器件110a、110b、110c和110d的侧表面朝向外侧突出的表面)可以具有其中朝向外侧的突出部上下重复的形状。在发明构思的示例性实施例中，表述“底部填充填角130a是整体连续的”可以表示在朝向外侧的突出部之间没有边界或界面。围绕半导体器件110a、110b、110c和110d以及底部填充填角130a的一些或全部的模制树脂140可以设置在封装基底120上。
图1B是根据发明构思的示例性实施例制造的半导体封装件的底部填充填角部分的剖视图像。图1C是根据一种方法制造的半导体封装件的剖视图像。
参照图1B，底部填充填角130a和围绕底部填充填角130a的模制树脂140可以从四个堆叠的半导体芯片(例如，所述多个半导体器件110)之间突出。虽然在底部填充填角130a和模制树脂140之间可以有清晰的界面，但是在底部填充填角130a之间没有发现界面。例如，底部填充填角130a整体连续(例如，底部填充填角130a形成一个结构)。
在图1C中，放大了根据一种方法制造的半导体芯片的由“A”表示的区域。参照图1C，在图1C的半导体封装件的剖视图中，底部填充填角可以从半导体芯片之间突出。在放大的区域“A”中，可以在多个突出的底部填充填角之间形成界面15。例如，底部填充填角彼此不成为一体且不连续。因此，底部填充填角不形成一个结构。
由于将在下面详细描述的制造方法，底部填充填角130a可以朝向半导体器件110a、110b、110c和110d的侧表面的外侧突出。在简要描述制造方法时，根据发明构思的示例性实施例，半导体器件110a、110b、110c和110d可以具有随后突出以变成底部填充填角130a的预施底部填充物。可以将半导体器件110a、110b、110c和110d设置在封装基底120上并且可以堆叠以制造半导体封装件100。预施底部填充物可以包括例如非导电膜(NCF)。在不回流连接端子117的同时，预施底部填充物可以根据NCF的粘着力而暂时结合。在一些情况中，预施底部填充物可以是例如非导电糊(NCP)。
然后，可通过将热和压力施加到最上面的半导体器件110d来回流连接端子117。随着温度升高，NCF可以逐渐变成流体。随着连接端子117的回流，半导体器件110a、110b、110c和110d之间的空间以及半导体器件110a和封装基底120之间的空间会减小。因此，由于外部施加的压力，多个半导体器件100的流体NCF可以部分地朝向半导体器件110a、110b、110c和110d的外侧挤出，并且可以设置在半导体器件110a、110b、110c和110d的侧表面上。该现象可以在半导体器件110a、110b、110c和110d之间的空间中以及半导体器件110a和封装基底120之间的空间中出现。NCF可以从半导体器件110a、110b、110c和110d之间的空间以及半导体器件110a和封装基底120之间的空间挤出。然而，发明构思的示例性实施例不限于此。只要不同半导体器件110的NCF在流体状态下从不同的半导体器件110之间或者半导体器件110和封装基底120之间的空间流出并且彼此汇合，那么当固化时NCF可以形成一个连续结构，在其间没有界面。
底部填充填角130a可以是例如BPA环氧树脂、BPF环氧树脂、脂肪族环氧树脂、脂环族环氧树脂等。底部填充填角130a还可以包括诸如碳化硅、氮化铝等的粉末作为无机填充剂。
如上所述，围绕半导体器件110a、110b、110c和110d以及底部填充填角130a的一些或全部的模制树脂140可以设置在封装基底120上。可以在模制树脂140和底部填充填角130a之间形成界面或边界。模制树脂140可以包括例如环氧塑封料(EMC)。
在发明构思的示例性实施例中，模制树脂140可以暴露所述多个半导体器件110中最上面的半导体器件110d的上表面。散热构件可以附着到模制树脂140和所述多个半导体器件110上，同时具有设置在散热构件、模制树脂140和所述多个半导体器件110之间的热界面材料(TIM)层。
TIM层可以包括绝缘材料或者包含绝缘材料且保持电绝缘的材料。TIM层可以包括例如环氧树脂。另外，TIM层可以包括例如矿物油、油脂、填隙油灰、相变凝胶、相变材料垫或颗粒填充环氧树脂。
散热构件可以包括例如散热器、散热片、热管或液冷式冷却板。
图2是根据发明构思的示例性实施例的半导体封装件100a的剖视图。
参照图2，如参照图1A所述，底部填充填角130a可以从封装基底120和半导体器件110a、110b、110c和110d之间的空间突出到半导体器件110a、110b、110c和110d的外侧。从其它空间延伸的底部填充填角130a也可以与从封装基底120和半导体器件110a、110b、110c和110d之间的空间突出的底部填充填角130a整体连续。
封装基底120和半导体器件110a、110b、110c和110d之间的间隔H1、H2、H3和H4可以不是均匀的。在发明构思的示例性实施例中，封装基底120和半导体器件110a、110b、110c和110d之间的间隔H1、H2、H3和H4可以彼此不同。在发明构思的示例性实施例中，封装基底120和半导体器件110a、110b、110c和110d之间的间隔H1、H2、H3和H4可以随着远离封装基底120而减小。例如，间隔H1、H2、H3和H4可以具有H1>H2>H3>H4的关系。
间隔H1、H2、H3和H4可以具有H1>H2>H3>H4的关系的原因可以是半导体器件110d的上表面的回流加热。例如，由于半导体器件110d的上表面是例如被加热的表面，所以例如向封装基底120传递的温度可以降低(例如，温度随着远离半导体器件110d的上表面而变得更低)，并且回流程度会与温度成比例地降低。高回流程度的部分可以具有相对小的间隔H4，而低回流程度的部分可具有相对大的间隔H1。
在发明构思的示例性实施例中，封装基底120和半导体器件110a、110b、110c和110d可以通过焊料凸块电连接到彼此。接合焊盘的厚度相对于封装基底120与半导体器件110a、110b、110c和110d可以是均匀的。间隔H1、H2、H3和H4可以与焊料凸块的高度直接相关。因此，焊料凸块的高度可以随着远离封装基底120而减小。
间隔H1、H2、H3和H4可以具有从大约5μm至大约100μm的范围的值。在示例中，间隔H1、H2、H3和H4可以具有从大约5μm至大约40μm的值。
围绕多个半导体器件110a、110b、110c和110d与底部填充填角130a的模制树脂140a可以部分地或完全地设置在封装基底120上。如图2中所示，模制树脂140a可以暴露所述多个半导体器件110中最上面的半导体器件110d的上表面。这可以通过例如在模制树脂140a形成为覆盖半导体器件110d的上表面之后去除模制树脂140a直至暴露半导体器件110d的上表面来实现。
边界或界面可以存在于底部填充填角130a和模制树脂140a之间。
图3是根据发明构思的示例性实施例的半导体封装件100b的剖视图。
参照图3，如参照图1A所述，底部填充填角130b可以从封装基底120以及半导体器件110a、110b、110c和110d之间的空间突出到半导体器件110a、110b、110c和110d的外侧。从其它空间延伸的底部填充填角130b也可以与从封装基底120和半导体器件110a、110b、110c和110d之间的空间突出的底部填充填角130b整体连续。
底部填充填角130b可以具有特别地独特的剖面形状。如图3中所示，预定的趋势可以存在于从封装基底120和半导体器件110a、110b、110c和110d之间的空间突出的底部填充填角130b中。
例如，底部填充填角130b可以包括与封装基底120和半导体器件110a之间的空间对应的块、与半导体器件110a和半导体器件110b之间的空间对应的块、与半导体器件110b和半导体器件110c之间的空间对应的块以及与半导体器件110c和半导体器件110d之间的空间对应的块。如图3中所示，当块的从下往上数的部分的位置顺序地是1、2、3和4时，从半导体器件110a、110b、110c和110d的侧表面突出的程度可以是1>2>3>4的顺序。例如，底部填充填角130b从每个空间突出的程度可以随着远离封装基底120而减小。
在发明构思的示例性实施例中，底部填充填角130b可以高于半导体器件110d的上表面而隆起。例如，底部填充填角130b的最上面的水平可以高于半导体器件110d的上表面的水平。就这一点而言，“水平”可以指在z轴方向上相对于封装基底120的距离。
最上面的半导体器件110d的上表面可以被底部填充填角130b部分地包覆。例如，半导体器件110d的上表面的边缘可以被底部填充填角130b至少部分地包覆。
这种类型的底部填充填角130可以由于如图3中箭头所示的在连接端子117的回流期间流动的预施底部填充物的流动轮廓而获得。例如，由于封装基底防止预施底部填充物向下移动(例如，在-z轴方向上移动)，所以存在于封装基底120和半导体器件110a之间的预施底部填充物可以突出最远(例如，程度1)。
由于底部填充物的一些可以向下流动而一些向上流动，所以从半导体器件110a和半导体器件110b之间的空间突出的底部填充物会突出得相对小于程度1。从半导体器件110b和半导体器件110c之间的空间突出的底部填充物可以受到小的重力影响，可以在向上(例如，+z轴)方向上流动，可以突出得小于程度2。由于底部填充物受到来自下面的底部填充物的力，所以从半导体器件110c和半导体器件110d之间的空间突出的底部填充物可以通过半导体器件110d的上表面上升至高水平，并且可以突出得小于程度3。
图4是根据发明构思的示例性实施例的半导体封装件100c的剖视图。
参照图4，如参照图1A所述，底部填充填角130c可以从封装基底120和半导体器件110a、110b、110c和110d之间的空间突出到半导体器件110a、110b、110c和110d的侧表面的外侧。从其它空间延伸的底部填充填角130c也可以与从封装基底120和半导体器件110a、110b、110c和110d之间的空间突出的底部填充填角130c整体连续。
底部填充填角130c可以具有特别地独特的剖面形状。如图4中所示，预定的趋势可以存在于从封装基底120和半导体器件110a、110b、110c和110d之间的空间突出至半导体器件110a、110b、110c和110d的外侧的底部填充填角130c中。
底部填充填角130c可以包括与封装基底120和半导体器件110a之间的空间对应的块、与半导体器件110a和半导体器件110b之间的空间对应的块、与半导体器件110b和半导体器件110c之间的空间对应的块以及与半导体器件110c和半导体器件110d之间的空间对应的块。如图4中所示，底部填充填角130c从半导体器件110a、110b、110c和110d的侧表面突出的程度可以是d>c>b>a的顺序。例如，每个底部填充填角130c突出的程度可以随着远离封装基底120而增加。
此外，封装基底120和半导体器件110a、110b、110c和110d之间的间隔H1c、H2c、H3c和H4c可以不是均匀的。在发明构思的示例性实施例中，封装基底120和半导体器件110a、110b、110c和110d之间的间隔H1c、H2c、H3c和H4c可以是不同的。在发明构思的示例性实施例中，封装基底120和半导体器件110a、110b、110c和110d之间的间隔H1c、H2c、H3c和H4c可以随着远离封装基底120而减小。例如，间隔H1c、H2c、H3c和H4c可以具有H1c>H2c>H3c>H4c的关系。
底部填充填角130c从半导体器件110a、110b、110c和110d的侧表面突出的突出程度d>c>b>a可以由间隔H1c、H2c、H3c和H4c的关系H1c>H2c>H3c>H4c引起。例如，如果假设设置在半导体器件110a、110b、110c和110d上的预施底部填充物的厚度相同，那么通过回流而减小间隔的底部填充物可以突出最多。因此，由于间隔H1c、H2c、H3c和H4c随着远离封装基底120而减小，流体和突出的底部填充物的量可以随着远离封装基底120而增加。
由底部填充填角130a、130b和130c形成的剖面形状可受诸如包括在底部填充填角130a、130b和130c中的聚合物的玻璃化转变温度(Tg)、粘度、固化特性、加热速度、冷却速度等的各种变量的影响。
图5是根据发明构思的示例性实施例的半导体封装件100d的剖视图。
参照图5，如参照图1A所述，底部填充填角130d可以从封装基底120和半导体器件110a、110b、110c和110d之间的空间突出到半导体器件110a、110b、110c和110d的外侧。从其它空间延伸的底部填充填角130d也可以与从封装基底120和半导体器件110a、110b、110c和110d之间的空间突出的底部填充填角130d整体连续。
底部填充填角130d可以在半导体器件100d的上表面上部分地暴露。例如，半导体器件100d的上表面可以存在于与模制树脂140d的上表面和底部填充填角130d的最上面的表面基本上相同的平面上。
图6是根据发明构思的示例性实施例的半导体封装件100e的剖视图。
参照图6，如参照图1A所述，底部填充填角130e可以从封装基底120和半导体器件110a、110b、110c和110d之间的空间突出到半导体器件110a、110b、110c和110d的侧表面的外侧。从其它空间延伸的底部填充填角130e也可以与从封装基底120和半导体器件110a、110b、110c和110d之间的空间突出的底部填充填角130e整体连续。
图6的半导体封装件可以与图4的半导体封装件相似，除了在图6中，半导体器件110a、110b、110c和110d的间隔H2e、H3e和H4e以及半导体器件110a和封装基底120之间的间隔H1e是均一的。
虽然间隔H1e、H2e、H3e和H4e相同，但是底部填充填角130e的突出量的差异可以由附着到半导体器件110a、110b、110c和110d的预施底部填充物的厚度的差异而引起。例如，考虑到回流期间半导体器件110a、110b、110c和110d的温度等级，预施底部填充物的厚度可以不同。例如，具有较大厚度的预施底部填充物可以施加到预计将具有相对高的温度的半导体器件110d，具有较小厚度的预施底部填充物可以施加到预计将具有相对低的温度的半导体器件110a。因此，回流之后的半导体器件110a、110b、110c和110d之间的间隔H1e、H2e、H3e和H4e可以基本上相同。
然而，在这种情况下，底部填充填角130e的突出的量可以在远离封装基底120的方向上增加。
图7A是根据发明构思的示例性实施例的半导体封装件100f的剖视图。图7B是根据发明构思的示例性实施例的图7A的放大部分B。为了清楚起见，图7A和图7B中省略了模制树脂。
在图1A和图2至图6的实施例中，NCF可以作为预施底部填充物被施加，诸如焊球或凸块的连接端子117可以被用于电连接。在图7A和图7B中，各向异性导电膜(ACF)可以被用作预施底部填充物。如图7B中所示其中导电颗粒185分布在基质膜中的ACF可以通过在导电颗粒185与焊盘115a和115b之间建立接触以形成焊盘115a和115b之间的导电路径来实现电连接。
因此，诸如焊球或凸块的连接端子可以是不必要的，可以制造薄的半导体封装件100f。
半导体器件110a、110b、110c和110d之间的间隔H2f、H3f和H4f以及半导体器件110a和封装基底120之间的间隔H1f可以基本上相同。由于焊球或凸块的回流是不必要的，并且相同厚度的ACF可以被施加到半导体器件110a、110b、110c和110d，所以H1f、H2f、H3f和H4f可以彼此相同或基本上相同。
图8是根据发明构思的示例性实施例的半导体封装件200的剖视图。
参照图8，半导体封装件200可以是其中子封装件210a、210b、210c和210d堆叠在封装基底220上的封装上封装(PoP)型半导体封装件。封装基底220可以与参照图1A描述的封装基底120基本上相同，因此省略对其重复的描述。
子封装件210a、210b、210c和210d之间的空间以及封装基底220和子封装件210a之间的空间可以被底部填充填角230填充。底部填充填角230可以从封装基底220和子封装件210a、210b、210c和210d之间的空间突出到子封装件210a、210b、210c和210d的外侧。此外，从其它空间延伸的底部填充填角230可以与从子封装件210a、210b、210c和210d延伸的底部填充填角230整体连续。
从封装基底220和子封装件210a之间的空间延伸的底部填充填角230与从子封装件210a和子封装件210b之间的空间延伸的底部填充填角230可以整体连续。从子封装件210a和子封装件210b之间的空间延伸的底部填充填角230与从子封装件210b和子封装件210c之间的空间延伸的底部填充填角230也可以整体连续。从子封装件210b和子封装件210c之间的空间延伸的底部填充填角230与从子封装件210c和子封装件210d之间的空间延伸的底部填充填角230也可以整体连续。就这一点而言，参照上面图1A描述“底部填充填角整体连续”的含义，因此省略额外的描述。
底部填充填角230的外表面(例如，从半导体封装件210a、210b、210c和210d的侧表面朝向外侧突出的表面)可以具有其中朝向外侧的突出部上下重复的形状。
子封装件210a、210b、210c和210d中的每个可以包括子封装基底212、安装在子封装基底212上的半导体芯片211、包封半导体芯片211的子模制树脂214和用来与另一个半导体器件电连接的连接端子217。半导体芯片211可以与参照图1A描述的半导体器件110基本上相同，因此省略对其的额外描述。
虽然在图8中子封装件210a、210b、210c和210d是相同的封装件，但是不同的封装件类型也可以以相同的方式封装在一起。
堆叠的子封装件210a、210b、210c和210d以及底部填充填角230可以被模制树脂240包封。
参照图1A和图2至图8描述的发明构思的示例性实施例在底部填充填角之间没有界面或边界。因此，半导体封装件的可靠性增加。另外，可以减少制造半导体封装件所花的时间和能量。因此，增加了生产量并减少了制造成本。
图9是根据发明构思的示例性实施例的半导体封装件300的剖视图。
参照图9，半导体封装件300可以是其中在封装基底320上水平地布置多个半导体器件310a和310b的半导体封装件。虽然在图9中半导体器件310a和310b中的每个形成为仅一层，但是其它半导体器件可以进一步堆叠在半导体器件310a和310b上。
封装基底320可以与参照图1A描述的封装基底120基本上相同，因此省略对其的额外描述。半导体器件310a和310b可以与图1A的半导体器件110a、110b、110c和110d基本上相同，因此省略对其的额外描述。
底部填充填角330可以在半导体器件310a和310b之间整体连续而在其间没有界面。例如，底部填充填角330可以从半导体器件310a的下部到半导体器件310b的下部整体连续而没有界面。因此，存在于半导体器件310a和封装基底320之间的底部填充填角330以及存在于半导体器件310b和封装基底320之间的底部填充填角330可以整体连续。
在发明构思的示例性实施例中，凹部350可以存在于半导体器件310a和310b之间的底部填充填角330中。这可以通过同时地回流附着到半导体器件310a的下部的预施底部填充物和附着到半导体器件310b的下部的预施底部填充物来产生。例如，在图9中，当附着到半导体器件310b的下部的预施底部填充物流向左边以与流向右边的附着到半导体器件310a的下部的预施底部填充物交汇时，可以产生凹部350。
与参照图1A和图2至图8描述的发明构思的示例性实施例相似，通过使用预施底部填充物的粘性将半导体器件310a和310b临时地附着到封装基底320上并且实施在发明构思的示例性实施例(如参照图9所述)中所描述的回流工艺，半导体器件310a和310b可以同时地结合到封装基底320上。
因此，可以减少制造半导体封装件所花的时间和能量，并且由于在底部填充填角330中不存在边界或界面，所以半导体封装件的可靠性可以增加。
图10是根据发明构思的示例性实施例制造半导体封装件的方法的流程图。图11A至图11G是用于顺序地示出根据发明构思的示例性实施例的制造半导体封装件的方法的剖视图。
参照图10、图11A和图11B，可以提供封装基底120(见图11C)与半导体器件110pre和110dpre(S100)。
参照图1A详细描述了封装基底120，因此省略对其的额外描述。
除了包括例如NCF或ACF的预施底部填充物130pre和130dpre被施加到半导体器件110pre和110dpre以外，半导体器件110pre和110dpre可以与参照图1A描述的半导体器件110相同。
如图11A中所示，预施底部填充物130pre和130dpre可以在形成半导体器件的有效表面上设置为晶片级。例如，诸如ACF或NCF的膜F可以附着到晶片W的有效表面上，可以根据划线被锯切并且可以被分成单独的半导体器件。在发明构思的示例性实施例中，可以通过这样的工艺准备半导体器件110pre和110dpre。
虽然在图11B中预施底部填充物130pre和130dpre的厚度和半导体器件110pre和110dpre的厚度相同，但是它们还可以彼此不同。如参照图6所述，预施底部填充物130pre和130dpre的厚度可以不同，使得回流之后半导体器件110pre和110dpre之间的间隔可以相同或间隔之间的差异最小化。
参照图10和图11C，半导体器件110pre可以堆叠在封装基底120上(S200)。为了在封装基底120上堆叠半导体器件110pre，半导体器件110pre的温度可以上升至第一温度T1。第一温度T1可以是例如从大约80℃至大约100℃的范围。然而，发明构思不限于此。
半导体器件110pre的温度可以上升至第一温度T1，因此可以在预施底部填充物130pre中形成较小的粘性和流动性，并且将半导体器件110pre附着到封装基底120会花费大约时间t1。
虽然在图11C中一个半导体器件110pre附着到封装基底120上，但是封装基底120可以是硅晶片，并且多个半导体器件110pre可以在水平方向(例如，X轴或Y轴方向)上以预定的间隔附着到封装基底120上。
参照图11D和图11E，可以在封装基底120上已堆叠的半导体器件110pre上堆叠额外的半导体器件110pre。半导体器件110pre可以以与参照图11C描述的相同的方式堆叠。然而，虽然在图11D和图11E中可以重复地堆叠相同的半导体器件110pre，但是在发明构思的范围内可以堆叠不同的半导体器件。
堆叠额外的半导体器件110pre花费的单独的时间可以与堆叠最下面的半导体器件110pre所花费的时间几乎相同或相近。
如图11E中所示，半导体器件110pre可以根据预施底部填充物130pre的粘性而彼此结合。因此，在这个阶段，半导体器件110pre可能不会牢固地结合。
参照图11F，在最上面的半导体器件110dpre附着到下面的半导体器件110pre的同时，最上面的半导体器件110dpre的温度可以从第一温度T1上升至第二温度T2。第二温度T2可以是执行回流的温度，可以是例如从大约220℃至大约280℃的范围。
参照图10和图11G，如果半导体器件110d的温度保持为作为回流温度的第二温度T2，同时将压力施加到半导体器件110d，则可以回流连接端子(S300)。可以考虑到回流温度、半导体器件110a、110b、110c和110d的尺寸、预施底部填充物的材料和厚度等来确定回流时间。
如参照图3所述，通过由于回流而减小半导体器件110a、110b、110c和110d之间的间隔以及半导体器件110a和封装基底120之间的间隔，可以在横向方向上形成底部填充填角130b。参照图1A和图2至图9详细描述了产生的底部填充填角130b的形状。
通过在回流完成之后停止加热和加压并且将环境温度冷却至第一温度T1或另一个合适的温度，可以固化底部填充填角130b。冷却温度并固化底部填充填角130b花费的时间t6-t5可以比将温度升高至回流温度花费的时间t4-t3长。例如，温度升高可以相对快速，而冷却和固化会花费更长的时间。
如上所述，当封装基底120是硅晶片并且半导体器件的堆叠结构沿水平方向设置时，可以以制造晶片级封装件(WLP)的方式用模制树脂同时地模制半导体器件的全部堆叠结构。例如，在半导体器件的多个堆叠结构沿着封装基底120的表面结合的同时，可以将模制树脂注入到模具中。因此，可以形成围绕半导体器件110a、110b、110c和110d以及底部填充填角130b的模制树脂。
然后，可以通过切割半导体器件的模制堆叠结构获得如图1A中所示的单个半导体封装件。
图12示出根据一种方法用于制造半导体封装件的温度曲线。参照图12，每当半导体器件在彼此上堆叠时，在第一温度T1和第二温度T2之间重复温度上升和下降/固化温度。图12示出堆叠四个半导体器件，它需要比图11G中示出的温度曲线的时间更长的时间。
根据发明构思的示例性实施例，半导体封装件可包括在数字媒体播放器、固态盘(SSD)、机动车辆、液晶显示器(LCD)或图形处理单元(GPU)中。
根据发明构思的示例性实施例，半导体封装件在底部填充填角中可以不包括边界或界面，因此可以获得高度可靠的半导体封装件。根据发明构思的示例性实施例，可以用短的时间和更少的能量来制造半导体封装件。这可以归因于用于将半导体封装件堆叠在一起的较低温度T1以及通过对于每个半导体封装件一次性地升高温度至T2以将全部的突出的底部填充填角熔化或整合到一起。因此，在相邻的底部填充填角之间可以不存在边界。因此，提高了生产量并降低了制造成本。
尽管已经参照发明构思的示例性实施例具体地示出和描述了发明构思，但是对于本领域普通技术人员明显的是，在不脱离发明构思的精神和范围的情况下，可以对其做出形式上和细节上的各种改变。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
封装基底；
多个半导体器件，堆叠在封装基底上；
多个底部填充填角，设置在所述多个半导体器件之间以及封装基底和所述多个半导体器件之间；以及
模制树脂，至少部分地围绕所述多个半导体器件和所述多个底部填充填角，
其中，所述多个底部填充填角包括从所述多个半导体器件中的每个之间或者封装基底和所述多个半导体器件中的每个之间的空间突出的多个突起，
其中，所述多个突起中的至少两个相邻的底部填充填角突起形成一个连续结构，在其间没有界面。
2.根据权利要求1所述的半导体封装件，其中，半导体封装件包括在数字媒体播放器、固态盘、机动车辆、液晶显示器或图形处理单元中。
3.根据权利要求1所述的半导体封装件，其中，界面存在于所述多个底部填充填角和模制树脂之间。
4.根据权利要求1所述的半导体封装件，其中，所述多个半导体器件之间以及封装基底和所述多个半导体器件之间的间隔对于更加远离封装基底的半导体器件变得更小。
5.根据权利要求4所述的半导体封装件，其中，所述多个底部填充填角中每个的每个突起的长度对于更加远离封装基底的底部填充填角变得更小。
6.根据权利要求5所述的半导体封装件，其中，所述多个底部填充填角中的一个的高度大于或等于所述多个半导体器件中的最上面的半导体器件的上表面的高度，
其中，均相对于封装基底的表面垂直地测量所述多个半导体器件中的最上面的半导体器件的上表面的高度和所述多个底部填充填角中的所述一个的高度。
7.根据权利要求5所述的半导体封装件，
其中，所述多个半导体器件中的最上面的半导体器件的上表面在第一平面处与模制树脂的上表面共面，
其中，所述多个底部填充填角在第一平面处被部分地暴露。
8.根据权利要求4所述的半导体封装件，其中，所述多个底部填充填角中每个的每个突起的长度对于更加远离封装基底的底部填充填角变得更大。
9.根据权利要求1所述的半导体封装件，其中，所述多个半导体器件之间以及封装基底和所述多个半导体器件之间的间隔基本上彼此相同。
10.根据权利要求9所述的半导体封装件，其中，所述多个底部填充填角中每个的每个突起的长度对于更加远离封装基底的底部填充填角变得更大。
11.根据权利要求1所述的半导体封装件，其中，所述多个底部填充填角包括非导电膜、非导电糊或各向异性导电膜。
12.根据权利要求1所述的半导体封装件，
其中，所述多个半导体器件是子封装件，其中，所述多个半导体器件中的至少一个包括半导体芯片，
其中，所述半导体封装件是封装上封装型封装件。
13.一种半导体封装件，所述半导体封装件包括：
封装基底；
多个半导体器件，堆叠在封装基底上；
多个底部填充填角，设置在所述多个半导体器件之间以及封装基底和所述多个半导体器件之间；以及
模制树脂，至少部分地围绕所述多个半导体器件和所述多个底部填充填角，
其中，所述多个半导体器件之间以及封装基底和所述多个半导体器件之间的间隔对于更加远离封装基底的半导体器件变得更小。
14.根据权利要求13所述的半导体封装件，其中，所述多个底部填充填角中至少两个相邻的底部填充填角从两个相邻的半导体器件和封装基底之间或者从三个顺序堆叠的半导体器件之间突出，
其中，所述至少两个相邻的底部填充填角的突起形成整体连续的结构。
15.根据权利要求13所述的半导体封装件，
其中，所述多个半导体器件和封装基底通过多个焊料凸块彼此电连接，
其中，所述多个焊料凸块中相对于封装基底的表面设置在第一垂直高度处的第一焊料凸块的高度大于所述多个焊料凸块中相对于封装基底的所述表面设置在第二垂直高度处的第二焊料凸块的高度，其中，第一垂直高度小于第二垂直高度。
16.一种半导体封装件，所述半导体封装件包括：
封装基底；
堆叠在封装基底上的第一半导体器件和第二半导体器件，其中，第一半导体器件设置在封装基底和第二半导体器件之间；
设置在封装基底和第一半导体器件之间的第一底部填充填角以及设置在第一半导体器件和第二半导体器件之间的第二底部填充填角；以及
模制树脂，覆盖第一底部填充填角和第二底部填充填角中每个的至少一部分，
其中，第一底部填充填角从封装基底和第一半导体器件之间的区域突出，第二底部填充填角从第一半导体器件和第二半导体器件之间的区域突出，
其中，第一底部填充填角的突起与第二底部填充填角的突起形成一个连续结构。
17.根据权利要求16所述的半导体封装件，其中，封装基底和第一半导体器件之间的第一间距等于第一半导体器件和第二半导体器件之间的第二间距，其中，沿着与封装基底的表面垂直的第一方向测量第一间距和第二间距，其中，第一底部填充填角的突起在与第一方向交叉的第二方向上比第二底部填充填角的突起短。
18.根据权利要求16所述的半导体封装件，其中，封装基底和第一半导体器件之间的第一间距大于第一半导体器件和第二半导体器件之间的第二间距，其中，沿着与封装基底的表面垂直的第一方向测量第一间距和第二间距，其中，第一底部填充填角的突起在与第一方向交叉的第二方向上比第二底部填充填角的突起短。
19.根据权利要求16所述的半导体封装件，其中，在远离第一半导体器件的边缘且与封装基底的面对第一半导体器件的表面平行的方向上，第一底部填充填角的突起比第二底部填充填角的突起长。
20.根据权利要求16所述的半导体封装件，其中，在远离第一半导体器件的边缘且与封装基底的面对第一半导体器件的表面平行的方向上，第一底部填充填角的突起与第二底部填充填角的突起基本上相等。
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US11018115B2 (en) 2021-05-25
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US20210280564A1 (en) 2021-09-09
US20190096856A1 (en) 2019-03-28
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