CN107017239A - 多芯片半导体功率封装体 - Google Patents

多芯片半导体功率封装体 Download PDF

Info

Publication number
CN107017239A
CN107017239A CN201611256982.6A CN201611256982A CN107017239A CN 107017239 A CN107017239 A CN 107017239A CN 201611256982 A CN201611256982 A CN 201611256982A CN 107017239 A CN107017239 A CN 107017239A
Authority
CN
China
Prior art keywords
semiconductor power
power device
semiconductor
electrode
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201611256982.6A
Other languages
English (en)
Inventor
M·格雷韦
S·马海因尔
A·迈泽尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN107017239A publication Critical patent/CN107017239A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49593—Battery in combination with a leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04034—Bonding areas specifically adapted for strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H01L2224/37599—Material
    • H01L2224/376—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40227—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/404—Connecting portions
    • H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
    • H01L2224/40499—Material of the auxiliary connecting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H01L2224/411—Disposition
    • H01L2224/4118—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8484—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Inverter Devices (AREA)

Abstract

半导体封装体包括：导电载体；第一层面第一半导体功率器件，具有安装在导电载体的安装表面之上的第一负载电极和相反的第二负载电极。还包括第一层面第二半导体功率器件，具有安装在安装表面之上的第一负载电极和相反的第二负载电极。第一连接夹具有连接至第一层面第一半导体功率器件的第二负载电极的第一表面和相反的安装表面。第二连接夹具有连接至第一层面第二半导体功率器件的第二负载电极的第一表面和相反的安装表面。还包括第二层面第一半导体功率器件，具有安装在第一连接元件的安装表面之上的第一负载电极和相反的第二负载电极；及第二层面第二半导体功率器件，具有安装在第二连接元件的安装表面之上的第一负载电极和相反的第二负载电极。

Description

多芯片半导体功率封装体
技术领域
本发明涉及封装技术，尤其涉及将多个半导体芯片封装成用于功率应用的层叠配置的技术。
背景技术
半导体封装体制造商不断努力以提高其产品的性能，同时降低其制造的成本。在半导体器件的制造中的成本密集区域是封装半导体芯片。所述半导体芯片可安装在诸如例如引线框架的导电载体上，并且必须产生至芯片电极和封装体的外部接触部的电连接。特别地，具有低成本的电连接和降低的电磁杂散辐射的封装体是令人期望的。
为了这些和其它的原因，有本发明的需要。
发明内容
根据本发明的第一个方面，提供了一种具有多层面布置的半导体封装体，包括：具有安装表面的导电载体；第一层面第一半导体功率器件，所述第一层面第一半导体功率器件具有安装在所述导电载体的所述安装表面之上的第一负载电极，并且具有与第一电极相反的第二负载电极；第一层面第二半导体功率器件，所述第一层面第二半导体功率器件具有安装在所述导电载体的所述安装表面之上的第一负载电极，并且具有与第一电极相反的第二负载电极；第一连接夹，所述第一连接夹具有连接至所述第一层面第一半导体功率器件的所述第二负载电极的第一表面，并且具有与所述第一表面相反的安装表面；第二连接夹，所述第二连接夹具有连接至所述第一层面第二半导体功率器件的所述第二负载电极的第一表面，并且具有与所述第一表面相反的安装表面；第二层面第一半导体功率器件，所述第二层面第一半导体功率器件具有安装在第一连接元件的安装表面之上的第一负载电极，并且具有与第一电极相反的第二负载电极；以及第二层面第二半导体功率器件，所述第二层面第二半导体功率器件具有安装在第二连接元件的安装表面之上的第一负载电极，并且具有与第一电极相反的第二负载电极。
根据本发明的一个可选的实施方式，所述第一层面第一半导体功率器件的所述第一负载电极和所述第一层面第二半导体功率器件的所述第一负载电极是源极或发射极电极。
根据本发明的一个可选的实施方式，所述第一层面第一半导体功率器件的所述第一负载电极和所述第一层面第二半导体功率器件的所述第一负载电极是漏极或集电极电极。
根据本发明的一个可选的实施方式，进一步包括：连接元件，所述连接元件电连接至所述第二层面第一半导体功率器件的所述第二负载电极并且电连接至所述第二层面第二半导体功率器件的所述第二负载电极。
根据本发明的一个可选的实施方式，所述第二层面第一半导体功率器件和所述第二层面第二半导体功率器件成行布置，所述连接元件在与所述行的方向平行的方向上延伸。
根据本发明的一个可选的实施方式，所述第二层面第一半导体功率器件和所述第二层面第二半导体功率器件成行布置，所述连接元件在与所述行的方向垂直的方向上延伸。
根据本发明的一个可选的实施方式，所述连接元件是夹。
根据本发明的一个可选的实施方式，第一层面第三半导体功率器件，所述第一层面第三半导体功率器件具有安装在所述导电载体的所述安装表面之上的第一负载电极，并且具有与所述第一负载电极相反的第二负载电极。
根据本发明的一个可选的实施方式，第三连接夹，所述第三连接夹具有连接至所述第一层面第三半导体功率器件的所述第二负载电极的第一表面，并且具有与所述第一表面相反的安装表面。
根据本发明的一个可选的实施方式，第二层面第三半导体功率器件，所述第二层面第三半导体功率器件具有安装在所述第三连接元件的所述安装表面之上的第一负载电极。
根据本发明的一个可选的实施方式，每个半导体功率器件均包括背向所述导电载体的栅极电极。
根据本发明的一个可选的实施方式，进一步包括：连接至所述连接夹的第一外部端子，其中，所有第一外部端子都沿所述半导体封装体的第一外周边布置。
根据本发明的一个可选的实施方式，进一步包括：连接至第二层面半导体功率器件的所述负载电极的一个或者一个以上的第二外部端子，其中，所述一个或者一个以上的第二外部端子沿所述半导体封装体的一个或一个以上的第二外周边布置，所述一个或一个以上的第二外周边取向为垂直于所述第一外周边。
根据本发明的一个可选的实施方式，所有栅极电极都沿半导体封装体的第三外周边布置，所述第三外周边与所述第一外周边相反。
根据本发明的第二个方面，提供了一种多相桥，包括：导电载体；安装在所述导电载体之上并且电连接至所述导电载体的多个第一层面半导体功率器件；多个连接夹，其中，每个连接夹分别安装在所述多个第一层面半导体功率器件中的相应的一个之上并且电连接至所述多个第一层面半导体功率器件中的所述相应的一个；以及多个第二层面半导体功率器件，其中，每个第二层面半导体功率器件分别安装在所述多个连接夹中的相应的一个连接夹之上。
根据本发明的一个可选的实施方式，所述多个第一层面半导体功率器件中的每个均源极在下地或者发射极在下地安装在所述导电载体上。
根据本发明的一个可选的实施方式，所述多个第二层面半导体功率器件中的每个均源极在下地或者发射极在下地安装在相应的连接夹上。
根据本发明的一个可选的实施方式，进一步包括：连接元件，所述连接元件安装在所述多个第二层面半导功率器件之上并且电连接至所述多个第二层面半导功率器件。
根据本发明的一个可选的实施方式，所述导电载体被配置为连接至外部地电位，公共连接元件被配置为连接至外部电源电位。
根据本发明的一个可选的实施方式，所述多个第一层面半导体功率器件中的每个均漏极在下地或集电极在下地安装在所述导电载体上。
根据本发明的一个可选的实施方式，所述多个第二层面半导体功率器件中的每个均漏极在下地或集电极在下地安装在相应的连接元件上。
根据本发明的一个可选的实施方式，进一步包括公共连接元件，所述公共连接元件安装在所述多个第二层面半导体功率器件之上并且电连接至所述多个第二层面半导体功率器件。
根据本发明的一个可选的实施方式，所述多个第二层面半导体功率器件成行布置，所述公共连接元件在与所述行的方向平行的方向上延伸。
根据本发明的一个可选的实施方式，所述多个第二层面半导体功率器件成行布置，所述公共连接元件在与所述行的方向垂直的方向上延伸。
根据本发明的一个可选的实施方式，进一步包括：控制半导体芯片，所述控制半导体芯片安装在所述导电载体之上，并且被配置用来控制第一层面半导体功率器件的栅极电极以及第二层面半导体功率器件的栅极电极。
附图说明
附图被包括以提供对实施例的进一步理解，并且被并入并组成本说明书的一部分。所述附图示出实施例并同描述一起起到解释实施例的原理的作用。当通过参照下文的详细描述更好地理解其他实施例和实施例的许多预期的优点时，它们将被容易地领会。附图中的各元件不一定相对彼此按比例绘制。相似的附图标记表示相应的类似部分。
图1A是示出半导体功率芯片的前侧的源极/发射极在下的半导体功率芯片的透视图。
图1B是示出半导体功率芯片的后侧的图1A中的源极/发射极在下的半导体功率芯片的透视图。
图2A是示出半导体功率芯片的前侧的漏极/集电极在下的半导体功率芯片的透视图。
图2B是示出半导体功率芯片的后侧的图2A的漏极/集电极在下的半导体功率芯片的透视图。
图3A示意性地示出具有多层面的半导体芯片布置的半导体封装体的俯视图，所述多层面的半导体芯片布置使用如图1A-B中示出的源极/发射极在下的半导体功率芯片。
图3B示意性地示出如从图3A中的视角V1所见的图3A中的半导体封装体的侧视图。
图3C示意性地示出沿图3A中的线A-A的图3A中的半导体封装体的剖视图。
图4是如例如图3A-C中示出的二相桥的电路图。
图5A示意性地示出具有多层面的半导体芯片布置的半导体封装体的俯视图，所述多层面的半导体芯片布置使用如图1A-B中示出的源极/发射极在下的半导体功率芯片。
图5B示意性地示出如从图5A中的视角V1所见的图5A中的半导体封装体的侧视图。
图5C示意性地示出沿图5A中的线A-A的图5A中的半导体封装体的剖视图。
图6是如例如图5A-C中示出的三相桥的电路图。
图7A示意性地示出具有多层面的半导体芯片布置的半导体封装体的俯视图，所述多层面的半导体芯片布置使用如图2A-B中的示出的漏极/集电极在下的半导体功率芯片。
图7B示意性地示出如从图7A中的视角V1所见的图7A中的半导体封装体的侧视图。
图7C示意性地示出如从图7A中的视角V2所见的图7A中的半导体封装体的侧视图。
图8示意性地示出具有多层面的半导体芯片布置的半导体封装体的俯视图，所述多层面的半导体芯片布置使用如图1A-B中示出的源极/发射极在下的半导体功率芯片和控制半导体芯片。
具体实施方式
在下文的详细描述中，参考了构成本文的一部分的附图，并且在附图中通过图示的方式示出可实践本公开的具体实施例。在这方面，诸如“顶部”、“底部”、“前”、“后”、“上”、“下”等等的方向性术语是参照被描述的附图的取向来使用的。因为各种实施例中使用的部件可以多种不同的取向放置，因此方向性术语是为图示的目的使用而绝非是限制的目的。应该理解的是，可使用其他实施例并且在不背离本发明的范围的情况下可做出结构或逻辑上的变化。因此下文的详细描述不应以限制的意义理解，本发明的范围由所附权利要求限定。
应该理解的是，除非特别声明，否则本文所描述的各种示例性实施例的特征可彼此结合起来。
如本说明书中使用的，术语“耦接的”和/或“连接的”通常并不旨在于意味着元件必须直接地耦接或连接在一起。可在“耦接的”或“连接的”元件之间提供中间元件。然而，尽管不限制于那种意义，但是术语“耦接的”和/或“连接的”也可被理解为可选地公开以下方面：元件直接地耦接或连接在一起，而没有在“耦接的”或“连接的”元件之间提供中间元件。
本文描述了包括四个或四个以上的功率半导体器件的半导体功率封装体。所述功率半导体器件被布置在至少两个层面x(低层面)和y(高层面)中。至少两个半导体功率器件布置在低层面x中。
封装体中的所有半导体功率器件或其中至少一部分可具有垂直结构，就是说半导体器件可以这样一种方式被制造使得电流可在与半导体芯片的主表面垂直的方向上流动，半导体功率器件在所述半导体芯片中实施。具有垂直结构的半导体功率器件在半导体芯片中实施，所述半导体芯片具有在其两个主表面上的，就是说在其顶侧和底侧上的电极。半导体芯片可包括一个或一个以上的半导体器件，即一个或一个以上的半导体器件可整体集成在一个半导体芯片中。
垂直功率半导体器件可例如被配置为MOSFET(Metal Oxide SemiconductorField Effect Transistors：金属氧化物半导体场效应晶体管)、IGBT(Insulated GateBipolar Transistors：绝缘栅双极型晶体管)、JFET(Junction Gate Field EffectTransistors：结栅场效应晶体管)、HEMT(High Electron Mobility Transistors：高电子迁移率晶体管)或功率双极晶体管。举例来说，功率MOSFET(IGBT)的源极(发射极)电极可布置在一个主表面上，而功率MOSFET(IGBT)的漏极(集电极)电极可布置在另一主表面上。MOSFET(IGBT)的栅极电极可布置在布置有MOSFET(IGBT)的源极(发射极)的主表面上，或布置在布置有MOSFET(IGBT)的漏极(集电极)的主表面上。
本文所指的功率半导体器件可由特定的半导体材料制造，诸如由例如Si、SiC、SiGe、GaAs、GaN、AlGaN、InGaAs、InAlAs等等制造，并且另外可包括非半导体的无机的和/或有机的材料。布置在封装体内的功率半导体器件可以为不同类型并且可通过不同技术制造。
两个或两个以上的半导体功率器件(其可整体集成在一个或一个以上的半导体芯片中)安装在封装体的导电载体之上并电连接至封装体的导电载体。在一个实施例中，导电载体可以是连续的金属板或片，诸如例如引线框架的芯片焊盘。所述金属板或片可由例如铜或铜合金的任何金属或金属合金制成。在其他实施例中，导电载体可例如包括涂覆有金属层的陶瓷板。举例来说，这种导电载体可以是结合有金属的陶瓷衬底，例如DCB(覆铜)陶瓷衬底。
另外，本文描述的半导体封装体可包括一个或一个以上的逻辑集成电路以控制功率半导体器件。所述逻辑集成电路可包括一个或一个以上的驱动电路以驱动一个或一个以上的功率半导体器件。逻辑集成电路可例如是微控制器，其包括例如存储电路、电平转换器等等。
导电载体和/或半导体功率芯片(半导体功率器件在其内实施)可至少部分地被包围或嵌入至少一种电绝缘材料中。所述电绝缘材料形成封装体的包封体本体。所述包封体本体可包括模制材料或由模制材料制成。可采用各种技术，例如压缩模制、注射模制、粉末模制或液体模制来形成模制材料的包封体本体。包封体本体可形成封装体的外围的一部分，即可至少部分地限定半导体封装体的形状。
电绝缘材料可以包括或由热固性材料或热塑性材料制成。热固性材料可例如基于环氧树脂形成。热塑性材料可例如包括聚醚酰亚胺(PEI：polyetherimide)、聚醚砜(PES：polyether-sulfone)、聚苯硫醚(PPS：polyphenylene-sulfide)或聚酰胺-酰亚胺(PAI：polyamide-imide)所组成的组中的一种或一种以上的材料。热塑性材料通过在模制或层压期间施加压力和热量而熔化，在冷却和压力释放时(可逆地)硬化。
形成包封体本体的电绝缘材料可包括聚合物材料或由聚合物材料制成。电绝缘材料可包括填充的或未填充的模制材料、填充或未填充的热塑性材料、填充或未填充的热固性材料、填充或未填充的层压体、纤维增强层压体、纤维增强聚合物层压体和具有填料颗粒的纤维增强聚合物层压体中的至少一种。
可以通过本文所描述的技术来设计各种不同类型的功率封装体。例如，本文所公开的功率封装体可包括两个半桥电路，每个半桥电路均包括高压侧功率晶体管和低压侧功率晶体管。另外，作为示例，本文所公开的功率封装体可以包括三个或甚至三个以上的半桥电路，每个半桥电路均包括高压侧功率晶体管和低压侧功率晶体管。
如本文所描述的功率封装体可例如被配置为多相桥。这种多相桥可被配置以使用于电源中，例如用于电动机的电源中，所述电动机例如是无刷直流(BLDC：brushless DC)电动机。本文所描述的多相桥也可用作整流器或电力变换器，例如DC-DC电力变换器或AC-DC电力变换器。
图1示出源极/发射极在下的半导体功率芯片10。所述源极/发射极在下的半导体功率芯片10具有第一表面10_1和与所述第一表面10_1相反的第二表面10_2。第一表面10_1代表源极/发射极在下的半导体功率芯片10的后侧，第二表面10_2代表源极/发射极在下的半导体功率芯片10的前侧。
源极或发射极(S/E)电极11布置在源极/发射极在下的半导体功率芯片10的第一表面10_1(后侧)上。漏极或集电极(D/C)电极12和栅极(G)电极13布置在源极/发射极在下的半导体功率芯片10的第二表面10_2(前侧)上。栅极电极13用于控制S/E电极11与D/C电极12之间的电流。栅极电极13可用于切换S/E电极11与D/C电极12之间的电流为导通或关断，或者调整S/E电极11与D/C电极12之间的电流至基本上是0A(安培)与源极/发射极在下的半导体功率芯片10被接通时所建立的最大电流之间的一可调节值。
源极/发射极在下的半导体功率芯片10可包括N个半导体功率器件，其中N是等于或大于1的整数。在这种情况下，源极/发射极在下的半导体功率芯片10可具有由所有半导体功率器件共用的一个公共的S/E电极11、N个D/C电极12(即，每个半导体功率器件一个D/C电极)和N个栅极电极13(即，每个半导体功率器件一个栅极电极13)。
图2示出漏极/集电极在下的半导体功率芯片20。所述漏极/集电极在下的半导体功率芯片20具有第一表面20_1和与所述第一表面20_1相反的第二表面20_2。第一表面20_1代表漏极/集电极在下的半导体功率芯片20的后侧，第二表面20_2表示漏极/集电极在下的半导体功率芯片20的前侧。
漏极或集电极(D/C)电极21布置在漏极/集电极在下的半导体功率芯片20的第一表面20_1(后侧)上。源极或发射极(S/E)电极22和栅极(G)电极23布置在漏极/集电极在下的半导体功率芯片20的第二表面20_2(前侧)上。栅极电极23用于控制D/C电极21与S/E电极22之间的电流。栅电极23可用于切换D/C电极21与S/E电极22之间的电流为导通或关断，或者调整D/C电极21与S/E电极22之间的电流至基本上是0A与如果漏极/集电极在下的半导体功率芯片20被接通所建立的最大电流之间的一可调节值。
与图1A-B中源极/发射极在下的半导体功率芯片10类似，漏极/集电极在下的半导体功率芯片20也可包括N个半导体功率器件。在这种情况下，漏极/集电极在下的半导体功率芯片20可具有由所有半导体功率器件共用的一个公共D/C电极21、N个S/E电极22(即，每个半导体功率器件一个S/E电极)和N个栅极电极23(即，每个半导体功率器件一个栅极电极23)。
图3A-C示出依照本文所描述的实施例的半导体功率封装体300。所述半导体功率封装体300包括导电载体310。所述导电载体310可以是例如引线框架的金属载体。在其他示例中，导电载体310可以是在其顶表面或其两个表面上涂覆有金属层的陶瓷板。导电载体310的顶表面可形成导电载体310的安装表面311。
下文中，放置在安装表面311上的半导体功率器件将被称为层面x(或第一层面)半导体功率器件。如可在图3A-C中看出的，层面x第一半导体功率器件320和层面x第二半导体功率器件321安装在导电载体310的安装表面311之上。
层面x第一和第二半导体功率器件320、321可均由如图1A-B中示出的源极/发射极在下的半导体功率芯片10形成。在这种情况下，两个源极/发射极在下的半导体功率芯片10可彼此相邻布置。每个源极/发射极在下的半导体功率芯片10具有第一表面10_1，其包括安装在安装表面311上的S/E电极11。在另一个示例中，层面x第一半导体功率器件320和层面x第二半导体功率器件321都整体地集成在一个源极/发射极在下的半导体功率芯片10中。在这种情况下，该单个源极/发射极在下的半导体功率芯片10可设置有位于其第一表面10_1处的公共的S/E电极11以及还设有两个D/C电极12和两个栅极电极13，即，一个D/C电极12和一个栅极电极13用于层面x第一和第二半导体功率器件310、321这两个中的相应的一个。
通常，如果N个层面x半导体功率器件320、321、…被安装在导电载体310的安装表面311上，那么源极/发射极在下的半导体功率芯片10(层面x半导体功率器件设施在其中)的数量可在1至N的范围内。图3C中，具有一个或者两个源极/发射极在下的半导体功率芯片10的选择通过虚线分隔线P表示出来。
第一连接夹330安装在层面x第一半导体功率器件320的D/C电极12之上，第二连接夹331安装在层面x第二半导体功率器件321的D/C电极12之上。第一和第二连接夹330、331均导电，例如由金属材料制成。第一和第二连接夹330、331分别电连接至相应的层面x第一或第二半导体功率器件320和321的各自的D/C电极12。
第一连接夹330具有安装表面332，其与连接至层面x第一半导体功率器件320的D/C电极12的夹表面相反。类似地，第二连接夹331具有安装表面333，其与连接至层面x第二半导体功率器件321的D/C电极12的表面相反。
如图3B中示出的，第一连接夹330和/或第二连接夹331可具有与源极/发射极在下的半导体功率芯片10的主表面10_1、10_2基本上平行延伸的第一部分，并且可具有分别向下引导至半导体功率封装体300的外部端子312和313的弯曲部分。所述外部端子312、313可位于与导电载体310相同的平面中。作为示例，导电载体310可形成引线框架的芯片焊盘，外部端子312、313可形成同一引线框架的端子焊盘(或端子引线)。
第一连接夹330和第二连接夹331的安装表面332、333可分别限定用于放置半导体功率芯片的第二层面y。具体而言，层面y第一半导体功率器件340可安装在第一连接夹330的安装表面332之上，层面y第二半导体功率器件341可安装在第二连接夹331的安装表面333之上。
层面y第一半导体功率器件340和层面y第二半导体功率器件341可如结合图1A-B所解释的那样均实施于源极/发射极在下的半导体功率芯片10中。因此，层面y第一半导体功率器件340的S/E电极11电连接至第一连接夹330的安装表面332，层面y第二半导体功率器件341的S/E电极11电连接至第二连接夹331的安装表面333。
层面y第一和第二半导体功率器件340、341的D/C电极12可通过连接元件350彼此电连接。所述连接元件350可例如是如图3A-C中示出的连接夹。
更具体地，连接元件350可具有板的形状，其在源极/发射极在下的半导体功率芯片10的第二表面10_2之上平行延伸，所述源极/发射极在下的半导体功率芯片10分别实现层面y第一半导体功率器件340和层面y第二半导体功率器件341。该板可具有被配置用来将连接元件350连接至半导体封装体300的外部端子315的弯曲部分。与外部端子312、313类似，所述外部端子315可例如由引线框架的引线焊盘或引线形成，所述引线框架还用于导电载体310。应该注意的是，连接元件350还可通过连接夹之外的实施方式形成，例如通过导电带或焊线形成。
如图3A-B中示出的，半导体封装体300可包括另外的外部端子Gx1、Gx2、Gy1和Gy2。外部端子Gx1可电连接至层面x第一半导体功率器件320的栅极电极13，外部端子Gx2可电连接至层面x第二半导体功率器件321，外部端子Gy1可电连接至层面y第一半导体功率器件340的栅极电极13，以及外部端子Gy2可电连接至层面y第二半导体功率器件341。所有前述的从栅极电极13至外部端子Gx1、Gx2、Gy1、Gy2的连接可例如通过焊线进行。替代地，也可使用(栅极)连接夹用于形成这些连接。在这种情况下，有可能的是通过连接夹来建立封装体300的整个电互连(这也可适用于本文公开的任何封装体)。
另外，外部端子Gx1、Gx2、Gy1、Gy2可与导电载体310和/或外部端子312、313、315位于同一平面中。作为示例，外部端子Gx1、Gx2、Gy1、Gy2可通过引线框架的焊盘或引线形成，所述引线框架也用于导电载体(作为引线框架的芯片焊盘)和外部端子312、313、315(作为引线框架的引线或焊盘)。
参考图3A，层面y第一半导体功率器件340和层面y第二半导体功率器件341可沿维度D1成行布置。连接元件350从一端(连接至层面y第一和第二半导体功率器件340、341的D/C电极12的一端)沿垂直于维度D1的维度D2延伸至另一端，即连接至外部端子315的一端。第一连接夹330和第二连接夹331也可沿维度D2延伸，然而，是在与连接元件350相比相反的方向上延伸。鉴于此，外部端子312和313可布置在封装体300的与布置外部端子315的外周边相反的外周边处。
仍然参照图3A，外部端子Gx1和Gx2(连接至层面x上的栅极电极13)可布置在封装体300的与外部端子315相同的外周边处。类似地，外部端子Gy1和Gy2(连接至层面y上的栅极电极13)可布置在封装体300的与外部端子312、313相同的外周边处。这样，半导体功率封装体300的仅两个外周边配备有外部端子，而剩下的两侧可以没有外部端子。由于如图3A-C中示出的那样，封装体的布线互连，因而半导体封装体可以非常紧凑，即在维度D1和D2上小。同时，半导体封装体300的覆盖区中的大部分(例如等于或大于所述覆盖区面积的50％、60％、70％、80％或90％)可由导电载体310形成，这可实现从封装体300至诸如例如PCB(印刷电路板)或散热器的外部安装平台(未示出)的良好的热消散。
半导体功率封装体300可形成2相桥。图4中示出2相桥的电路图的一个示例。所述2相桥包括两个半桥。第一半桥包括在负电源电压(例如地：GND)401与正电源电压(例如电池：BAT)402之间串联连接的低压侧开关LS1和高压侧开关HS1。第二半桥包括在负电源电压401与正电源电压402之间串联连接的低压侧开关LS2和高压侧开关HS2。低压侧开关LS1和LS2的控制电极(例如栅极电极)分别连接至节点403和404。高压侧开关HS1和HS2的控制电极(例如栅极电极)分别连接至节点405和406。第一半桥的低压侧开关LS1与高压侧开关HS1之间的连接部被连接至节点412。第二半桥的低压侧开关LS2与高压侧开关HS2之间的连接部被连接至节点413。
图4中示出的示例中，低压侧开关LS1、LS2和高压侧开关HS1、HS2例如通过MOSFET实施。在这种情况下，节点412连接至LS1的漏极和HS1的源极，节点413连接至LS2的漏极和HS2的源极。然而，也有可能的是低压侧开关LS1、LS2和高压侧开关HS1和HS2例如通过IGBT实施。在这种情况下，电路图将与图4中的电路图类似，但除了IGBT替代了MOSFET外。此时，节点412将连接至LS1的集电极和HS1的发射极，节点413将连接至LS2的集电极和HS2的发射极。
如通过将图4中的电路图与图3A-C中示出的半导体功率封装体300进行比较而可理解的，导电载体310相应于节点401，层面x第一和第二半导体功率器件320、321分别相应于LS1和LS2，第一连接夹330和第二连接夹331分别相应于节点412和节点413，层面y第一和第二半导体功率器件340、341分别相应于HS1和HS2，外部端子Gx1、Gx2、Gy1、Gy2分别相应于节点403、节点404、节点405和节点406，以及外部端子315相应于节点402。
外部端子312、313(相应于图4中的电路图的节点412、413)代表半导体功率封装体300的输出端子。作为示例，外部端子312可电连接至由半导体功率封装体300供电的外部装置(例如电动机)的第一相输入，外部端子313可电连接至第二相输入。
应该注意的是，导电载体310、层面x第一和第二半导体功率器件320、321、第一和第二连接夹330、331、层面y第一和第二半导体功率器件340、341、和连接元件350之间的电连接可通过焊接，例如软焊接、硬焊接、扩散焊接，或通过诸如烧结、利用导电粘附剂的粘合等任何其它合适的连接方法形成。
另外，应该注意的是，半导体功率封装体300可设置有密封剂，其用于半导体功率封装体300的本体并且包围图3A-C中示出的布置结构。然而，导电载体310的底部表面(即与所述导电载体310的安装表面311相反的表面)和外部端子312、313、314、Gx1、Gx2、Gy1、Gy2的底部表面或形成这些外部端子的引线可暴露于密封剂或从密封剂突出出来。
图5A-5C示出一种半导体功率封装体500。所述半导体功率封装体500是三相桥的一个示例，该三相桥由三个半桥而不是由以半导体功率封装体300为例的两个半桥组成。除此以及将在下文中进一步做出更加详细地解释的其他区别之外，半导体功率封装体500与半导体功率封装体300类似，可参看上文的描述以避免重复。
半导体功率封装体500附加地包括层面x第三半导体功率器件522，其与层面x第一和第二半导体功率器件320、321在同一源极/发射极在下的半导体功率芯片10中实施，或者在单独的源极/发射极在下的半导体功率芯片10中实施。层面x第一、第二和第三半导体功率器件320、321、522可布置在沿维度D1延伸的行中。
层面x第三半导体功率器件522连接至第三连接夹532，所述第三连接夹532安装在相应的源极/发射极在下的半导体功率芯片10的第二表面10_2之上并且连接至它的D/C电极12。第一、第二和第三连接夹330、331和532也布置在沿维度D1延伸的行中。
层面y第三半导体功率器件542安装在第三连接夹532上。参见图5A-B，层面y第三半导体功率器件542可通过源极/发射极在下的半导体功率芯片10实施。
图5A-B中显而易见的是，层面y第一、第二和第三半导体功率器件340、341、542的栅极电极13位于相应的芯片的左侧处，即靠近层面x第一、第二和第三半导体功率器件320、321、542的栅极电极13。这样，外部端子Gx1、Gy1、Gx2、Gy2、Gx3(连接至层面x第三半导体功率器件542的栅极电极13)和Gy3(连接至层面y第三半导体功率器件542的栅极电极13)可沿半导体功率封装体500的外周边布置在沿维度D1延伸的行中。就是说，连接至栅极电极13的所有外部端子都可沿半导体功率封装体500的一个外周边布置。
连接元件550安装在层面y第一、第二和第三半导体功率器件340、341、542的D/C电极12之上并且电连接至层面y第一、第二和第三半导体功率器件340、341、542的D/C电极12。所述连接元件550可类似于连接元件350(例如可通过连接夹形成)并且可参考上文的描述。然而，在这此示例中，连接元件550在维度D1上跨越半导体功率封装体500，从半导体封装体的一个外周边跨越至它的相反的外周边。因此，连接元件550可沿维度D1延伸而非如半导体功率封装体300的示例中示出的那样沿维度D2延伸。
类似于半导体功率封装体300，输出外部端子312、313和附加的输出外部端子514沿封装体本体的右外周边布置。在此示例中，没有外部栅极端子沿半导体功率封装体500的这一边布置。因此半导体功率封装体500可具有专有地布置在封装体本体(沿维度D1延伸)的右外周边处的外部输出端子312、312、514，专有地布置在封装体本体的相反外周边处的栅极外部端子Gx1、Gy1、Gx2、Gy2、Gx3、Gy3，以及外部端子515，所述外部端子515沿着封装体的沿维度D2延伸的外周边中的一侧或者两侧布置。
在半导体功率封装体500中，高压外部端子(正电源电压在外部端子315处，输出相在外部端子312、313、514处)在空间上与低压外部端子Gx1、Gy1、Gx2、Gy2、Gx3、Gy3分开。这有助于提供半导体功率封装体500所需的介电强度，并且从PCB布局的角度来看可能进一步是有利的。
根据示出了三相桥的一个示例电路图的图6，第三半桥通过低压侧开关LS3和高压侧开关HS3实施。相输出连接至低压侧开关LS3的漏极，高压侧开关HS3的源极连接至输出节点614。低压侧开关LS3的栅极连接至节点605，高压侧开关HS3的栅极连接至节点607。关于图5A-C中的半导体功率封装体500，节点605相应于外部端子Gx3，节点607相应于外部端子Gy3以及输出节点614相应于外部端子514。此外，如先前与图4结合所提到的，如果期望的话，图6中的MOSFET可由IGBT替代。
在如图3A-C和5A-C中示出的半导体功率封装体300、500的示例中，许多不同的特征是可互换的，其意义为半导体功率封装体500的一种特定特征可被功率封装体300的相应的特定(不同的)特征替换，反之亦然。作为示例，半导体功率封装体500的沿维度D1延伸的连接元件550可替换半导体功率封装体300中作为示例使用的连接元件350。此外，半导体功率封装体300的外部端子Gy1和Gy2可被设计成与半导体功率封装体500中的相应的外部端子的布置相类似，布置在同一个外周边处并且邻近外部端子Gx1和Gx2。在这种情况下，功率封装体300的层面y第一和第二半导体功率器件340、341可如功率封装体500中那样以相同的方式取向。简单地说，半导体功率封装体300可被设计成在功率封装体500的覆盖区和配置(除了第三半桥不存在)方面，与半导体功率封装体500部分地或者完全相同。反之亦然，有可能的是，半导体功率封装体500与半导体功率封装体300(并且通过添加第三半桥所需的部件)的相应的特征设计得一致。
另外，对于半导体功率封装体300和500，通过示例的方式所描述的布置方式和思想可扩展至具有超过三个半桥的多相桥。将半导体功率封装体300和500扩展(或者使用半导体功率封装体300中的一些特征和半导体功率封装体500中的一些特征的“混合”功率封装体)至N相桥是显而易见的，并且为了简洁起见省略了上文公开中的重复。
图7A-C示出半导体功率封装体700。半导体功率封装体700类似于半导体功率封装体300，并且可参考上文的描述以避免重复。然而，在半导体功率封装体700中，层面x第一和第二半导体功率器件320、321中的一部分或者全部和层面y第一或第二半导体功率器件340、341中的一部分或者全部如图2A-B中示出的那样，通过漏极/集电极在下的半导体功率芯片20实施。鉴于此，D/C电极21现位于半导体功率芯片20的(底)后侧20_1，S/E电极22和栅极电极23现位于半导体功率芯片20的(顶)前侧20_2。如本领域技术人员所公知的，这是对半导体功率芯片的普通的或“经典的”设计。
另外，半导体功率封装体700示出一个示例，在该示例中连接元件550与半导体封装体500的连接元件550类似，沿维度D1延伸。另外，低压外部端子Gx1、Gy1、Gx2、Gy2和高压外部端子312、313以及导电载体310处的正电源电压在空间上的分离与半导体功率封装体500类似，并且可参考上文的描述以避免重复。
由于漏极/集电极在下的半导体功率芯片20使用于半导体封装体700中，因此图4中的电路图与半导体功率封装体700的部件的对应如下：第一半桥的低压侧开关LS1和高压侧开关HS1分别相应于层面y第一半导体功率器件340和层面x第一半导体功率器件320。第二半桥的低压侧开关LS2和高压侧开关HS2分别相应于层面y第二半导体功率器件341和层面x第二半导体功率器件321。节点412和413分别相应于外部端子312和313。节点403、404、405、406分别相应于外部(栅极)端子Gy1、Gy2、Gx1和Gx2。电源电压节点401(负电源电压)和402(正电源电压)分别相应于外部端子515和导电载体310。
应当注意的是，半导体功率封装体700可替代地依照半导体功率封装体300的配置形成，即，具有沿维度D2延伸的连接元件350并且具有外部端子Gx1、Gy1、Gx2、Gy2、312、313、315，它们依照半导体功率封装体300沿封装体本体的外周边布置。
图8示出半导体功率封装体800。半导体功率封装体800与半导体功率封装体500类似，并且可参考上文的公开以避免重复。与半导体功率封装体500不同的是，层面x第一、第二和第三半导体功率器件320、321、522的栅极电极13和层面y第一、第二和第三半导体功率器件340、341、542的栅极电极13至少部分地连接至控制集成电路(control IC：controlintegrated circuit)810而非连接至半导体功率封装体800的外部端子Gx1、Gy1、Gx2、Gy2、Gx3、Gy3。控制IC 810可安装在导电载体310上。控制IC 810可部分地或者全部嵌入形成半导体功率封装体800的本体的密封剂(未示出)中。在图8中示出的示例中，导电载体310连接至例如地(GND)的负电源电压401。因此，控制IC 810可直接结合至导电载体310上，而在之间无需任何绝缘层。
控制IC 810可包括许多栅极驱动器，例如图8中示出的示例中的6个栅极驱动器。控制IC 810可还包括逻辑器件以控制栅极驱动器。控制IC 810可还包括输入焊盘，其电连接至半导体功率封装体800的外部端子812、813、814。所述外部端子812、813、814可沿维度D1和/或维度D2布置在半导体功率封装体800的外周边处。外部端子812、813、814可通过前述的引线框架的端子焊盘或引线形成，所述引线框架也用于导电载体310(芯片焊盘)和外部端子312、313、514和515。通过例如焊线被连接至控制IC 810的输入焊盘的外部端子812、813、814可接收诸如例如PWM(pulse width modulated：脉冲宽度调制)信号的外部输入信号。
应该注意的是，半导体功率封装体300、500和700可也与半导体功率封装体800类似，配备有控制IC 810。然而，如果使用漏极/集电极在下的半导体功率芯片20而非源极/发射极在下的半导体功率芯片10，那么控制IC 810通过在导电载体与控制IC 810之间延伸的绝缘层(未示出)与导电载体310电绝缘。
进一步地，在本文公开的所有实施例中，第一、第二和第三连接夹330、331、532和/或连接元件350、550可配备通孔830。所述通孔830可在半导体功率封装体300、500、700、800的制造过程中，例如在用于将半导体芯片10或20连接至连接夹330、331、532和/或连接元件350、550的焊料回流过程期间，起到排气孔的作用。另外，第一、第二和第三连接夹330、331、532的通孔830可用于连接夹330、331、532的上表面(安装表面332、333)与底表面之间的焊料交换。
更进一步地，在本文所公开的所有实施例中，可在半导体功率封装体300、500、700、800的外部端子与低压侧开关LS1、LS2、…、LSN的漏极D之间提供电连接(例如焊线)。这些端子可作为用于外部电路的电压感测端子使用。
如本文所描述的半导体功率封装体300、500、700、800可在车辆工程中具有特别的应用。作为示例，半导体功率封装体300、500、700、800可被配置用来为使用于在燃料泵、水泵中的或使用于电驱动涡轮增压器中的电动机(例如BLDC)供电。
如本文所描述的半导体功率封装体300、500、700、800可提供例如1W至500W，尤其是等于或大于或小于10W、50W、200W、200W、300W或400W的输出功率。如本文所描述的半导体功率封装体300、500、700、800可提供例如0.1A至100A，尤其是等于或大于或小于1A、10A、30A、50A、70A或90A的输出电流。在运行中，高于或低于5V、10V、50V、100V、200V或500V的电压可被施加在节点401与402之间。N桥的切换频率可在100Hz至100MHz的范围内，但也可在这个范围之外。
所有的半导体功率封装体300、500、700、800提供了空间优化的封装体布局。进一步地，所有的半导体功率封装体300、500、700、800提供了低杂散阻抗而减少寄生能量损失，沿半导体功率封装体300、500、700、800的外周的外部端子的良好分布而允许高散热能力。
尽管本文已经示出并描述具体实施例，但是本领域的普通技术人员将意识到，在不背离本发明的范围的情况下，各种替代的和/或等同的实施方式可替代示出并描述的具体实施例。本申请旨在于覆盖本文所讨论的具体实施例的任何改变或变化。因此，本发明旨在于仅由权利要求及其等同方案限定。

Claims (25)

1.一种具有多层面布置的半导体封装体，包括：
具有安装表面的导电载体；
第一层面第一半导体功率器件，所述第一层面第一半导体功率器件具有安装在所述导电载体的所述安装表面之上的第一负载电极，并且具有与第一电极相反的第二负载电极；
第一层面第二半导体功率器件，所述第一层面第二半导体功率器件具有安装在所述导电载体的所述安装表面之上的第一负载电极，并且具有与第一电极相反的第二负载电极；
第一连接夹，所述第一连接夹具有连接至所述第一层面第一半导体功率器件的所述第二负载电极的第一表面，并且具有与所述第一表面相反的安装表面；
第二连接夹，所述第二连接夹具有连接至所述第一层面第二半导体功率器件的所述第二负载电极的第一表面，并且具有与所述第一表面相反的安装表面；
第二层面第一半导体功率器件，所述第二层面第一半导体功率器件具有安装在第一连接元件的安装表面之上的第一负载电极，并且具有与第一电极相反的第二负载电极；以及
第二层面第二半导体功率器件，所述第二层面第二半导体功率器件具有安装在第二连接元件的安装表面之上的第一负载电极，并且具有与第一电极相反的第二负载电极。
2.根据权利要求1所述的半导体封装体，其中，所述第一层面第一半导体功率器件的所述第一负载电极和所述第一层面第二半导体功率器件的所述第一负载电极是源极或发射极电极。
3.根据权利要求1所述的半导体封装体，其中，所述第一层面第一半导体功率器件的所述第一负载电极和所述第一层面第二半导体功率器件的所述第一负载电极是漏极或集电极电极。
4.根据前述权利要求中任一项所述的半导体封装体，进一步包括：
连接元件，所述连接元件电连接至所述第二层面第一半导体功率器件的所述第二负载电极并且电连接至所述第二层面第二半导体功率器件的所述第二负载电极。
5.根据权利要求4所述的半导体封装体，其中，所述第二层面第一半导体功率器件和所述第二层面第二半导体功率器件成行布置，所述连接元件在与所述行的方向平行的方向上延伸。
6.根据权利要求4所述的半导体封装体，其中，所述第二层面第一半导体功率器件和所述第二层面第二半导体功率器件成行布置，所述连接元件在与所述行的方向垂直的方向上延伸。
7.根据权利要求4至6中任一项所述的半导体封装体，其中，所述连接元件是夹。
8.根据前述权利要求中任一项所述的半导体封装体，进一步包括：
第一层面第三半导体功率器件，所述第一层面第三半导体功率器件具有安装在所述导电载体的所述安装表面之上的第一负载电极，并且具有与所述第一负载电极相反的第二负载电极。
9.根据权利要求8所述的半导体封装体，进一步包括：
第三连接夹，所述第三连接夹具有连接至所述第一层面第三半导体功率器件的所述第二负载电极的第一表面，并且具有与所述第一表面相反的安装表面。
10.根据权利要求9所述的半导体封装体，进一步包括：
第二层面第三半导体功率器件，所述第二层面第三半导体功率器件具有安装在所述第三连接元件的所述安装表面之上的第一负载电极。
11.根据前述权利要求中任一项所述的半导体封装体，其中，每个半导体功率器件均包括背向所述导电载体的栅极电极。
12.根据前述权利要求中任一项所述的半导体封装体，进一步包括：
连接至所述连接夹的第一外部端子，其中，所有第一外部端子都沿所述半导体封装体的第一外周边布置。
13.根据权利要求12所述的半导体封装体，进一步包括：
连接至第二层面半导体功率器件的所述负载电极的一个或者一个以上的第二外部端子，其中，所述一个或者一个以上的第二外部端子沿所述半导体封装体的一个或一个以上的第二外周边布置，所述一个或一个以上的第二外周边取向为垂直于所述第一外周边。
14.根据前述权利要求中任一项所述的半导体封装体，其中，所有栅极电极都沿半导体封装体的第三外周边布置，所述第三外周边与所述第一外周边相反。
15.一种多相桥，包括：
导电载体；
安装在所述导电载体之上并且电连接至所述导电载体的多个第一层面半导体功率器件；
多个连接夹，其中，每个连接夹分别安装在所述多个第一层面半导体功率器件中的相应的一个之上并且电连接至所述多个第一层面半导体功率器件中的所述相应的一个；以及
多个第二层面半导体功率器件，其中，每个第二层面半导体功率器件分别安装在所述多个连接夹中的相应的一个连接夹之上。
16.根据权利要求15所述的多相桥，其中，所述多个第一层面半导体功率器件中的每个均源极在下地或者发射极在下地安装在所述导电载体上。
17.根据权利要求15或16所述的多相桥，其中，所述多个第二层面半导体功率器件中的每个均源极在下地或者发射极在下地安装在相应的连接夹上。
18.根据权利要求15至17中任一项所述的多相桥，进一步包括：
连接元件，所述连接元件安装在所述多个第二层面半导功率器件之上并且电连接至所述多个第二层面半导功率器件。
19.根据权利要求18所述的多相桥，其中，所述导电载体被配置为连接至外部地电位，公共连接元件被配置为连接至外部电源电位。
20.根据权利要求15所述的多相桥，其中，所述多个第一层面半导体功率器件中的每个均漏极在下地或集电极在下地安装在所述导电载体上。
21.根据权利要求15或20所述的多相桥，其中，所述多个第二层面半导体功率器件中的每个均漏极在下地或集电极在下地安装在相应的连接元件上。
22.根据权利要求15至21中任一项所述的多相桥，进一步包括公共连接元件，所述公共连接元件安装在所述多个第二层面半导体功率器件之上并且电连接至所述多个第二层面半导体功率器件。
23.根据权利要求22所述的多相桥，其中，所述多个第二层面半导体功率器件成行布置，所述公共连接元件在与所述行的方向平行的方向上延伸。
24.根据权利要求22所述的多相桥，其中，所述多个第二层面半导体功率器件成行布置，所述公共连接元件在与所述行的方向垂直的方向上延伸。
25.根据权利要求15至24中任一项所述的多相桥，进一步包括：
控制半导体芯片，所述控制半导体芯片安装在所述导电载体之上，并且被配置用来控制第一层面半导体功率器件的栅极电极以及第二层面半导体功率器件的栅极电极。
CN201611256982.6A 2016-01-27 2016-12-30 多芯片半导体功率封装体 Pending CN107017239A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102016101433.8 2016-01-27
DE102016101433.8A DE102016101433A1 (de) 2016-01-27 2016-01-27 Multi-Chip-Halbleiterleistungsgehäuse

Publications (1)

Publication Number Publication Date
CN107017239A true CN107017239A (zh) 2017-08-04

Family

ID=59295689

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611256982.6A Pending CN107017239A (zh) 2016-01-27 2016-12-30 多芯片半导体功率封装体

Country Status (3)

Country Link
US (1) US20170213783A1 (zh)
CN (1) CN107017239A (zh)
DE (1) DE102016101433A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110148566A (zh) * 2019-06-03 2019-08-20 珠海格力电器股份有限公司 一种堆叠结构的智能功率模块及其制造方法
CN111463188A (zh) * 2020-05-03 2020-07-28 矽力杰半导体技术(杭州)有限公司 应用于功率转换器的封装结构
TWI757143B (zh) * 2020-04-07 2022-03-01 美商克里菲亞特維拉公司 功率模組

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10396018B2 (en) 2017-11-27 2019-08-27 Infineon Technologies Ag Multi-phase half bridge driver package and methods of manufacture
FR3074994B1 (fr) * 2017-12-07 2019-12-20 Legrand France Procede d'assemblage d'un variateur de lumiere
US11721617B2 (en) 2020-04-07 2023-08-08 Wolfspeed, Inc. Power module
US20230343683A1 (en) * 2022-04-26 2023-10-26 Nxp Usa, Inc. Semiconductor device with embedded battery and method therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103534805A (zh) * 2011-05-16 2014-01-22 丰田自动车株式会社 功率模块
US20140306332A1 (en) * 2013-04-11 2014-10-16 Texas Instruments Incorporated Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips
CN104603948A (zh) * 2012-09-05 2015-05-06 德克萨斯仪器股份有限公司 垂直堆叠的功率fet和具有低导通电阻的同步降压转换器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10009171B4 (de) * 2000-02-26 2005-08-11 Robert Bosch Gmbh Stromrichter und sein Herstellverfahren
US7042086B2 (en) * 2002-10-16 2006-05-09 Nissan Motor Co., Ltd. Stacked semiconductor module and assembling method of the same
US7271470B1 (en) * 2006-05-31 2007-09-18 Infineon Technologies Ag Electronic component having at least two semiconductor power devices
US9515060B2 (en) * 2013-03-20 2016-12-06 Infineon Technologies Austria Ag Multi-chip semiconductor power device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103534805A (zh) * 2011-05-16 2014-01-22 丰田自动车株式会社 功率模块
CN104603948A (zh) * 2012-09-05 2015-05-06 德克萨斯仪器股份有限公司 垂直堆叠的功率fet和具有低导通电阻的同步降压转换器
US20140306332A1 (en) * 2013-04-11 2014-10-16 Texas Instruments Incorporated Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110148566A (zh) * 2019-06-03 2019-08-20 珠海格力电器股份有限公司 一种堆叠结构的智能功率模块及其制造方法
CN110148566B (zh) * 2019-06-03 2020-12-25 珠海零边界集成电路有限公司 一种堆叠结构的智能功率模块及其制造方法
TWI757143B (zh) * 2020-04-07 2022-03-01 美商克里菲亞特維拉公司 功率模組
CN111463188A (zh) * 2020-05-03 2020-07-28 矽力杰半导体技术(杭州)有限公司 应用于功率转换器的封装结构

Also Published As

Publication number Publication date
US20170213783A1 (en) 2017-07-27
DE102016101433A1 (de) 2017-07-27

Similar Documents

Publication Publication Date Title
CN107017239A (zh) 多芯片半导体功率封装体
US10734911B2 (en) Power module including multiple signal wiring patterns disposed on an insulating substrate
US11037847B2 (en) Method of manufacturing semiconductor module and semiconductor module
US8497572B2 (en) Semiconductor module and method of manufacturing the same
CN104412383B (zh) 半导体装置以及半导体装置的连接构造
CN106158839B (zh) 半导体器件
CN108511396B (zh) 电子装置
CN110998838B (zh) 半导体模块
CN104637891B (zh) 包括两个半导体模块和横向延伸连接器的半导体封装
US9312211B2 (en) Semiconductor device and manufacturing method thereof
CN107731779B (zh) 电子装置
EP2851950A1 (en) Power semiconductor module
US10319671B2 (en) Semiconductor package with leadframe
CN108933124B (zh) 电子装置
CN107799484A (zh) 具有重复的覆盖区模的半导体芯片封装
CN104701308B (zh) 电子器件
CN107768355A (zh) 单侧功率装置封装体
CN107275316A (zh) 具有源极在下配置的晶体管管芯和漏极在下配置的晶体管管芯的半导体封装
CN113140551A (zh) 空间高效且低寄生的半桥
CN106024773B (zh) 包括多层级载体的化合物半导体装置
JP7142784B2 (ja) 電気回路装置
CN107154396A (zh) 功率半导体封装体及其应用
WO2020240882A1 (ja) 半導体装置および半導体装置の製造方法
WO2019150870A1 (ja) 半導体モジュール
JP3242736U (ja) 電力半導体モジュール

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20170804

WD01 Invention patent application deemed withdrawn after publication