CN106992163A - 具有防焊盘剥离结构的半导体器件和相关方法 - Google Patents

具有防焊盘剥离结构的半导体器件和相关方法 Download PDF

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Publication number
CN106992163A
CN106992163A CN201610836377.XA CN201610836377A CN106992163A CN 106992163 A CN106992163 A CN 106992163A CN 201610836377 A CN201610836377 A CN 201610836377A CN 106992163 A CN106992163 A CN 106992163A
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China
Prior art keywords
pad
tsv
groove
conductive layer
substrate
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CN201610836377.XA
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English (en)
Inventor
郑志楷
谢政杰
黄诗雯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN106992163A publication Critical patent/CN106992163A/zh
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Abstract

公开了一种具有防焊盘剥离结构的半导体器件。该半导体器件包括具有衬底穿孔(TSV)的半导体衬底；半导体衬底上且包括其中的多个凹槽的介电层；以及位于半导体衬底之上以覆盖介电层部分和延伸至凹槽的焊盘；其中，焊盘延伸至多个凹槽，以及在焊盘和导电层之间的凹槽中限制多个接触点，以及当自上向下角度看时，每个接触点至少部分地被排除在TSV的边界之外。本发明实施例涉及具有防焊盘剥离结构的半导体器件和相关方法。

Description

具有防焊盘剥离结构的半导体器件和相关方法
技术领域
本发明实施例涉及具有防焊盘剥离结构的半导体器件和相关方法。
背景技术
半导体器件的焊盘用作半导体器件的内部电路和半导体器件外侧的外部电路之间的连接接口。在现代的半导体器件封装技术中，在晶圆上形成半导体器件之后，晶圆必须被切割成管芯。结果，执行管芯接合工艺之后，接下来执行引线接合工艺以电连接具有金属引线的半导体器件的外部电路和导电焊盘。结果，执行模制操作以完成整个半导体器件封装工艺。
典型的导电焊盘通常为矩形或正方形。因此，尤其在接合工艺(或焊接工艺)期间在导电焊盘的拐角处可能发生高电平应力。应力可能造成导电焊盘剥离且进一步损坏导电焊盘下方的半导体器件。
发明内容
根据本发明的一个实施例，提供了一种具有防焊盘剥离结构的半导体器件，包括：半导体衬底，包括衬底穿孔；介电层，位于所述半导体衬底上并且所述介电层中包括多个凹槽；以及焊盘，位于所述半导体衬底之上以覆盖所述介电层的部分并且所述焊盘延伸至所述凹槽，其中，从顶视图看，所述焊盘完全地覆盖所述衬底穿孔，且所述焊盘的边缘和所述凹槽的最外侧边缘之间的距离大于指定的长度。
根据本发明的另一实施例，还提供了一种半导体器件，包括：半导体衬底，包括衬底穿孔；导电层，位于所述衬底穿孔上；介电层，位于所述半导体衬底上以及所述介电层中包括多个凹槽；以及焊盘，位于所述半导体衬底之上以覆盖所述介电层的部分；其中，所述焊盘延伸至所述多个凹槽，且多个接触点限制在位于所述焊盘和所述导电层之间的所述凹槽中，以及当从顶视图看时，所述接触点的每个至少部分地排除在所述衬底穿孔的边界之外。
根据本发明的又一实施例，还提供了一种用于制造具有防焊盘剥离结构的半导体器件的方法，包括：提供包括衬底穿孔的半导体衬底；在所述半导体衬底上形成介电层；在所述介电层中形成多个穿孔；以及在所述半导体衬底之上形成焊盘以覆盖所述介电层的至少部分且填充所述穿孔；其中，当从顶视图看时，所述焊盘的至少部分与所述衬底穿孔重叠。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1至图5是根据本发明的示例性实施例的用于示出制造具有防焊盘剥离结构的半导体器件的流程的截面示意图；
图6是根据本发明的示例性实施例的图3的示意性顶视图；
图7是根据本发明的示例性实施例的图5的示意性顶视图；
图8至图12是根据本发明的另一实施例的用于示出制造具有防焊盘剥离结构的半导体器件的流程的截面示意图；
图13是根据本发明的另一实施例的图10的示意性顶视图；
图14是根据本发明的另一实施例的图12的示意性顶视图；
图15是根据本发明的又一实施例的图12的示意性顶视图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
尽管提出本发明宽泛范围的数值范围和参数设定是近似值，在特定实例中的数值设定被尽可能精确地报告。任何数值，然而，固有地包含某些必然误差，该误差由各自的测试测量结果中发现的标准偏差产生。同样，正如此处使用的术语“约”一般指在给定值或范围的10％、5％、1％或0.5％内。或者，术语“约”意思是在本领域普通的技术人员可以考虑到的可接受的平均标准误差内。除了在操作/工作实例中，或者除非明确指出，否则应该理解，通过术语“大约”修改所有示例中的所有的数值范围、数量、值和百分比(诸如用于本文所公开的材料的数量、持续时间、温度、操作条件、比率大小等)。因此，除非有相反规定，本发明和所附权利要求所记载的数值参数设定是可以根据要求改变的近似值。至少，每个数值参数应该至少被解释为根据被报告的有效数字的数目，并应用普通的四舍五入技术。此处范围可以表示为从一个端点到另一个端点或在两个端点之间。此处公开的所有范围包括端点，除非另有说明。
图1至图5是根据本发明的示例性实施例的用于示出制造具有防焊盘剥离结构的半导体器件的流程的截面示意图。首先，参照图1，提供半导体衬底100，其中，已经形成有源电路结构。衬底100可以包括块状硅衬底。可选地，衬底100可以由包括以下材料：元素半导体，诸如晶体结构的硅或锗；化合物半导体，诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；或它们的组合。在一些实施例中，衬底可以包括绝缘体上硅(SOI)衬底。使用注氧隔离(SIMOX)、晶圆接合和/或其他合适的方法制造SOI衬底。
应该理解，为了简化附图，在图1中仅描述有源电路结构的矩形的导电层102，并且没有示出有源电路结构的所有器件。本领域的技术人员应该知道有源电路结构包括例如多个半导体组件和多个半导体金属互连件。在本发明中，导电层102代表半导体衬底100中的有源电路结构中的层。导电层102从半导体衬底的顶面100a暴露出。导电层102提供表面102a作为用于与半导体衬底100外部的组件任何连接的电接触终端。在一些实施例中，导电层102位于有源电路结构的最上水平面中。
导电层102优选地包括铜(Cu)和具有约5千埃(KA)至10KA的厚度。导电层102在衬底穿孔(TSV)103上方形成且电连接至衬底穿孔(TSV)103。TSV 103纵向穿过半导体衬底100。在该实施例中，TSV是由铜材料或具有超导电性的其它材料组成的。大体地，TSV是垂直电连接件，即完全地穿过硅晶圆或管芯的通孔。与为了至少若干原因的诸如叠层封装的可选方式相比，TSV是用作替代引线接合和翻转芯片以产生3D封装件和3D集成电路的高性能互连技术。原因之一是因为通孔的密度可以设计为比引线或球栅接合形式的接触件密度高。此外，原因之一是由通孔连接的导电路径可以设计为比引线接合形式或球栅接合形式短。在含有两个或更多芯片(集成电路)的TSV 3D封装件(封装件中系统、芯片堆叠MCM等)中，含有TSV的衬底用于在封装件中将多个芯片连接在一起。3D集成电路(3D IC)是通过堆叠硅晶圆和/或管芯并且垂直地互连它们从而使得它们表现为单个器件的单个集成电路。通过使用TSV技术，3D IC可以在一个小的“覆盖区”内获得大量的功能。堆叠件中的不同的器件可以是异质的，例如将CMOS逻辑、DRAM和III-V族材料组合至单个IC内。此外，可以大幅缩短通过器件的关键电气路径，导致更快的操作速度。
TSV 103具有两端，其中，一端103a从衬底100的外表面100b暴露出。外表面100b与表面100a相对。暴露端103a设计为连接至衬底100外部的组件或电路。与端103a相对的另一端103b与导电层102接触。TSV 103和导电层102在衬底100中且穿过衬底100形成导电路径。因此，可以在表面100a上方的任何电路或表面100b下方的任何电路之间实现电通信。从而在3D封装件中互连。
参照图2，通过任何合适的工艺在半导体衬底100和导电层102上形成介电层104。介电层104可以由介电材料组成，诸如氧化硅、氮化硅、氮氧化硅、高k介电材料、其他合适的介电材料和/或它们的组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料和/或它们的组合。然而，这并不是对本发明的限定。
如图3所示，在介电层104中形成凹槽106和108。在介电层104中形成凹槽106和108。每个凹槽具有基本上沿着TSV 103的纵向测量的深度h。由于在制造操作期间的一些误差，可能在不同凹槽之间具有稍微变化。但是，每个凹槽的对应的深度h足够大以暴露出表面102a的至少部分。TSV 103具有在TSV 103之上设置的至少一个凹槽(主题实施例中的两个凹槽)，但是凹槽与不足(underpaid)的TSV部分地重叠。以凹槽106为例，凹槽106位于TSV103上方但是具有在TSV 103的侧壁103e上方横向突出的表面106a。另一方面，凹槽106的表面106b位于TSV 103上面且横向地位于侧壁103e的边界内。以与凹槽106相似的方式在TSV103的相对侧壁103f之上设置凹槽108。
结合图6仍然参照图3，图6是根据本发明的示意性实施例的图3的示意性顶视图。图3是沿图6的线6-6'截取的半导体的截面示意图。如图6所示，凹槽106、108和凹槽110-120基本上是四边形，且TSV 103的边界大约为圆形。暴露出凹槽中的导电层102(阴影部分)。边界113由虚线描述是因为它由导电层102覆盖。特别地，凹槽106、108、110和112被形成为与TSV 103的侧壁的部分重叠。当从顶面看时，凹槽114至120形成在TSV 103的边界113的外侧且不与TSV 103重叠。因此，部分重叠的凹槽(诸如106或108)和不重叠的凹槽(诸如114或120)均不完全地形成在边界113内部。
例如，形成凹槽106至120的方法是在图2的介电层104上形成图案化的光刻胶层(未示出)。图案化的光刻胶层的图案暴露出介电层104的表面的八个基本上为四边形的区域。然后，图案化的光刻胶层用作掩模以蚀刻暴露的介电层104。蚀刻停止在导电层102处以及实施凹槽106至120的形成。
请注意，这不旨在为本发明限制于此处所示的实例。在一些其它实施例中，图6的凹槽106至120可以是其它类型的形状。例如，凹槽106至120的形状可以是多边形。在另一实例中，凹槽106至120的形状可以是圆形或椭圆形。
参照图4，在半导体衬底100之上形成焊盘122以电连接导电层102。焊盘122覆盖介电层104的部分且延伸至凹槽106至120(由于截面角度，在图4中仅描述凹槽106和108)。焊盘122可以完全地或部分地重叠导电层102和TSV 103。在该实施例中，当从顶视图看时，焊盘完全地覆盖TSV 103的区域。请注意，焊盘122可以完全地或至少部分地填充凹槽106至120。在该实施例中，例如，焊盘122是厚焊盘，且焊盘122具有约20KA(千埃)至约40KA的厚度。焊盘122可以包括由例如铝(AL)组成的金属层。例如，形成焊盘122的方法是在半导体衬底100之上形成铝金属层(未示出)，从而覆盖整个介电层104且填满凹槽106至120。然后，在铝金属层上形成图案化的光刻胶层(未示出)，从而暴露出大约在对应的导电层102之上的理想位置之上的铝金属层。之后，图案化的光刻胶层用作掩模以蚀刻暴露的铝金属层，从而完成焊盘122的形成。
焊盘122的在凹槽106至120中形成的部分提供接触件以通过焊盘122的在凹槽106至120中的部分电连接至导电层102。焊盘122、导电层102、和TSV 103一起形成导电路径以在表面100a上方或表面100b下方设置的组件之间传达电通信。导电路径是堆叠结构且相对位置的布置可以根据堆叠的层之间的应力相互作用改变。例如，如图4所示，焊盘122布置为不完全地与导电层102接触。焊盘122和导电层102之间的接触点限制在凹槽106和108中。除了导电焊盘122，导电层102的部分还与介电层104接触。换言之，导电层102的顶面102a同时与导电焊盘122的导电材料和介电层104的介电材料接触。
本发明中提到的另一相互关系是焊盘122和TSV 103之间的相对位置。即使焊盘122不与TSV 103接触，但是，从顶视图看，焊盘122和TSV 103之间的相对位置也是本发明中考虑的一个要素。因为图6中的凹槽106和108不完全地位于TSV 103的边界内，因此从图4中的顶视图看，焊盘122和导电层102之间的接触点也不完全地位于TSV 103的边界内。因此，在一些实施例中，焊盘122位于TSV 103上方且完全地覆盖TSV 103,其中，插入的导电层102是焊盘122和TSV 103之间的连接件。然而，焊盘122和导电层102之间的接触点都不完全地在TSV 103的边界内。换言之，从顶视图，焊盘122和导电层102之间的完全内部的接触点被排除在焊盘122和TSV 103之间的重叠区域之外。
参照图4A，在一些实施例中，在衬底100和介电层104之间可辨识另一介电层104a。介电层104a可以由介电材料组成，诸如氧化硅、氮化硅、氮氧化硅、高k或低k介电材料、其他合适的介电材料和/或它们的组合。导电层102由介电层104a围绕。为了一些其它实施例，为了简洁，可以省略介电层104和介电层104a之间的界线。
参照图5，形成保护层124以覆盖介电层104的表面和焊盘122的侧壁122a和122b的部分。保护层124可以由绝缘材料组成。保护层包括以下任何合适的材料：包括氧化硅、蓝宝石、其他合适的绝缘材料和/或它们的组合。示例性的保护层可以包括埋氧层(BOX)。通过任何合适的工艺形成保护层，诸如注入(如，SIMOX)、氧化、沉积和/或其他合适的工艺。请注意，这不旨在为本发明限制于此处所示的实例。保护层124覆盖焊盘122的边缘，因此加强焊盘122(尤其用于焊盘122的拐角)的接合。一旦已经沉积了保护层124，可以在随后的操作中执行接下来的引线接合操作从而通过形成焊线(未示出)电连接外部电路和焊盘122。随后的操作还包括模制操作以完成半导体器件封装工艺。由于本领域的技术人员已知随后的引线接合和模制操作，且本发明关注在引线接合和模制操作之前的操作和结构，为了简洁将在此不再描述关于随后操作的细节。
应该注意，与其中整个焊盘接触或电连接至内部电路的常规技术不同，在本发明的方法中，仅在开口中形成的焊盘的一部分用于将整个焊盘电连接至内部电路。请结合图7参照图5，图7是根据本发明的示意性实施例的图5的示意性顶视图。相对地，图5是沿图7的线7-7截取的半导体的截面示意图。如图7所示，由于在TSV 103的中心区域正上方的位置承受由深TSV 103和厚焊盘122的结构诱导的极高的应力，因此在TSV 103的内部没有凹槽。如图7所示，为了防止这样的应力影响焊盘122和导电层102之间的整个导电性，本发明的所有凹槽106至120远离TSV 103的中心区域且至少至横跨TSV 103的侧壁的位置。
具体地，从图7的顶视图看，不超过开口区域的约50％与TSV 103的覆盖区重叠。在该实施例中，凹槽106、108、110和112的每个的不到约50％的区域与TSV 103重叠。以这样的方式，可以避免由深TSV 103和厚焊盘122诱导的高应力被转移至厚焊盘122，其中，可以有效地避免焊盘122的剥离。
此外，在随后的引线接合操作期间，由于布线之后向上的张力，焊盘122的拐角通常承受高应力。高应力有可能从焊盘122的边缘沿着焊盘122被转移至凹槽106至120。来自焊盘122的边缘的应力可以造成凹槽106至120中的连接部分从导电层102剥离，并且构成称为分层的焊盘剥离的高风险，以及还损坏焊盘122下方的有源电路结构。在该实施例中，公开了厚焊盘122的边缘和凹槽106至120的最外侧之间的更长的距离以解决上述问题。特别地，如图7所示，厚焊盘122的每个边缘和凹槽106至120的最外侧边缘之间的距离L大于约2um。在一些实施例中，厚焊盘122的距离L和厚度的比值可以为从约0.2至约2。
当在图7的实例中应用同一拉伸应力测试条件时，可以观察到，与现有技术半导体器件相比，在图7的示例性半导体器件中可以显著地减小铝焊盘的剥离。因此，可以使用图7的示例性半导体器件改善铝焊盘和下面的导电层之间的电和机械接合的稳定性。因此，与现有技术的半导体器件相比，图7的示例性半导体器件已经改善了可靠性。
此外，与常规技术的方法相比，本发明的工艺不复杂。实际上，本发明中不需要额外的操作或掩模。以下示出了防止本发明的实施例的焊盘剥离的结构。
图8至图12是根据本发明的另一实施例的用于示出制造具有防焊盘剥离结构的半导体器件的流程的截面示意图。在图8中，提供半导体衬底800，其中，已经形成有源电路结构。衬底800是由与衬底100相同或相似的材料组成的。应该理解，为了简化附图，在图8中仅描述有源电路结构的矩形的导电层802，并且没有示出有源电路结构中的所有器件。本领域的技术人员应该知道有源电路结构包括例如多个半导体组件和多个半导体金属互连件。在本发明中，导电层802代表半导体衬底800中的有源电路结构中的层。导电层802从半导体衬底的顶面800a暴露出。导电层802提供表面802a作为用于与半导体衬底800外部的组件任何连接的电接触终端。在一些实施例中，导电层802位于有源电路结构的最上水平面中。
导电层802优选地包括铜和具有约5KA至10KA的厚度。导电层802在TSV 801和803上方形成且电连接至TSV 801和803。TSV 801和803纵向穿过半导体衬底800。在该实施例中，TSV是具有超导电性的铜材料组成的。TSV 801的一端801a和TSV 803的一端803a从衬底800的外部表面800b暴露。外表面800b与表面800a相对。暴露端801a和803a设计为连接至衬底800外部的一个或多个组件或电路。分别与端801a和803a相对的TSV 801的另一端801b和TSV 803的另一端803b与导电层802接触。TSV 801和803与导电层802在衬底800中且穿过衬底800形成导电路径。因此，可以在表面800a上方的任何电路或表面800b下方的任何电路之间实现电通信。从而在3D封装件中互连。
参照图9，通过任何合适的工艺在半导体衬底800和导电层802上形成介电层804。介电层804可以由介电材料组成，诸如氧化硅、氮化硅、氮氧化硅、高k介电材料、其他合适的介电材料和/或它们的组合。
如图10所示，在介电层804中形成凹槽806和814。在介电层804中形成凹槽806、808、812和814。每个凹槽具有基本上沿着TSV 801和803的纵向测量的深度h。由于在制造操作期间的一些误差，可能在不同凹槽之间具有稍微变化。但是，每个凹槽的对应的深度h足够大以暴露出表面802a的至少部分。TSV 801和803的每个具有在其之上设置的至少一个凹槽(主题实施例中的两个凹槽对应每个TSV)但是凹槽与对应的很少的TSV部分地重叠。以凹槽806为例，凹槽806位于TSV 801上方但是具有在TSV801的侧壁801e上方横向突出的表面806a。另一方面，凹槽806的表面806b位于TSV 801上面且横向地位于侧壁801e的边界内。以与凹槽806相似的方式在TSV 801的相对侧壁801f之上设置凹槽808。此外，以与凹槽806和808相似的方式，在TSV 803的两个侧壁之上设置凹槽812和814。
结合图13仍然参照图10，图13是根据本发明的另一实施例的图10的示意性顶视图。图10是沿图13的线13-13截取的半导体的截面示意图。如图13所示，凹槽806至842基本上是四边形的，且TSV 801的边界811和TSV 803的边界813大约是圆形的。暴露出凹槽中的导电层802(阴影部分)。边界811和813由虚线描述是因为它由导电层102覆盖。特别地，凹槽806、808、812、814、818、826、832和840被形成为与TSV 801和803的侧壁的部分重叠。凹槽810、816、820、822、824、828、830、834、836、838和842形成在TSV 801和803的边界811和813外侧且当从顶视图看时不与TSV 801和803重叠。因此，部分重叠的凹槽(诸如806或812)和不重叠的凹槽(诸如816或842)均不完全地形成在边界811和813内部。
例如，形成凹槽806至842的方法是通过在图9的介电层804上形成图案化的光刻胶层(未示出)。图案化的光刻胶层的图案暴露出介电层804的表面的八个基本上是四边形的区域。然后，图案化的光刻胶层用作掩模以蚀刻暴露的介电层804。蚀刻停止在导电层802处且实施凹槽806至842的形成。在一些其它实施例中，图13的凹槽806-842可以是其它类型的形状。例如，凹槽806-842的形状可以是多边形。在另一实例中，凹槽806-842的形状可以是圆形或椭圆形。
参照图11，在半导体衬底800之上形成焊盘844以电连接导电层802。焊盘844覆盖介电层804且延伸至凹槽806至842(由于截面角度，在图11中仅描述凹槽806至814)。焊盘844可以完全地或部分地重叠导电层802和TSV 801和803。在该实施例中，当从顶视图看时，焊盘844完全地覆盖TSV 801和803的区域。请注意，焊盘844可以完全地或至少部分地填充凹槽806至814。在该实施例中，例如，焊盘844是厚焊盘，且焊盘844具有约20KA至约40KA的厚度。焊盘844可以包括由例如铝组成的金属层。例如，形成焊盘844的方法是通过在半导体衬底800之上形成铝金属层(未示出)，从而覆盖整个介电层804且填满凹槽806至842。然后，在铝金属层上形成图案化的光刻胶层(未示出)，从而暴露出大约在对应的导电层802之上的理想位置之上的铝金属层。之后，图案化的光刻胶层用作掩模以蚀刻暴露的铝金属层，从而完成该焊盘844形成。
焊盘844的在凹槽806至842中形成的部分提供功能以通过焊盘844的在凹槽806至842中的部分电连接至导电层802。
参照图12，形成保护层846以覆盖介电层804的表面和焊盘844的侧壁844a和844b的部分。保护层846可以由绝缘材料组成。保护层包括以下任何合适的材料，包括氧化硅、蓝宝石、其他合适的绝缘材料和/或它们的组合。示例性的保护层可以包括埋氧层(BOX)。通过任何合适的工艺形成保护层，诸如注入(如，SIMOX)、氧化、沉积和/或其他合适的工艺。请注意，这不旨在为本发明限制于此处所示的实例。保护层846覆盖焊盘844的边缘，因此加强焊盘844(尤其用于焊盘844的拐角)的接合。一旦已经沉积了保护层846，可以在随后的操作中执行接下来的引线接合操作从而通过形成焊线(未示出)电连接外部电路和焊盘844。
请结合图14仍然参照图12。图14是根据本发明的另一实施例的图12的示意性顶视图。相对地，图12是沿图14的线14-14截取的半导体的截面示意图。如图14所示，由于在TSV801和803的中心区域正上方的位置承受由深TSV 801和803以及厚焊盘844的结构诱导的极高的应力，因此在TSV 801和803的内部没有凹槽。如图14所示，为了防止这样的应力影响焊盘844和导电层802之间的整个导电性，本发明的所有凹槽806至842远离TSV 801和803的中心区域且至少至横跨TSV 801和803的侧壁的位置。
类似于图7，凹槽806、808、812、814、818、826、832和840的每个的不到约50％的区域与TSV 801和803重叠。以这样的方式，可以避免由深TSV 801和803以及厚焊盘844诱导的高应力被转移至厚焊盘844，其中，可以有效地避免焊盘844的剥离。此外，如图14所示，厚焊盘844的边缘的最外侧与凹槽806、814、816、818、820、822、824、826、828、830、832、834、836、838、840和842的最外侧之间的距离L大于约2um。在一些实施例中，厚焊盘844的距离L和厚度的比值可以为从约0.2至约2。
与图5中示出的单个TSV对一个焊盘结构相比，双TSV对一个焊盘结构具有在位于焊盘844的更宽的长度附近的TSV 801和803的边缘上方的凹槽(即，图14的凹槽818、826、832和840)处的焊盘部分上方形成的额外的拉伸应力。图15是根据本发明的另一实施例的图12的示意性顶视图。如可以从图15所见，去除TSV 801和803的位于焊盘844的更宽长度附近的边缘上方的凹槽以避免额外的拉伸应力的效应。当在图15的实例中应用同一拉伸应力测试条件时，可以观察到，与图14相比，进一步减小了铝焊盘的剥离。因此，当一个焊盘结构放置在TSV行上方时，可以使用图15的半导体器件进一步改善铝焊盘和下面的导电层之间的电和机械接合的稳定性。
本发明的一些实施例提供一种具有防焊盘剥离结构的半导体器件。该半导体器件包括具有衬底穿孔(TSV)的半导体衬底；介电层，位于半导体衬底上且介电层中包括多个凹槽；以及位于半导体衬底之上以覆盖介电层的部分且延伸至凹槽的焊盘；其中，从顶视图栏，焊盘完全覆盖TSV，且焊盘的每个边缘和凹槽的最外侧边缘之间的距离大于指定的长度。
在本发明的一些实施例中，该方法还包括TSV上的导电层；其中，焊盘通过凹槽电连接至导电层使得焊盘电连接至TSV。
在本发明的一些实施例中，该方法还包括介电层上的保护层以覆盖焊盘的侧壁的至少部分。
在本发明的一些实施例中，导电层包括铜(Cu)。
在本发明的一些实施例中，指定的长度为约2um。
在本发明的一些实施例中，当从顶视图看时，对于与TSV重叠的每个开口，重叠比率小于开口的区域的指定的比率。
在本发明的一些实施例中，指定的比率为约50％。
在本发明的一些实施例中，焊盘包括铝(AL)。
本发明的一些实施例提供了一种具有防焊盘剥离结构的半导体器件。该半导体器件包括具有衬底穿孔(TSV)的半导体衬底；位于TSV上的导电层；介电层，位于半导体衬底上且介电层中包括多个凹槽；以及位于半导体衬底之上以覆盖介电层部分的焊盘；其中，焊盘延伸至多个凹槽，以及多个接触点限制在焊盘和导电层之间的凹槽中，以及当从顶视图看时，每个接触点至少部分地被排除在TSV的边界之外。
在本发明的一些实施例中，焊盘和导电层包括不同的金属。
在本发明的一些实施例中，焊盘通过接触点和导电层电连接至TSV。
在本发明的一些实施例中，当从顶视图看时，凹槽的至少部分与TSV部分地重叠。
在本发明的一些实施例中，当从顶视图看时，焊盘的每个边缘和接触点的最外侧边缘之间的距离大于约2um。
在本发明的一些实施例中，当从顶视图看时，对于与TSV重叠的每个接触点，重叠比率小于接触点的区域的约50％。
在本发明的一些实施例中，导电层位于TSV上方且完全地覆盖TSV。
在本发明的一些实施例中，焊盘位于TSV上方且完全地覆盖TSV。
在本发明的一些实施例中，导电层包括铜(Cu)，且焊盘包括铝(AL)。
本发明的一些实施例提供了一种用于制造具有防焊盘剥离结构的半导体器件的方法。该方法包括：提供包括衬底穿孔(TSV)的半导体衬底；在半导体衬底上形成介电层；在介电层中形成多个凹槽；以及在半导体衬底之上形成焊盘以覆盖介电层的至少部分且填充凹槽；其中，当从顶视图看时，焊盘的至少部分与TSV重叠。
在本发明的一些实施例中，该方法还包括TSV上形成导电层；其中，焊盘通过凹槽电连接至导电层使得焊盘电连接至TSV。
在本发明的一些实施例中，该方法还包括在介电层上形成保护层以覆盖焊盘的侧壁的至少部分。
根据本发明的一个实施例，提供了一种具有防焊盘剥离结构的半导体器件，包括：半导体衬底，包括衬底穿孔；介电层，位于所述半导体衬底上并且所述介电层中包括多个凹槽；以及焊盘，位于所述半导体衬底之上以覆盖所述介电层的部分并且所述焊盘延伸至所述凹槽，其中，从顶视图看，所述焊盘完全地覆盖所述衬底穿孔，且所述焊盘的边缘和所述凹槽的最外侧边缘之间的距离大于指定的长度。
在上述半导体器件中，还包括：导电层，位于所述衬底穿孔上；其中，所述焊盘穿过所述凹槽延伸至所述导电层以使所述焊盘电连接至所述衬底穿孔。
在上述半导体器件中，还包括：保护层，位于所述介电层上以覆盖所述焊盘的侧壁的至少部分。
在上述半导体器件中，所述导电层包括铜(Cu)。
在上述半导体器件中，所述指定的长度为2um。
在上述半导体器件中，从所述顶视图看，每个凹槽与所述衬底穿孔部分地重叠，且重叠比率小于所述凹槽的区域的指定的比率。
在上述半导体器件中，所述指定的比率为50％。
在上述半导体器件中，所述焊盘包括铝(Al)。
根据本发明的另一实施例，还提供了一种半导体器件，包括：半导体衬底，包括衬底穿孔；导电层，位于所述衬底穿孔上；介电层，位于所述半导体衬底上以及所述介电层中包括多个凹槽；以及焊盘，位于所述半导体衬底之上以覆盖所述介电层的部分；其中，所述焊盘延伸至所述多个凹槽，且多个接触点限制在位于所述焊盘和所述导电层之间的所述凹槽中，以及当从顶视图看时，所述接触点的每个至少部分地排除在所述衬底穿孔的边界之外。
在上述半导体器件中，所述焊盘和所述导电层包括不同的金属。
在上述半导体器件中，所述焊盘通过所述接触点和所述导电层电连接至所述衬底穿孔。
在上述半导体器件中，当从所述顶视图看时，所述凹槽的至少部分与所述衬底穿孔部分地重叠。
在上述半导体器件中，当从所述顶视图看时，所述焊盘的每个边缘和所述接触点的所述最外侧边缘之间的距离大于2um。
在上述半导体器件中，当从所述顶视图看时，对于与所述衬底穿孔重叠的每个接触点，重叠比率小于所述接触点的区域的50％。
在上述半导体器件中，所述导电层位于所述衬底穿孔上方且完全地覆盖所述衬底穿孔。
在上述半导体器件中，所述焊盘位于所述衬底穿孔上方且完全地覆盖所述衬底穿孔。
在上述半导体器件中，所述导电层包括铜(Cu)，且所述焊盘包括铝(Al)。
根据本发明的又一实施例，还提供了一种用于制造具有防焊盘剥离结构的半导体器件的方法，包括：提供包括衬底穿孔的半导体衬底；在所述半导体衬底上形成介电层；在所述介电层中形成多个穿孔；以及在所述半导体衬底之上形成焊盘以覆盖所述介电层的至少部分且填充所述穿孔；其中，当从顶视图看时，所述焊盘的至少部分与所述衬底穿孔重叠。
在上述方法中，还包括：在所述衬底穿孔上形成导电层；其中，所述焊盘延伸至所述导电层并且穿过所述介电层，使得所述焊盘电连接至所述衬底穿孔。
在上述方法中，还包括：在所述介电层上形成保护层以覆盖所述焊盘的侧壁的至少部分。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (1)

1.一种具有防焊盘剥离结构的半导体器件，包括：
半导体衬底，包括衬底穿孔；
介电层，位于所述半导体衬底上并且所述介电层中包括多个凹槽；以及
焊盘，位于所述半导体衬底之上以覆盖所述介电层的部分并且所述焊盘延伸至所述凹槽，
其中，从顶视图看，所述焊盘完全地覆盖所述衬底穿孔，且所述焊盘的边缘和所述凹槽的最外侧边缘之间的距离大于指定的长度。
CN201610836377.XA 2015-10-19 2016-09-21 具有防焊盘剥离结构的半导体器件和相关方法 Pending CN106992163A (zh)

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