CN106469717A - 三维集成电路结构及其制造方法 - Google Patents

三维集成电路结构及其制造方法 Download PDF

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Publication number
CN106469717A
CN106469717A CN201610009113.7A CN201610009113A CN106469717A CN 106469717 A CN106469717 A CN 106469717A CN 201610009113 A CN201610009113 A CN 201610009113A CN 106469717 A CN106469717 A CN 106469717A
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die
tube core
layer
weld pad
integrated circuit
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CN201610009113.7A
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CN106469717B (zh
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蔡文景
陈明发
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了三维集成电路结构，包括第一管芯、衬底通孔和连接件。第一管芯接合至第二管芯，其中，第一管芯的第一介电层接合至第二管芯的第二介电层，其中，第一钝化层位于第一管芯的第一介电层和第一衬底之间，且第一测试焊盘嵌入在第一钝化层中。衬底通孔穿过第一管芯并电连接至第二管芯。连接件通过衬底通孔电连接至第一管芯和第二管芯。本发明的实施例还涉及三维集成电路结构的制造方法。

Description

三维集成电路结构及其制造方法
技术领域
本发明的实施例涉及集成电路器件，更具体地，涉及三维集成电路结构及其制造方法。
背景技术
近年来，半导体工业由于诸如晶体管、二极管、电阻器、电容器等的各种电子元件的集成度不断提高而经历了快速增长。这种集成度的提高主要归因于最小部件尺寸越来越小，这允许在给定区域中集成更多元件。
这些更小的电子元件也需要占用面积比现有封装件更小的较小的封装件。半导体封装件的典型类型包括四方扁平封装(QFP)、插针网格阵列(PGA)、球栅阵列(BGA)、倒装芯片(FC)、三维集成电路(3DIC)、晶圆极封装(WLP)和堆叠式封装(PoP)器件。一些3DIC通过在半导体晶圆级上堆叠式放置芯片制备而成。由于堆叠的芯片之间的互连件的长度减小，因此3DIC提供了集成度升高和诸如速度更快和带宽更高的其他优势。然而，3DIC技术发展仍面临相当多的挑战。
发明内容
本发明的实施例提供了一种三维集成电路结构，包括：第一管芯，接合至第二管芯，其中，所述第一管芯的第一介电层接合至所述第二管芯的第二介电层，其中，第一钝化层位于所述第一管芯的所述第一介电层和第一衬底之间，并且第一测试焊盘嵌入在所述第一钝化层中；衬底通孔，穿过所述第一管芯并电连接至所述第二管芯；以及连接件，通过所述衬底通孔电连接至所述第一管芯和所述第二管芯。
本发明的另一实施例提供了一种三维集成电路结构，包括：第一管芯，接合至第二管芯，其中，所述第一管芯的第一介电层接合至所述第二管芯的第二介电层，其中，第一钝化层位于所述第一管芯的所述第一介电层和第一衬底之间，并且第一测试焊盘在所述第一钝化层中形成并延伸至所述第一介电层；衬底通孔，穿过所述第一管芯并电连接至所述第二管芯；以及连接件，通过所述衬底通孔电连接至所述第一管芯和所述第二管芯。
本发明的又一实施例提供了一种制造三维集成电路结构的方法，所述方法包括：对第一半导体晶圆的第一金属化结构和第二半导体晶圆的第二金属化结构实施管芯性能测试以识别第一管芯和第二管芯，其中，所述第一管芯和所述第二管芯是已知良好管芯；在所述第一半导体晶圆上形成第一介电层，并在所述第二半导体晶圆上形成第二介电层；将所述第一管芯拿起以接合至所述第二管芯，其中，将所述第一介电层接合至所述第二介电层；形成连接件以通过衬底通孔电连接至所述第一管芯和所述第二管芯，从而形成堆叠结构；以及将所述堆叠结构分割以形成所述三维集成电路结构。
附图简述
图1A至图1K是示出根据第一实施例的三维集成电路(3DIC)结构的制造方法的示意性截面图。
图2A至图2G是示出根据第二实施例的3DIC结构的制造方法的示意性截面图。
图3A至图3G是示出根据第三实施例的3DIC结构的制造方法的示意性截面图。
图4A至图4F是示出根据第四实施例的三维集成电路结构的制造方法的示意性截面图。
图5A至图5G是示出根据第五实施例的3DIC结构的制造方法的示意性截面图。
图6是示出根据一些实施例的3DIC结构的制造方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实施例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…上方”、“在…上方”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
图1A至图1K是示出根据第一实施例的三维集成电路(3DIC)结构的制造方法的示意性截面图。图6是示出根据一些实施例的3DIC结构的制造方法的流程图。
参考图1A，提供了第一半导体晶圆100。第一半导体晶圆100包括第一衬底102，第一衬底102可由硅或其他半导体材料制成。可选地或额外地，第一衬底102可包括诸如锗的其他元素半导体材料。在一些实施例中，第一衬底102由诸如碳化硅、砷化镓、砷化铟或磷化铟的化合物半导体制成。在一些实施例中，第一衬底102由诸如锗化硅、磷化硅锗的合金半导体制成。在一些实施例中，第一衬底102包括外延层。例如，第一衬底102具有位于块状半导体上面的外延层。
参考图1A，在一些实施例中，在前段制程(FEOL)工艺中形成位于第一半导体晶圆100中的第一器件区104。第一器件区104之一包括栅极结构108、源极/漏极区112和诸如浅沟槽隔离(STI)结构的隔离结构114。栅极结构108包括栅极介电层109、栅电极110并且可能包括间隔件(未示出)。例如，栅极介电层109由氧化硅、高介电常数(高-k)材料或其组合制成。在一些实施例中，高-k材料具有大于约4或甚至大于约10的介电常数。在一些实施例中，高-k材料包括金属氧化物，诸如二氧化钛(TiO2)、二氧化锆(ZrO2)、二氧化铪(HfO2)、五氧化二钽(Ta2O5)和氧化钡锶钛((Ba,Sr)TiO3)或其组合。在一些实施例中，栅电极110是包括金属、金属合金、金属硅化物或其组合的金属栅极。在可选实施例中，栅电极110是多晶硅栅极。源极/漏极区112包括外延层(例如，SiGe或SiC)和/或在其中包括掺杂区。图1A所示的第一器件区104仅为实例，并且在第一器件区104中可形成其他结构。
第一器件区104可形成多种N-型金属氧化物半导体(NMOS)和/或P-型金属氧化物半导体(PMOS)器件，诸如晶体管或存储器等，所述器件互连以实施一种或多种功能。在第一衬底102上也可形成诸如电容器、电阻器、二极管、光电二极管、熔断器等的其他器件。
参考图1A，在第一器件区104的旁边和上方形成介电层106。例如，介电层106包括氧化硅、氮化硅、氮氧化硅或具有低于4的介电常数的低介电常数(低-k)材料。在一些实施例中，介电层106由氧化硅制成。例如，形成介电层106的方法包括化学气相沉积(CVD)法、物理气相沉积(PVD)工艺等。
在第一器件区104上方形成第一互连件120以将其电连接至第一器件区104。在一些实施例中，第一互连件120包括位于介电层106中或上的接触插塞122和导线124。
导线124嵌入在第一绝缘层126中。例如，接触插塞122和导线124包括铜、铜合金、镍、铝、钨、其组合等。在一些实施例中，接触插塞122由钨制成且导线124由铜制成。在一些实施例中，形成接触插塞122和导线124包括图案化介电层，在介电层106中或上形成插塞和金属层。在可选实施例中，接触插塞122和导线124可通过例如双镶嵌工艺形成。
在一些实施例中，在接触插塞122和介电层106之间或者在导线124和第一绝缘层126之间可形成阻挡层(未示出)以防止接触插塞122或导线124的材料迁移至第一器件区104。例如，阻挡层的材料包括钽、氮化钽、钛、氮化钛、钴-钨(CoW)或其组合。例如，形成阻挡层的方法包括CVD、PVD等。
第一绝缘层126包括低介电常数(低-k)材料、诸如氮化硅的氮化物、诸如氧化硅的氧化物、未掺杂硅酸盐玻璃(USG)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)或其组合。在一些实施例中，低-k材料具有小于约4或甚至小于约3的介电常数。在一些实施例中，低-k材料包括诸如苯并环丁烯(BCB)、或的聚合物基材料；或诸如氢倍半硅氧烷(HSQ)或SiOF的二氧化硅基材料。在一些实施例中，一个或多个第一绝缘层126包括多种介电材料。每个第一绝缘层126通过诸如旋转涂布、CVD等的适当工艺形成。
示出第一互连件120仅为了说明的目的。第一互连件120可包括其他配置并可包括一个或多个导线和通孔层。参考图1A，导线124是指顶部导线，其可连接至在随后的步骤中形成的测试焊盘。
此后，在第一绝缘层126和导线124上方形成第一钝化层130。在一些实施例中，第一钝化层130包括氧化硅、氮化硅、苯并环丁烯(BCB)聚合物、聚酰亚胺(PI)、聚苯并噁唑(PBO)或其组合并通过诸如旋转涂布、CVD等的适当工艺形成。在一些实施例中，第一钝化层130的厚度为从6000埃至10000埃的范围内。第一钝化层130之中具有开口132。在一些实施例中，开口132通过实施光刻工艺和蚀刻工艺形成。蚀刻工艺为诸如反应离子蚀刻工艺等的干蚀刻工艺。
在一些实施例中，在形成第一钝化层130之前，任选在第一绝缘层126和导线124上方形成覆盖层128。在一些实施例中，覆盖层128的材料可与第一钝化层130的材料不同。在可选实施例中，覆盖层128的材料可与第一钝化层130的材料相同。例如，覆盖层128由氮化硅、氧化硅、氮氧化硅等制成。在一些实施例中，第一钝化层130由氧化硅制成，且覆盖层128由氮化硅制成。在实施蚀刻工艺以形成开口132期间，还去除位于导线124上方的覆盖层128的部分以暴露导线124的顶面的部分。
参考图1A，在第一钝化层130和导线124上面形成第一导电材料层134。第一导电材料层134可为金属材料层。开口132并未完全填充第一导电材料层134。在一些实施例中，在第一钝化层130和导线124上面共形地形成第一导电材料层134，并在开口132中的导线124上方形成凹槽132a。在一些实施例中，第一导电材料层134的厚度为从2000埃至6000埃的范围内。第一导电材料层134的材料不同于导线124的材料。在一些实施例中，第一导电材料层134的材料比第一互连件120的材料柔软。例如，第一导电材料层134包括铝、铜、镍、金、银、钨、其组合等。在一些实施例中，第一互连件120由铜或铜合金制成，且第一导电材料层134由铝制成。例如，形成第一导电材料层134的方法包括电化学镀工艺、CVD、PECVD、原子层沉积(ALD)、PVD、其组合等。
参考图1B，在凹槽132a中的第一导电材料层134的顶面上面形成掩模140。在一些实施例中，凹槽132a中的掩模140的顶面低于第一钝化层130的顶面。掩模140的材料不同于第一导电材料层134的材料。例如，掩模140可由可流动材料形成。在一些实施例中，掩模140可为光刻胶、旋涂玻璃(SOG)等。在一些实施例中，例如，形成掩模140的方法包括旋转涂布、沉积等。例如，首先通过旋转涂布方法将掩模材料(未示出)涂覆于第一导电材料层134的表面。然后，例如，除了凹槽132a中的掩模材料之外，可通过回蚀刻去除第一导电材料层134的表面上的掩模材料。此后，保留在凹槽132a中的掩模材料形成为掩模140，并且凹槽132a中的掩模140的顶面低于第一钝化层130的顶面。
参考图1B和图1C，使用掩模140作为蚀刻掩模，对第一导电材料层134实施蚀刻工艺(例如，干蚀刻)。去除位于第一钝化层130上的第一导电材料层134。同时，还去除未被掩模140覆盖的位于开口132中的第一导电材料层134的部分。因此，在开口132中形成第一测试焊盘134a，并且开口132的侧壁附近的第一测试焊盘134a的顶面低于第一钝化层130的顶面。换言之，第一测试焊盘134a具有U-形，且第一测试焊盘134a的顶面和第一钝化层130的顶面形成一种台阶结构。在这些实施例中，第一测试焊盘134a和第一互连件120的组合是指第一金属化结构136。此后，例如，通过干蚀刻、湿蚀刻或其组合去除掩模140。
参考图1D和图6，步骤S10，对第一半导体晶圆100的第一金属化结构136实施管芯性能测试以识别或选择已知良好管芯(KGD)。在一些实施例中，管芯性能测试通过使用管芯性能探针150实施。将管芯性能探针150插入第一金属化结构136的第一测试焊盘134a中，在管芯性能测试之后在第一测试焊盘134a的上部形成探针标记152。例如，探针标记152的深度为从2000埃至6000埃的范围内。
参考图1E和图1F以及图6，步骤S12，在第一半导体晶圆100的第一钝化层130和第一测试焊盘134a上方形成第一介电材料层160。例如，第一介电材料层160包括氧化硅、氮化硅、氮氧化硅或其组合。例如，形成第一介电层160的方法包括CVD、PVCVD等。此后，对第一介电材料层160实施平坦化工艺以形成第一介电层160a。在一些实施例中，平坦化工艺可为化学机械抛光(CMP)工艺，使得第一介电层160a具有平坦表面。
参考图1G，在实施管芯性能测试并且形成第一介电材料层160后，对第一半导体晶圆100实施分割或切割工艺以使第一管芯100a彼此分离。用于分离第一管芯100a的切割工艺通常包括使用旋转叶片或激光束(未示出)沿着划线区分割第一半导体晶圆100。换言之，分割或切割工艺为例如激光切割工艺或机械切割工艺。
参考图1G，提供了第二半导体晶圆200。第二半导体晶圆200的结构可与第一半导体晶圆100的结构类似或不同。在一些实施例中，提供了与第一半导体晶圆100类似的第二半导体晶圆200。半导体晶圆200包括第二衬底202和器件区204。第二衬底202的材料与第一衬底102的材料类似。与第一器件区104类似，第二器件区204可包括栅极结构208、源极/漏极区212和隔离结构214。与栅极结构108类似，栅极结构208包括栅极介电层209、栅电极210，并且可能包括间隔件(未示出)。与第一半导体晶圆100类似，第二半导体晶圆200还包括第二金属化结构236、覆盖层228、第二钝化层230、第二测试焊盘234a和第二介电层260a。第二金属化结构236包括第二测试焊盘234a和第二互连件220。与第一互连件120类似，第二互连件220包括嵌入在介电层材料206中的接触插塞222和嵌入在第二绝缘材料层226中的导线224。
在可选实施例中，第二半导体晶圆200与第一半导体晶圆100不同。例如，可根据下列实施例中的制造半导体晶圆的方法中的任何一种方法制造第二半导体晶圆200。
参考图1G和图6，步骤S10至步骤12，在第二半导体晶圆200上形成第二介电层260a之前，也可对第二半导体晶圆200实施管芯性能测试。在该情况下，将第一管芯100a(选自第一半导体晶圆100的KGD)接合至第二管芯200a(第二半导体晶圆200的KGD)。因此，可提高产率。
在可选实施例中，第二半导体晶圆200还可为载体、衬底、管芯或适于装载或接合选自第一半导体晶圆100的KGD的任何物理结构。
参考图1G和图6，步骤S14，在一些实施例中，第一管芯100a选自和拿自第一半导体晶圆100。第一管芯100a和第二半导体晶圆200的第二管芯200a通过熔融接合而面对面地接合在一起。第一管芯100a和第二管芯200a在第一介电层160a的顶面和第二介电层260a的顶面处接合。在一些实施例中，例如，通过直接表面接合工艺将第一管芯100a接合至第二半导体晶圆200的第二管芯200a。直接表面接合工艺通过清洗和/或表面活化工艺以及随后对结合的表面施加压力、热和/或其他接合工艺步骤建立氧化物之间的接合。在一些实施例中，将一些接合的管芯或接合的管芯/晶圆烘烤、退火、加压或其他处理以加强或完成接合。
参考图1H，在第一管芯100a旁边形成密封剂304。更具体地，在第一管芯100a周围和第二半导体200的顶面上方形成密封剂304。密封剂304为模塑料、模制底充胶、树脂(诸如环氧树脂)等。在一些实施例中，例如，使用模具(未示出)将密封剂304成形或模制，模具可能具有边框或其他特征以用于在施加时保留密封剂304。这种模具可用于在第一管芯100a旁边或周围加压模制密封剂304以迫使密封剂304进入开口和凹槽中，消除密封剂304中的气袋等。在一些实施例中，密封剂304为诸如环氧树脂、树脂的非导电材料或介电材料；诸如聚苯并噁唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、其组合等的可模制聚合物；或另外的可模制材料。例如，密封剂304为可通过化学反应或通过干燥固化的环氧树脂或树脂。在一些实施例中，密封剂304为紫外线(UV)固化的聚合物。在一些实施例中，在封装件上形成包括氧化物、氮化物等的介电膜或绝缘膜。在这类实施例中，密封剂304被绝缘膜替代。然而，为了简洁，密封剂304的实施例在本文是指包括介电膜或绝缘膜的实施例。在一些实施例中，绝缘膜可为诸如氮化硅、氧化硅、氮氧化硅的氧化物膜或氮化物膜，或另外的介电材料，并通过CVD、PECVD或另外的工艺形成。
例如，可通过研磨、CMP、蚀刻或另外的工艺削减或平坦化密封剂304。例如，在密封剂304为诸如氧化物或氮化物的绝缘膜的情况下，干蚀刻或CMP用于削减或平坦化密封剂304的顶面。在一些实施例中，在如图1H所示的平坦化之后，密封剂304可能覆盖第一管芯100a。在可选实施例中，削减密封剂304使得第一管芯100a暴露(未示出)。在一些实施例中，以与密封剂304相同的工艺将第一管芯100a的第一衬底102削薄或削减，导致第一管芯100a的后侧面与密封剂304的表面基本共面。在其他实施例中，可以相同工艺将第二管芯200a的第二衬底202削薄或削减。
参考图1I至图1J以及图6，步骤S16，形成衬底通孔(TSV)311以穿过第一管芯100a。TSV 311用于提供电连接并用于堆叠结构300a的散热。在一些实施例中，TSV 311用于将位于第二半导体晶圆200上的导线224连接至第一管芯100a的后侧。在可选实施例中，TSV 311可通过再分布线(RDL)与第一管芯100a连接，再分布线可在下列实施例中在第二半导体晶圆200上形成。在另一可选实施例中，第一导线124和第二导线224可通过TSV 311电连接。尽管图1J仅示出一个TSV 311，但可形成多于一个TSV。
参考图1I，将堆叠结构300a图案化并通过一种或多种蚀刻工艺形成延伸穿过第一管芯100a的TSV开口313以暴露第二半导体晶圆200的导线224的部分。在一些实施例中，使用双镶嵌后通孔工艺形成TSV开口313。在可选实施例中，使用两种或多种蚀刻工艺和时间模式蚀刻工艺形成TSV开口313以便可将TSV开口313的深度和宽度控制在预定的深度和宽度。在另一可选实施例中，如图1I所示，TSV开口313的上部的宽度大于TSV开口313的下部的宽度。
在一些实施例中，TSV 311包括间隔件312和导电通孔材料316。间隔件312形成在TSV开口313的侧壁上以充当隔离层，从而使得导电通孔材料316和第一衬底102彼此不直接接触。在一些实施例中，如图1J所示，间隔件312使导线124的横向表面的部分暴露在TSV开口313中，从而使得随后形成的导电通孔材料316可与导线224电接触。在一些双镶嵌实施例中，在TSV开口313的上部和下部形成间隔件312，其中，上部和下部间隔件312彼此横向隔开并且暴露导线124的横向表面。
间隔件312的形成包括形成绝缘材料层(未示出)，然后实施各向异性蚀刻工艺。例如，绝缘材料层由包括氧化硅、氮化硅、氮氧化硅的绝缘材料制成。绝缘材料层可通过使用PECVD工艺或其他适用工艺形成。绝缘材料层可为单层或多层。在一些实施例中，间隔件312的厚度为从约100埃至5000埃的范围内。导电通孔材料316由铜、铜合金、铝合金或其组合制成。可选地，可使用其他适用材料。在一些实施例中，通过镀形成导电通孔材料316。
在一些实施例中，在间隔件312上方共形地形成扩散阻挡层(未示出)。扩散阻挡层用于防止随后形成的导电通孔材料316迁移至第一器件区104和第二器件区204。例如，扩散阻挡层由钽、氮化钽、钛、氮化钛、钴-钨(CoW)或其组合制成。在一些实施例中，扩散阻挡层通过PVD工艺形成。
参考图1K，可在密封剂304的顶面304a上形成具有一个或多个绝缘层(例如，在图1K中示出两个绝缘层331和333)和导电元件332的再分布线(RDL)层330。在一些实施例中，在导电元件332和绝缘层331之间形成扩散阻挡层(未示出)。在RDL层330上形成导电焊盘322，并且在导电焊盘322和RDL层330的部分上形成钝化层328。导电焊盘322通过RDL层330电连接至TSV 311。在一些实施例中，例如，导电焊盘322由诸如铜、铝、铜合金、铝合金的具有低电阻率的导电材料或其他适用材料制成。
参考图1K，在导电焊盘322上形成UBM层324。UBM 324层可包括粘附层和/或润湿层。在一些实施例中，例如，UBM层324由钽、氮化钽、钛、氮化钛等制成。在一些实施例中，UBM层324还包括铜晶种层(未示出)。
参考图1K和图6，步骤S16，在UBM层324上方形成连接件326(诸如焊球、导电柱等)。在一些实施例中，连接件326可由诸如焊料或焊料合金的具有低电阻率的导电材料制成。例如，焊料合金包括锡(Sn)、铅(Pb)、银(Ag)、铜(Cu)、镍(Ni)、铋(Bi)或其组合。在一些实施例中，第一管芯100a的导线124通过TSV 311电连接至第二管芯200a的导线224并且通过导电元件332进一步电连接至连接件326。
参考图1K和图6，步骤S18，对堆叠结构300a实施分割或切割工艺以使3DIC结构310a彼此分离。例如，分割或切割工艺为激光切割工艺或机械切割工艺。
参考图1K，在该情况下，将第一管芯100a(其为选自第一半导体晶圆100的KGD)接合至第二管芯200a(其为选自第二半导体晶圆200的KGD)，其中，将第一管芯100a的第一介电层160a接合至第二管芯200a的第二介电层260a。每个3DIC的产率均提高，因为在分割之前已完成管芯性能测试和选择。此外，在第一实施例中，接合层的平坦表面可提高接合强度。而且，与传统制造工艺相比，省略测试焊盘的光掩模或额外的钝化层以简化制造工艺并降低工艺成本。
图2A至图2G是示出根据第二实施例的3DIC结构的制造方法的示意性截面图。
参考图2A，第二实施例与上述第一实施例类似。然而，可形成图2A中位于第一半导体晶圆100上的第一钝化层130，其厚度比图1A中的钝化层薄。在一些实施例中，例如，第一钝化层130的厚度小于6000埃。
参考图2A，在第一钝化层130和导线124上面形成第一导电材料层134。第一钝化层130中的开口132完全填充第一导电材料层134。在一些实施例中，第一导电材料层134的厚度可能比第一钝化层130的厚度略厚。形成第一导电材料层134的材料和方法已在上文描述。因此，此处省略重复描述。
参考图2A和图2B，对第一导电材料层134实施平坦化工艺。第一导电材料层134的部分保留在开口132中，由此第一测试焊盘134a形成并且嵌入在第一钝化层130中。在一些实施例中，第一测试焊盘134a的顶面与第一钝化层130的顶面基本共面。例如，平坦化工艺为CMP工艺等。在一些实施例中，第一金属化结构136包括第一测试焊盘134a和互连件120。
参考图2C至图2G以及图6，根据第一实施例中描述的方法实施步骤S10至步骤S16以形成堆叠结构300b。此后，参考图6，步骤S18，可将堆叠结构300b分割以随后形成3DIC结构310b。将第一钝化层130的厚度制成比图1H中的钝化层薄，因此降低了堆叠结构300b的厚度。
图3A至图3G是示出根据第三实施例的3DIC结构的制造方法的示意性截面图。
参考图3A，第三实施例与上述第二实施例类似。然而，在第一钝化层130中形成多个开口132以暴露位于第一半导体晶圆100上的互连件120的顶部导线124的部分。可选地或额外地，在第一钝化层130中还可形成另外的开口133。在一些实施例中，可同时形成开口132和开口133。例如，开口132和开口133分别包括沟槽和通孔。
参考图3A，在第一钝化层130和导线124上面形成第一导电材料层134。在一些实施例中，开口132和开口133完全填充第一导电材料层134。
参考图3B，对第一导电材料层134实施平坦化工艺。保留在开口132和开口133中的第一导电材料层134形成为嵌入在第一钝化层130中的第一测试焊盘134a和RDL 134b。在一些实施例中，在平坦化之后，第一测试焊盘134a的顶面和RDL的顶面与第一钝化层130的顶面基本共面。例如，平坦化工艺可为CMP工艺等。在一些实施例中，第一测试焊盘134a具有T-形。在一些实施例中，第一金属化结构136包括第一测试焊盘134a、RDL 134b和互连件120。
参考图3C至图3G以及图6，根据第一实施例中描述的方法实施步骤S10至步骤S16以形成堆叠结构300c。此后，参考图3G和图6，步骤S18，将堆叠结构300c分割以随后形成3DIC结构310c。
图4A至图4F是示出根据第四实施例的3DIC结构的制造方法的示意性截面图。
参考图4A和4B，第四实施例与上述第一实施例类似。然而，通过例如光刻工艺和蚀刻工艺将第一导电材料层134图案化以在第一钝化层130和互连件120的导线124上方形成第一测试焊盘134a和RDL 134b。例如，蚀刻工艺为干蚀刻工艺。在一些实施例中，干蚀刻工艺为反应离子蚀刻工艺等。在一些实施例中，第一金属化结构136包括第一测试焊盘134a、RDL 134b和互连件120。
参考图4B至4D，根据第一实施例中描述的方法实施步骤S10至步骤S12。在实施管芯性能测试之后，在第一测试焊盘134a、RDL 134b和第一钝化层130上形成第一介电层160a。换言之，第一测试焊盘134a形成在第一钝化层130中并延伸至第一介电层160a。RDL 134b嵌入在第一介电层160a中。
参考图4E和图6，根据第一实施例中描述的方法实施步骤S14至步骤S16以形成堆叠结构300d。此后，参考图6，步骤S18，将堆叠结构300d分割以随后形成3DIC结构310d。
在第三和第四实施例中，由于可同时形成测试焊盘和RDL，因此可简化制造方法的工艺并且提高空间利用率。
图5A至图5G是示出根据第五实施例的3DIC结构的制造方法的示意性截面图。
参考图5A，第五实施例与上述第一实施例类似。然而，没有形成第一实施例的覆盖层128、第一钝化层130和第一导电材料层134。在这些实施例中，第一半导体晶圆100的第一金属化结构136包括互连件120。
参考图5B和图6，步骤S10，对第一半导体晶圆100实施管芯性能测试以识别或选择KGD。在该情况下，导线124用作上述第一测试焊盘。在一些实施例中，将管芯性能探针150直接插入导线124中进行测试。在管芯性能测试之后，在导线124上部形成探针标记152。例如，探针标记152的深度为从2000埃至6000埃的范围内。
参考图5C，在一些实施例中，对第一绝缘层126和导线124实施平坦化工艺，从而可去除或减少探针标记152。例如，平坦化工艺可为CMP工艺等。在平坦化工艺之后，第一绝缘层126和导线124的表面基本共面。
参考图5D和图5E以及图6，步骤S12，在第一绝缘层126和导线124上方形成第一介电材料层160。对第一介电材料层160实施另一平坦化工艺以形成第一介电层160a。形成第一介电层160a的厚度、材料和方法已在上文描述。因此，此处省略重复描述。
参考图5F和图5G以及图6，根据第一实施例中描述的方法实施步骤S14至步骤S16以形成堆叠结构300e。此后，参考图5G和图6，步骤S18，可将堆叠结构300e分割以随后形成3DIC结构310e。
在第五实施例中，由于省略了形成测试焊盘的步骤，因此可简化制造方法的工艺。
根据上文所述内容，因为在分割之前已完成管芯性能测试和选择，所以可提高本发明的每个3DIC的产率。此外，在第一实施例中，接合层的平坦表面可提高接合强度。而且，在一些实施例中，与传统制造工艺相比，省略用于图案化测试焊盘或额外钝化层的光掩模以简化制造工艺并降低工艺成本。在一些实施例中，由于可同时形成测试焊盘和再分布线，因此可简化制造方法的工艺，并进一步地，提高空间利用率。
根据本发明的一些实施例，3DIC结构包括第一管芯、衬底通孔和连接件。第一管芯接合至第二管芯，其中，第一管芯的第一介电层接合至第二管芯的第二介电层，其中，第一钝化层位于第一管芯的第一介电层和第一衬底之间，并且第一测试焊盘嵌入在第一钝化层中。衬底通孔穿过第一管芯并电连接至第二管芯。连接件通过衬底通孔电连接至第一管芯和第二管芯。
在上述3DIC结构中，其中，所述第一测试焊盘的顶面低于所述第一钝化层的顶面。
在上述3DIC结构中，其中，所述第一测试焊盘的顶面与所述第一钝化层的顶面基本共面。
在上述3DIC结构中，还包括嵌入在所述第一钝化层中的再分布线。
在上述3DIC结构中，其中，所述第一测试焊盘之中具有探针标记。
在上述3DIC结构中，其中，所述第一测试焊盘的材料比连接至所述第一测试焊盘的第一互连件的材料柔软，并且所述第一互连件位于所述第一测试焊盘和所述第一衬底之间。
在上述3DIC结构中，其中，所述第一测试焊盘的材料比连接至所述第一测试焊盘的第一互连件的材料柔软，并且所述第一互连件位于所述第一测试焊盘和所述第一衬底之间，所述第一测试焊盘的材料包括铝，且所述第一互连件的材料包括铜、铜合金、镍、铝、钨或其组合。
在上述3DIC结构中，其中，所述第一管芯与所述第二管芯面对面地接合在一起。
在上述3DIC结构中，其中，第二钝化层位于所述第二管芯的所述第二介电层和第二衬底之间，且第二测试焊盘嵌入在所述第二钝化层中。
根据本发明的可选实施例，3DIC结构包括第一管芯、衬底通孔和连接件。第一管芯接合至第二管芯，其中，第一管芯的第一介电层接合至第二管芯的第二介电层，其中，第一钝化层位于第一管芯的第一介电层和第一衬底之间，并且第一测试焊盘在第一钝化层中形成并延伸至第一介电层。衬底通孔穿过第一管芯并电连接至第二管芯。连接件通过衬底通孔电连接至第一管芯和第二管芯。
在上述3DIC结构中，还包括嵌入在所述第一介电层中的再分布线。
在上述3DIC结构中，其中，所述第一测试焊盘之中具有探针标记。
在上述3DIC结构中，其中，所述第一测试焊盘的材料比第一互连件的材料柔软，且所述第一互连件位于所述第一测试焊盘和所述第一衬底之间。
在上述3DIC结构中，其中，所述第一测试焊盘的材料比第一互连件的材料柔软，且所述第一互连件位于所述第一测试焊盘和所述第一衬底之间，所述第一测试焊盘的材料包括铝，且所述第一互连件的材料包括铜、铜合金、镍、铝、钨或其组合。
在上述3DIC结构中，其中，所述第一管芯与所述第二管芯面对面地接合在一起。
在上述3DIC结构中，其中，第二钝化层位于所述第二管芯的所述第二介电层和第二衬底之间，且第二测试焊盘在所述第二钝化层中形成并延伸至所述第二介电层。
根据本发明的一些实施例，制造3DIC结构的方法包括下列步骤。对第一半导体晶圆的第一金属化结构和第二半导体晶圆的第二金属化结构实施管芯性能测试以识别第一管芯和第二管芯，其中，第一管芯和第二管芯是已知良好管芯。在第一半导体晶圆上形成第一介电层，并在第二半导体晶圆上形成第二介电层。将第一管芯拿起以接合至第二管芯，其中将第一介电层接合至第二介电层。形成连接件以通过衬底通孔电连接至第一管芯和第二管芯，从而形成堆叠结构。将堆叠结构分割以形成三维集成电路结构。
在上述方法中，其中，所述第一金属化结构和所述第二金属化结构分别包括测试焊盘、互连件、再分布线或其组合。
在上述方法中，其中，所述第一金属化结构和所述第二金属化结构分别包括测试焊盘、互连件、再分布线或其组合，所述测试焊盘的材料比连接至所述测试焊盘的所述互连件的材料柔软。
在上述方法中，其中，将所述第一管芯与所述第二管芯面对面地接合。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种三维集成电路结构，包括：
第一管芯，接合至第二管芯，其中，所述第一管芯的第一介电层接合至所述第二管芯的第二介电层，其中，第一钝化层位于所述第一管芯的所述第一介电层和第一衬底之间，并且第一测试焊盘嵌入在所述第一钝化层中；
衬底通孔，穿过所述第一管芯并电连接至所述第二管芯；以及
连接件，通过所述衬底通孔电连接至所述第一管芯和所述第二管芯。
2.根据权利要求1所述的三维集成电路结构，其中，所述第一测试焊盘的顶面低于所述第一钝化层的顶面。
3.根据权利要求1所述的三维集成电路结构，其中，所述第一测试焊盘的顶面与所述第一钝化层的顶面基本共面。
4.根据权利要求1所述的三维集成电路结构，还包括嵌入在所述第一钝化层中的再分布线。
5.根据权利要求1所述的三维集成电路结构，其中，所述第一测试焊盘之中具有探针标记。
6.根据权利要求1所述的三维集成电路结构，其中，所述第一测试焊盘的材料比连接至所述第一测试焊盘的第一互连件的材料柔软，并且所述第一互连件位于所述第一测试焊盘和所述第一衬底之间。
7.根据权利要求6所述的三维集成电路结构，其中，所述第一测试焊盘的材料包括铝，且所述第一互连件的材料包括铜、铜合金、镍、铝、钨或其组合。
8.根据权利要求1所述的三维集成电路结构，其中，所述第一管芯与所述第二管芯面对面地接合在一起。
9.一种三维集成电路结构，包括：
第一管芯，接合至第二管芯，其中，所述第一管芯的第一介电层接合至所述第二管芯的第二介电层，其中，第一钝化层位于所述第一管芯的所述第一介电层和第一衬底之间，并且第一测试焊盘在所述第一钝化层中形成并延伸至所述第一介电层；
衬底通孔，穿过所述第一管芯并电连接至所述第二管芯；以及
连接件，通过所述衬底通孔电连接至所述第一管芯和所述第二管芯。
10.一种制造三维集成电路结构的方法，所述方法包括：
对第一半导体晶圆的第一金属化结构和第二半导体晶圆的第二金属化结构实施管芯性能测试以识别第一管芯和第二管芯，其中，所述第一管芯和所述第二管芯是已知良好管芯；
在所述第一半导体晶圆上形成第一介电层，并在所述第二半导体晶圆上形成第二介电层；
将所述第一管芯拿起以接合至所述第二管芯，其中，将所述第一介电层接合至所述第二介电层；
形成连接件以通过衬底通孔电连接至所述第一管芯和所述第二管芯，从而形成堆叠结构；以及
将所述堆叠结构分割以形成所述三维集成电路结构。
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