TW201709469A - 三維積體電路結構及其製造方法 - Google Patents

三維積體電路結構及其製造方法 Download PDF

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TW201709469A
TW201709469A TW104138456A TW104138456A TW201709469A TW 201709469 A TW201709469 A TW 201709469A TW 104138456 A TW104138456 A TW 104138456A TW 104138456 A TW104138456 A TW 104138456A TW 201709469 A TW201709469 A TW 201709469A
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die
layer
dielectric layer
integrated circuit
dimensional integrated
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TW104138456A
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TWI575694B (zh
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蔡文景
陳明發
余振華
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供一種三維積體電路結構，包括第一晶粒、基板穿孔以及連接件。第一晶粒藉由第一晶粒的第一介電層與第二晶粒的第二介電層以與第二晶粒接合。第一保護層介於第一介電層與第一晶粒的第一基板之間，且第一測試墊嵌入於第一保護層中。基板穿孔穿過第一晶粒且電性連接第二晶粒。連接件經由基板穿孔電性連接第一晶粒與第二晶粒。

Description

三維積體電路結構及其製造方法
本揭露是關於一種半導體結構及其製造方法，且特別是有關於一種三維積體電路結構及其製造方法。
近年來，由於各種電子元件（例如電晶體、二極體、電阻器、電容器等）的積集度不斷提升，半導體工業因而快速成長。這種積集度的提升，大多因為最小特徵尺寸的持續縮小，因而可以將更多的元件整合在一特定的區域中。
這些尺寸較小的電子元件所需要封裝較小，其相較於先前的封裝所需的面積較小。用於半導體的封裝的例示性類型包括四方扁平封裝（quad flat pack；QFP）、針格陣列（pin grid array；PGA）、球格陣列（ball grid array；BGA）、覆晶（flip chip；FC）、三維積體電路（three dimensional integrated circuit；3DIC）、晶圓級封裝（wafer level package；WLP）以及疊層封裝（package on package；PoP）元件。在半導體晶圓層級下，有一些3DIC是藉由將晶片置於晶片上方的方式來製造。由於堆疊的晶片之間的內連線長度縮短，因此3DIC可提升積集度並具有例如是速度較快以及頻寬較高等其它的優點。然而，3DIC技術仍存在不少的挑戰。
本揭露提供一種三維積體電路結構及其製造方法，可以改善個別三維積體電路的良率且減少製程步驟以及製造成本。
根據本揭露的一些實施例，三維積體電路結構包括第一晶粒、基板穿孔以及連接件。第一晶粒藉由第一晶粒的第一介電層以及第二晶粒的第二介電層與第二晶粒接合。第一保護層介於第一介電層與第一晶粒的第一基板之間，且第一測試墊嵌入於第一保護層中。基板穿孔穿過第一晶粒且電性連接第二晶粒。連接件經由基板穿孔電性連接第一晶粒以及第二晶粒。
依據本揭露實施例所述，上述第一測試墊的頂面低於所述第一保護層的頂面。
依據本揭露實施例所述，上述第一測試墊的頂面實質上與所述第一保護層的頂面共平面。
依據本揭露實施例所述，上述的三維積體電路結構更包括重配置線路，嵌入於所述第一保護層中。
依據本揭露實施例所述，上述第一測試墊中具有探針標記。
根據本揭露的替代實施例，三維積體電路結構包括第一晶粒、基板穿孔以及連接件。第一晶粒藉由第一晶粒的第一介電層以及第二晶粒的第二介電層以與第二晶粒接合。第一保護層介於第一介電層與第一晶粒的第一基板之間，而第一測試墊形成於第一保護層中且延伸至第一介電層中。基板穿孔穿過第一晶粒且電性連接第二晶粒。連接件經由基板穿孔電性連接第一晶粒以及第二晶粒。
依據本揭露實施例所述，上述三維積體電路結構更包括重配置線路，嵌入於所述第一介電層中。
依據本揭露實施例所述，上述第一測試墊中具有探針標記。
根據本揭露的一些實施例，製造三維積體電路結構的方法包括下述：對第一半導體晶圓的第一金屬化結構與第二半導體晶圓的第二金屬化結構進行晶粒效能測試，以辨別第一晶粒與第二晶粒，其中第一晶粒與第二晶粒為已知良好晶粒。在第一半導體晶圓上形成第一介電層，且在第二半導體晶圓上形成第二介電層。取出第一晶粒，所述第一晶粒藉由第一介電層以及第二介電層與第二晶粒接合。形成連接件，連接件藉由基板穿孔電性連接至第一晶粒與第二晶粒，以形成堆疊結構。切割堆疊結構，以形成三維積體電路結構。
依據本揭露實施例所述，上述第一金屬化結構與所述第二金屬化結構各自包括測試墊、內連線、重配置線路或其組合。
本揭露的三維積體電路結構及其製造方法，可改善個別三維積體電路的良率，且減少製程步驟以及製造成本，進一步提高空間利用率。
為讓本揭露的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。於以下描述元件的具體實例及配置以簡化本揭露。當然，這些僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複參考數字及/或字母。此重複是為了簡單及清楚起見，且並不表示其指定所討論的各個實施例及/或設置之間的關係。
另外，為了易於描述圖式中繪示的一個組件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」等的空間相對術語。所述空間相對術語意圖為除了圖式中描繪的定向之外，還涵蓋使用或操作中的元件的不同定向。設備可被另外定位（旋轉90度或在其它定位），而本文所用的空間相對描述語可同樣地據此闡釋。
圖1A至圖1K為繪示根據第一實施例的三維積體電路（3DIC）結構的製造方法的剖面示意圖。圖6為繪示根據一些實施例的製造3DIC結構的方法的流程圖。
請參照圖1A，提供第一半導體晶圓100。所述第一半導體晶圓100包括第一基板102，其可由矽或其它半導體材料製成。或者（或是除此之外），第一基板102可包括其它基本半導體材料，例如鍺。在一些實施例中，第一基板102是由例如碳化矽、砷化鎵、砷化銦或磷化銦的化合物半導體製成。在一些實施例中，第一基板102是由例如矽鍺、矽鍺磷化物（silicon germanium phosphide）的合金半導體製成。在一些實施例中，第一基板102包括磊晶層。舉例來說，第一基板102具有覆於塊狀半導體的磊晶層。
請參照圖1A，在一些實施例中，在前段（front-end-of-line；FEOL）製程中，在第一半導體晶圓100中形成多個第一元件區104。第一元件區104中的一者包括閘極結構108、源極/汲極區112以及隔離結構114，例如淺溝渠隔離（STI）結構。閘極結構108包括閘介電層109、閘電極110且可包括間隙壁（未繪示）。閘介電層109例如是由氧化矽、高介電常數（高k）材料或其組合製成。在一些實施例中，高介電常數材料的介電常數為約大於4或甚至約大於10。在一些實施例中，高介電常數材料包括金屬氧化物例如氧化鈦（titanium oxide；TiO2 ）、氧化鋯（ZrO2 ）、氧化鉿（hafnium oxide；HfO2 ）、氧化鉭（Ta2 O5 ）以及鈦酸鋇鍶（barium and strontium titanium oxide；(Ba,Sr)TiO3 ）或其組合。在一些實施例中，閘電極110為包括金屬、金屬合金、金屬矽化物或其組合的金屬閘極。在一些替代實施例中，閘電極110為多晶矽閘極。源極/汲極區112包括磊晶層（如SiGe或SiC）及/或其中的摻雜區。圖1A中繪示的第一元件區104僅為例示，且在第一元件區104中可形成其它的結構。
第一元件區104可形成各種N型金氧半導體（NMOS）及/或P型金氧半導體（PMOS）元件，例如電晶體或記憶體等，其互相連接以執行一個或多個功能。在第一基板102上也可形成其它元件，例如電容器、電阻器、二極體、光二極體、熔斷器（fuse）等。
請參照圖1A，在第一元件區104旁以及第一元件區104上方形成介電層106。介電層106（例如）包括氧化矽、氮化矽、氮氧化矽或介電常數小於4的低介電常數（低k）材料。在一些實施例中，介電層106是由氧化矽製成。形成介電層106的方法包括（例如）化學氣相沈積（chemical vapor deposition；CVD）、物理氣相沈積（physically vapor deposition；PVD）製程等。
在第一元件區104上方形成第一內連線120，第一內連線120電性連接第一元件區104。在一些實施例中，第一內連線120包括在介電層106中或在介電層106上的接觸窗插塞122以及導電線路124。
導電線路124嵌入於第一絕緣層126中。接觸窗插塞122與導電線路124包括（例如）銅、銅合金、鎳、鋁、鎢、其組合等。在一些實施例中，接觸窗插塞122由鎢製成，而導電線路124由銅製成。在一些實施例中，接觸窗插塞122與導電線路124的形成包括將介電層圖案化，在介電層106中或在介電層106上形成插塞以及金屬層。在一些替代實施例中，接觸窗插塞122以及導電線路124可藉由例如是雙重金屬鑲嵌製程來形成。
在一些實施例中，在接觸窗插塞122與介電層106之間或在導電線路124與第一絕緣層126之間可形成阻障層（未繪示），以避免接觸窗插塞122或導電線路124的材料遷移至第一元件區104中。阻障層的材料包括（例如）鉭、氮化鉭、鈦、氮化鈦、鈷鎢（CoW）或其組合。形成阻障層的方法包括（例如）CVD、PVD等。
第一絕緣層126包括低介電常數（低k）材料；氮化物，例如氮化矽；氧化物，例如氧化矽、未經摻雜的玻璃（undoped silicate glass；USG）、磷矽玻璃（phosphosilicate glass；PSG）、硼矽玻璃（borosilicate glass；BSG）、硼磷矽玻璃（boron-doped phosphosilicate glass；BPSG）或其組合。在一些實施例中，低介電常數材料的介電常數約小於4或甚至約小於3。在一些實施例中，低介電常數材料包括聚合物類材料，例如苯環丁烯（benzocyclobutene；BCB）、FLARE® 或SILK® ；或二氧化矽類材料，例如氫化倍半矽氧烷（hydrogen silsesquioxane；HSQ）或SiOF。在一些實施例中，第一絕緣層126中的一者或更多者包括多種介電材料。第一絕緣層126可藉由合適的製程（例如旋轉塗佈、CVD等）來形成。
所繪示的第一內連線120僅是為了用來說明。第一內連線120還可包括其它結構且可包括一個或多個導電線路以及介層窗層。在圖1A中，導電線路124可以是指頂導電線路，其可連接至以下步驟中形成的測試墊。
之後，在第一絕緣層126與導電線路124上方形成第一保護層130。在一些實施例中，第一保護層130包括氧化矽、氮化矽、苯環丁烯（BCB）聚合物、聚醯亞胺（polyimide；PI）、聚苯並噁唑（polybenzoxazole；PBO）或其組合，且可藉由合適的製程（例如旋轉塗佈、CVD等）形成。在一些實施例中，第一保護層130的厚度的範圍在6000埃至10000埃。第一保護層130中具有開口132。在一些實施例中，開口132是藉由進行微影製程以及蝕刻製程形成。蝕刻製程可以是乾蝕刻製程，例如反應性離子蝕刻製程等。
在一些實施例中，在形成第一保護層130之前，可以選擇性地在第一絕緣層126與導電線路124上方形成蓋層128。在一些實施例中，蓋層128的材料與第一保護層130的材料可不同。在一些替代實施例中，蓋層128的材料與第一保護層130的材料可相同。蓋層128例如是由氮化矽、氧化矽、氮氧化矽或類似物製成。在一些實施例中，第一保護層130是由氧化矽製成，而蓋層128是由氮化矽製成。在進行形成開口132的蝕刻製程期間，也可移除導電線路124上方的部分的蓋層128，以暴露出部分導電線路124的頂面。
請參照圖1A，於第一保護層130以及導電線路124上形成第一導電材料層134。第一導電材料層134可以是金屬材料層。第一導電材料層134不完全填滿開口132。在一些實施例中，第一導電材料層134共形地形成，覆蓋第一保護層130與導電線路124，且於開口132中的導電線路124上方形成凹部132a。在一些實施例中，第一導電材料層134的厚度範圍在2000埃至6000埃。第一導電材料層134的材料與導電線路124的材料不同。在一些實施例中，第一導電材料層134的材料比第一內連線120的材料軟。第一導電材料層134例如是包括鋁、銅、鎳、金、銀、鎢、上述組合等。在一些實施例中，第一內連線120由銅或銅合金製成，而第一導電材料層134由鋁製成。形成第一導電材料層134的方法包括（例如）電化學電鍍製程、CVD、PECVD、原子層沈積（atomic layer deposition；ALD）、PVD、上述的組合等。
請參照圖1B，形成罩幕140，其覆蓋凹部132a中的第一導電材料層134的頂面。在一些實施例中，凹部132a中的罩幕140的頂面低於第一保護層130的頂面。罩幕140的材料與第一導電材料層134的材料不同。罩幕140可例如是以流動性的材料形成。在一些實施例中，罩幕140可以是光阻、旋塗式玻璃（spin-on glass；SOG）等。在一些實施例中，形成罩幕140的方法包括（例如）旋轉塗佈、沈積等。舉例來說，首先藉由旋轉塗佈法將罩幕材料（未繪示）塗佈於第一導電材料層134的表面上。接著，可藉由（例如）回蝕刻移除凹部132a以外位在第一導電材料層134的表面上的罩幕材料。此後，凹部132a中剩餘的罩幕材料形成為罩幕140，且凹部132a中的罩幕140的頂面低於第一保護層130的頂面。
請參照圖1B與圖1C，以罩幕140做為蝕刻罩幕，對第一導電材料層134進行蝕刻製程（如乾蝕刻）。移除第一保護層130上的第一導電材料層134。同時，也移除開口132中未被罩幕140覆蓋的部分的第一導電材料層134。因此，於開口132中形成第一測試墊134a。第一測試墊134a接近開口132側壁的頂面低於第一保護層130的頂面。換句話說，第一測試墊134a為U形，且第一測試墊134a的頂面與第一保護層130的頂面形成階梯。在這些實施例中，第一測試墊134a與第一內連線120的組合為第一金屬化結構136。之後，藉由（例如）乾蝕刻、濕蝕刻或其組合移除罩幕140。
請參照圖1D與圖6，步驟S10：對第一半導體晶圓100的第一金屬化結構136進行晶粒效能測試，以辨別或選擇已知良好晶粒（known good die；KGD）。在一些實施例中，晶粒效能測試是藉由使用晶粒效能探針150進行。晶粒效能探針150插入第一金屬化結構136的第一測試墊134a中，且在晶粒效能測試後，於第一測試墊134a的上部中留下探針標記152。探針標記152的深度範圍例如在2000埃至6000埃。
請參照圖1E與圖1F以及圖6，步驟S12：於第一半導體晶圓100的第一保護層130及第一測試墊134a上方形成第一介電材料層160。第一介電材料層160包括例如氧化矽、氮化矽、氮氧化矽或其組合。形成第一介電材料層160的方法包括（例如）CVD、PVCVD等。之後，對第一介電材料層160進行平坦化製程，以形成第一介電層160a。在一些實施例中，平坦化製程可以是化學機械研磨（chemical mechanical polishing；CMP）製程，使得第一介電層160a具有平坦的表面。
請參照圖1G，在進行晶粒效能測試並且形成第一介電材料層160之後，對第一半導體晶圓100進行切割或單顆化製程（singulation process），以便將第一晶粒100a彼此分離。用於分離第一晶粒100a的切割製程一般包括以旋轉切刀或雷射束（未繪示）沿著切割道切割第一半導體晶圓100。換句話說，切割或單顆化製程例如是雷射切割製程或機械切割製程。
請參照圖1G，提供第二半導體晶圓200。第二半導體晶圓200的結構可與第一半導體晶圓100的結構類似或不同。在一些實施例中，提供類似於第一半導體晶圓100的第二半導體晶圓200。半導體晶圓200包括第二基板202與元件區204。第二基板202的材料與第一基板102的材料類似。第二元件區204類似於第一元件區104，其可包括閘極結構208、源極/汲極區212以及隔離結構214。閘極結構208類似於閘極結構108，其可包括閘介電層209、閘電極210，且可包括間隙壁（未繪示）。第二半導體晶圓200類似於第一半導體晶圓100，其可以更包括第二金屬化結構236、蓋層228、第二保護層230以及第二介電層260a。第二金屬化結構236包括第二測試墊234a與第二內連線220。第二內連線220類似於第一內連線120，其可包括嵌入於介電層材料206中的接觸窗插塞222以及嵌入於第二絕緣材料層226中的導電線路224。
在一些替代實施例中，第二半導體晶圓200與第一半導體晶圓100不同。舉例來說，第二半導體晶圓200可以是以根據以下實施例的製造半導體晶圓的方法中的任一個來製造。
請參照圖1G與圖6，步驟S10至步驟S12：也可在於第二半導體晶圓200上形成第二介電層260a之前，對第二半導體晶圓200進行晶粒效能測試。在此情況下，選自第一半導體晶圓100的第一晶粒100a為KGD，其可接合第二晶粒200a（其為第二半導體晶圓200的KGD）。因此，可改善良率。
在一些替代實施例中，第二半導體晶圓200也可以是適合負載選自第一半導體晶圓100的KGD或適合與選自第一半導體晶圓100的KGD接合的載板、基板、晶粒或任何物理結構。
請參照圖1G與圖6，步驟S14：在一些實施例中，從第一半導體晶圓100選擇與取出第一晶粒100a。藉由熔化接合（fusion bonding）將第一晶粒100a與第二半導體晶圓200的第二晶粒200a面對面接合在一起。第一晶粒100a與第二晶粒200a在第一介電層160a的頂面與第二介電層260a的頂面處接合。在一些實施例中，例如藉由直接表面接合製程（direct surface bonding process）將第一晶粒100a與第二半導體晶圓200的第二晶粒200a接合。直接表面接合製程藉由對接合的表面進行清潔及/或表面活化製程，接著施加壓力、熱及/或其它接合製程步驟來產生氧化物對氧化物的鍵結。在一些實施例中，還進一步對接合的晶粒或接合的晶粒/晶圓進行烘烤、退火、加壓或以其它處理以強化接合或做最後的接合。
請參照圖1H，在第一晶粒100a旁形成封裝物304。更具體地說，在第一晶粒100a周圍形成封裝物304，且封裝物304覆蓋第二半導體200的頂面。封裝物304是模製化合物（molding compound）、模製底部填料（molding underfill）、樹脂（例如環氧樹脂）等。在一些實施例中，在使用封裝物304時，封裝物304是使用（例如）模板（mold）（未繪示）來成型或模製。所述模板可具有邊界或其它特徵來固持封裝物304。這種模板可用來對第一晶粒100a旁或周圍的封裝物304進行加壓模製，使得封裝物304填入開口與凹部、除去封裝物304中的氣穴等。在一些實施例中，封裝物304為非導電或介電材料，例如環氧化物、樹脂。可模製的聚合物，例如聚苯並噁唑（PBO）、聚醯亞胺、苯環丁烯（BCB）、其組合等或其它可模製的材料。舉例來說，封裝物304是藉由化學反應或乾燥來固化的環氧化物或樹脂。在一些實施例中，封裝物304是紫外線（UV）固化的聚合物。在一些實施例中，在封裝上方形成包括氧化物、氮化物等的介電膜或絕緣膜。在這些實施例中，封裝物304可以絕緣膜來替代。然而為了簡單起見，本文中將封裝物304的實施例是指包括介電膜或絕緣膜。在一些實施例中，絕緣膜可以是氧化物膜或氮化物膜，例如氮化矽、氧化矽、氮氧化矽或其它介電材料，且藉由CVD、PECVD或其它製程來形成。
封裝物304可藉由（例如）拋光、CMP、蝕刻或其它製程來減少其厚度或平坦化。舉例來說，當封裝物304是絕緣膜（例如氧化物或氮化物）時，使用乾蝕刻或CMP來減少其厚度或平坦化封裝物304的頂面。在一些實施例中，在平坦化之後（如圖1H所示），封裝物304覆蓋第一晶粒100a。在一些替代實施例中，封裝物304減少後，可使得第一晶粒100a暴露出來（未繪示）。在一些實施例中，第一晶粒100a的第一基板102可以相同於封裝物304製程來薄化或減少，使得第一晶粒100a的背面實質上與封裝物304的表面共平面。在其它實施例中，第二晶粒200a的第二基板202可以相同製程來薄化或減少。
請參照圖1I至圖1J與圖6，步驟S16：形成穿過第一晶粒100a的基板穿孔（through-substrate via；TSV）311。基板穿孔311可提供堆疊結構300a的電性連接與散熱。在一些實施例中，基板穿孔311可將第二半導體晶圓200上的導電線路224與第一晶粒100a的背側連接。在一些替代實施例中，基板穿孔311可將以下實施例中第二半導體晶圓200上形成的重配置線路（redistribution line；RDL）連接至第一晶粒100a。在又一替代實施例中，基板穿孔311可電性連接第一導電線路124與第一導電線路224。雖然圖1J僅繪示一個基板穿孔311，但可形成多於一個的基板穿孔。
請參照圖1I，藉由一個或多個蝕刻製程，將堆疊結構300a圖案化，形成TSV開口313。所述TSV開口313延伸穿過第一晶粒100a，以暴露部分的第二半導體晶圓200的導電線路224。在一些實施例中，TSV開口313是使用雙重金屬鑲嵌的後介層窗孔製程（dual damascene via last process）來形成。在一些替代實施例中，TSV開口313可以是使用兩個或更多個蝕刻製程與時間模式蝕刻製程來形成，以將TSV開口313的深度與寬度控制在預定深度與寬度。在又一替代實施例中，如圖1I所示，TSV開口313的上部的寬度較TSV開口313的下部寬。
在一些實施例中，基板穿孔311包括間隙壁312以及導電介層窗材料316。在TSV開口313的側壁上形成的間隙壁312可做為隔離層，使得導電介層窗材料316與第一基板102彼此不直接接觸。在一些實施例中，如圖1J中所示，間隙壁312可使得部分的導電線路124的橫向表面暴露於TSV開口313中，以令後續形成的導電介層窗材料316可與導電線路224電性接觸。在一些雙重金屬鑲嵌的實施例中，間隙壁312在TSV開口313的上部與下部中是分離的，其上部與下部間隙壁312彼此橫向地分離且暴露導電線路124的橫向表面。
間隙壁312的形成包括形成絕緣材料層（未繪示），且接著進行非等向性蝕刻製程。絕緣材料層例如是由包括氧化矽、氮化矽、氮氧化矽的絕緣材料製成。絕緣材料層可藉由使用PECVD製程或其它可應用的製程來形成。絕緣材料層可以是單一層或多層。在一些實施例中，間隙壁312的厚度範圍在約100埃至5000埃。導電介層窗材料316是由銅、銅合金、鋁合金或其組合製成。或者，可使用其它可應用的材料。在一些實施例中，導電介層窗材料316是藉由電鍍形成。
在一些實施例中，在間隙壁312上還可共形地形成擴散阻障層（未繪示）。擴散阻障層可用於防止稍後形成的導電介層窗材料316遷移至第一元件區104與第二元件區204中。擴散阻障層例如是由鉭、氮化鉭、鈦、氮化鈦、鈷鎢（CoW）或其組合製成。在一些實施例中，擴散阻障層是藉由PVD製程形成。
請參照圖1K，在封裝物304的頂面304a上可形成具有一個或多個絕緣層（如圖1K中所示的兩個絕緣層331以及絕緣層333）以及導電組件332的重配置線路（RDL）層330。在一些實施例中，在導電組件332與絕緣層331之間還可形成擴散阻障層（未繪示）。在RDL層330上形成導電墊322，並在部分的導電墊322以及RDL層330上方形成保護層328。導電墊322經由RDL層330與基板穿孔311電性連接。在一些實施例中，導電墊322例如是由低電阻的導電材料，例如銅、鋁、銅合金、鋁合金或其它可應用的材料製成。
請參照圖1K，在導電墊322上形成球下金屬層（UBM層）324。UBM層324可包括黏著層及/或潤濕層。在一些實施例中，UBM層324例如是由鉭、氮化鉭、鈦、氮化鈦等製成。在一些實施例中，UBM層324可更包括銅晶種層（未繪示）。
請參照圖1K與圖6，步驟S16：在UBM層324上方形成連接件326（例如焊球、導電柱等）。在一些實施例中，連接件326可由低電阻的導電材料，例如焊料或焊料合金製成。舉例來說，焊料合金包括錫（Sn）、鉛（Pb）、銀（Ag）、銅（Cu）、鎳（Ni）、鉍（Bi）或其組合。在一些實施例中，第一晶粒100a的導電線路124經由基板穿孔311電性連接至第二晶粒200a的導電線路224，而導電線路124經由導電組件332進一步電性連接至連接件326。
請參照圖1K與圖6，步驟S18：對堆疊結構300a進行切割或單顆化製程，以將3DIC結構310a彼此分離。切割或單顆化製程為（例如）雷射切割製程或機械切割製程。
請參照圖1K，在此情況下，第一晶粒100a（其為選自第一半導體晶圓100的KGD）藉由第一晶粒100a的第一介電層160a以及第二晶粒200a的第二介電層260a來與第二晶粒200a（其為選自第二半導體晶圓200的KGD）接合。由於在切割之前完成晶粒效能測試及選擇，因此3DIC的良率得以改善。此外，在第一實施例中，接合層的平坦的表面形態（topography）可改善接合強度。另外，與傳統製造製程相比，省略用於測試墊的光罩或額外的保護層，因此可以減少製造製程及製造成本。
圖2A至圖2G繪示根據第二實施例的製造3DIC結構的方法的剖面示意圖。
請參照圖2A，第二實施例與以上第一實施例類似。然而，圖2A中在第一半導體晶圓100上的第一保護層130的厚度可形成為較圖1A中的第一保護層的厚度薄。在一些實施例中，第一保護層130的厚度例如是小於6000埃。
請參照圖2A，形成第一導電材料層134，第一導電材料層134覆蓋第一保護層130與導電線路124。第一導電材料層134完全填滿第一保護層130中的開口132。在一些實施例中，第一導電材料層134的厚度可稍微較第一保護層130的厚度厚。形成第一導電材料層134的材料與方法已經描述如上，因此，不再重複敘述。
請參照圖2A與圖2B，對第一導電材料層134進行平坦化製程。平坦化後，部分的第一導電材料層134留在開口132中，而形成嵌入於第一保護層130中的第一測試墊134a。在一些實施例中，第一測試墊134的頂面實質上與第一保護層130的頂面共平面。平坦化製程例如是CMP製程等。在一些實施例中，第一金屬化結構136包括第一測試墊134a以及內連線120。
請參照圖2C至圖2G與圖6，根據第一實施例中所述的方法進行步驟S10至步驟S16，以形成堆疊結構300b。之後，請參照圖6，步驟S18：接著可切割堆疊結構300b以形成3DIC結構310b。第一保護層130的厚度為較圖1H中第一保護層的厚度薄，因此堆疊結構300b的厚度減少。
圖3A至圖3G繪示根據第三實施例的3DIC結構的製造方法的剖面示意圖。
請參照圖3A，第三實施例與以上第二實施例類似，但是，在第一保護層130中形成多個開口132，以暴露在第一半導體晶圓100的部分內連線120的頂導電線路124。或者（或是除此之外），也可在第一保護層130中形成另一開口133。在一些實施例中，開口132與開口133可同時形成。開口132與開口133各自包括例如溝渠與介層窗。
請參照圖3A，形成第一導電材料層134，第一導電材料層134覆蓋第一保護層130與導電線路124。在一些實施例中，第一導電材料層134完全填滿開口132與開口133。
請參照圖3B，對第一導電材料層134進行平坦化製程。留在開口132與開口133中的第一導電材料層134形成為第一測試墊134a與重配置線路134b。所形成的第一測試墊134a與重配置線路134b嵌入於第一保護層130中。在一些實施例中，在平坦化後，第一測試墊134a的頂面及重配置線路的頂面實質上與第一保護層130的頂面共平面。平坦化製程可例如是CMP製程等。在一些實施例中，第一測試墊134a為T型。在一些實施例中，第一金屬化結構136包括第一測試墊134a、重配置線路134b與內連線120。
請參照圖3C至圖3G與圖6，根據第一實施例中所述的方法進行步驟S10至步驟S16以形成堆疊結構300c。之後，請參照圖3G與圖6，步驟S18：切割堆疊結構300c，以形成3DIC結構310c。
圖4A至圖4F為繪示根據第四實施例的3DIC結構的製造方法的剖面示意圖。
請參照圖4A與圖4B，第四實施例與以上第一實施例類似。然而，第一導電材料層134是藉由（例如）微影製程與蝕刻製程來圖案化，以形成在內連線120的導電線路124以及第一保護層130上方的第一測試墊134a與重配置線路134b。蝕刻製程例如是乾蝕刻製程。在一些實施例中，乾蝕刻製程是反應性離子蝕刻製程等。在一些實施例中，第一金屬化結構136包括第一測試墊134a、重配置線路134b與內連線120。
請參照圖4B至圖4D，根據第一實施例中所述的方法進行步驟S10至步驟S12。在進行晶粒效能測試後，在第一測試墊134a、重配置線路134b與第一保護層130上形成第一介電層160a。換句話說，第一測試墊134a形成於第一保護層130中且延伸至第一介電層160a中；而重配置線路134b嵌在第一介電層160a中。
請參照圖4E與圖6，根據第一實施例中所述的方法進行步驟S14至步驟S16，以形成堆疊結構300d。之後，請參照圖6，步驟S18：切割堆疊結構300d，以形成3DIC結構310d。
在第三與第四實施例中，由於測試墊與重配置線路可同形成，因此可減少製程步驟且可提高空間利用率。
圖5A至圖5G為繪示根據第五實施例的3DIC結構的製造方法的剖面示意圖。
請參照圖5A，第五實施例與以上第一實施例類似。然而，未形成第一實施例的蓋層128、第一保護層130以及第一導電材料層134。在這些實施例中，第一半導體晶圓100的第一金屬化結構136包括內連線120。
請參照圖5B與圖6，步驟S10：對第一半導體晶圓100進行晶粒效能測試，以辨別或選擇KGD。在此情況下，導電線路124做為上述第一測試墊。在一些實施例中，晶粒效能探針150直接插入導電線路124中來測試。在晶粒效能測試後，在導電線路124的上部中留下探針標記152。探針標記152的深度範圍例如在2000埃至6000埃。
請參照圖5C，在一些實施例中，對第一絕緣層126與導電線路124進行平坦化製程，以移除或減少探針標記152的深度。平坦化製程可例如是CMP製程等。在平坦化製程後，第一絕緣層126與導電線路124的表面實質上為平面。
請參照圖5D與圖5E以及圖6，步驟S12：在第一絕緣層126與導電線路124上方形成第一介電材料層160。對第一介電材料層160進行另一平坦化製程，以形成第一介電層160a。形成第一介電層160a的方法、材料以及厚度已描述如上，因此，此處不再複述。
請參照圖5F與圖5G以及圖6，根據第一實施例中描述的方法進行步驟S14至步驟S16，以形成堆疊結構300e。之後，請參照圖5G與圖6，步驟S18：切割堆疊結構300e，以形成3DIC結構310e。
在第五實施例中，由於省略形成測試墊的步驟，因此可減少製程步驟。
基於上述，由於在切割之前完成晶粒效能測試與選擇，因此本揭露的個別3DIC的良率得以改善。此外，在第一實施例中，接合層的平坦表面形態可改善接合強度。另外，與傳統製造製程相比，在一些實施例中省略了用於圖案化測試墊的光罩或額外的保護層，因此可以減少製造製程以及製造成本。在一些實施例中，由於可同時形成測試墊以及重配置線路，因此可減少製程步驟，且進一步提高空間利用率。
根據本揭露的一些實施例，3DIC結構包括第一晶粒、基板穿孔以及連接件。第一晶粒藉由第一晶粒的第一介電層以及第二晶粒的第二介電層來與第二晶粒接合，其中第一保護層介於第一介電層與第一晶粒的第一基板之間，且第一測試墊嵌入於第一保護層中。基板穿孔穿過第一晶粒且電性連接至第二晶粒。連接件經由基板穿孔電性連接至第一晶粒以及第二晶粒。
根據本揭露的替代實施例，3DIC結構包括第一晶粒、基板穿孔以及連接件。第一晶粒藉由第一晶粒的第一介電層以及第二晶粒的第二介電層來與第二晶粒接合，其中第一保護層介於第一介電層與第一晶粒的第一基板之間，而第一測試墊形成於第一保護層中且延伸至第一介電層。基板穿孔穿過第一晶粒且電性連接至第二晶粒。連接件經由基板穿孔電性連接至第一晶粒以及第二晶粒。
根據本揭露的一些實施例，製造3DIC結構的方法包括下述：對第一半導體晶圓的第一金屬化結構與第二半導體晶圓的第二金屬化結構進行晶粒效能測試，以辨別第一晶粒與第二晶粒，其中第一晶粒與第二晶粒為已知良好晶粒。在第一半導體晶圓上形成第一介電層，且在第二半導體晶圓上形成第二介電層。取出第一晶粒，並藉由第一介電層與第二介電層來將所述第一晶粒與第二晶粒接合。形成連接件，連接件藉由基板穿孔電性連接至第一晶粒與第二晶粒，以形成堆疊結構。切割堆疊結構，以形成三維積體電路結構。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更加了解本揭露的態樣。本領域具有通常知識者應理解其可輕易地使用本揭露做為進行本文所介紹的相同目的及/或達到本文中介紹的實施例的相同優點的其它製程與結構的設計或修改的依據。本領域具有通常知識者還應理解到，這種相等的結構不悖離本揭露的精神與範疇，且其可做出各種本文中的改變、置換以及變更而不悖離本揭露的精神與範疇。
100、200‧‧‧半導體晶圓 100a、200a‧‧‧晶粒 102、202‧‧‧基板 104、204‧‧‧元件區 106‧‧‧介電層 108、208‧‧‧閘極結構 109、209‧‧‧閘介電層 110、210‧‧‧閘電極 112、212‧‧‧源極/汲極區 114、214‧‧‧隔離結構 120、220‧‧‧內連線 122、222‧‧‧接觸窗插塞 124、224‧‧‧導電線路 126‧‧‧第一絕緣層 128、228‧‧‧蓋層 130、230、328‧‧‧保護層 132、133‧‧‧開口 132a‧‧‧凹部 134‧‧‧導電材料層 134a、234a‧‧‧測試墊 134b‧‧‧重配置線路 136、236‧‧‧金屬化結構 140‧‧‧罩幕 150‧‧‧探針 152‧‧‧探針標記 160‧‧‧第一介電材料層 160a、260a‧‧‧介電層 206‧‧‧介電層材料 226‧‧‧絕緣材料層 300a、300b、300c、300d、300e‧‧‧堆疊結構 304‧‧‧封裝物 304a‧‧‧頂面 310a、310b、310c、310d、310e‧‧‧3DIC結構 311‧‧‧基板穿孔 312‧‧‧間隙壁 313‧‧‧TSV開口 316‧‧‧介層窗材料 322‧‧‧導電墊 324‧‧‧UBM層 326‧‧‧連接件 330‧‧‧RDL層 331、333‧‧‧絕緣層 332‧‧‧導電組件 S10、S12、S14、S16、S18‧‧‧步驟
圖1A至圖1K為繪示根據第一實施例的三維積體電路（3DIC）結構的製造方法的剖面示意圖。 圖2A至圖2G為繪示根據第二實施例的3DIC結構的製造方法的剖面示意圖。 圖3A至圖3G為繪示根據第三實施例的3DIC結構的製造方法的剖面示意圖。 圖4A至圖4F為繪示根據第四實施例的三維積體電路結構的製造方法的剖面示意圖。 圖5A至圖5G為繪示根據第五實施例的3DIC結構的製造方法的剖面示意圖。 圖6為繪示根據一些實施例的製造3DIC結構的方法的流程圖。
100a、200a‧‧‧晶粒
102‧‧‧基板
104‧‧‧元件區
120‧‧‧內連線
122‧‧‧接觸窗插塞
124‧‧‧導電線路
128、228‧‧‧蓋層
130、230‧‧‧保護層
134a‧‧‧測試墊
136‧‧‧金屬化結構
160a、260a‧‧‧介電層
204‧‧‧元件區
220‧‧‧內連線
222‧‧‧接觸窗插塞
224‧‧‧導電線路
234a‧‧‧測試墊
236‧‧‧金屬化結構
300a‧‧‧堆疊結構
304‧‧‧封裝物
304a‧‧‧頂面
310a‧‧‧3DIC結構
311‧‧‧基板穿孔
312‧‧‧間隙壁
316‧‧‧介層窗材料
322‧‧‧導電墊
324‧‧‧UBM層
326‧‧‧連接件
328‧‧‧保護層
330‧‧‧RDL層
331、333‧‧‧絕緣層
332‧‧‧導電組件

Claims (10)

  1. 一種三維積體電路結構，包括： 第一晶粒，藉由所述第一晶粒的第一介電層與第二晶粒的第二介電層來與所述第二晶粒接合，其中第一保護層介於所述第一介電層與所述第一晶粒的第一基板之間，且第一測試墊嵌入於所述第一保護層中； 基板穿孔，穿過所述第一晶粒且電性連接所述第二晶粒；以及 連接件，經由所述基板穿孔電性連接所述第一晶粒與所述第二晶粒。
  2. 如申請專利範圍第1項所述的三維積體電路結構，其中所述第一測試墊的頂面低於所述第一保護層的頂面。
  3. 如申請專利範圍第1項所述的三維積體電路結構，其中所述第一測試墊的頂面實質上與所述第一保護層的頂面共平面。
  4. 如申請專利範圍第1項所述的三維積體電路結構，更包括重配置線路，嵌入於所述第一保護層中。
  5. 如申請專利範圍第1項所述的三維積體電路結構，其中所述第一測試墊中具有探針標記。
  6. 一種三維積體電路結構，包括： 第一晶粒，藉由所述第一晶粒的第一介電層與第二晶粒的第二介電層來與所述第二晶粒接合，其中第一保護層介於所述第一介電層與所述第一晶粒的第一基板之間，且第一測試墊形成於所述第一保護層中且延伸至所述第一介電層中； 基板穿孔，穿過所述第一晶粒且電性連接所述第二晶粒；以及 連接件，經由所述基板穿孔電性連接所述第一晶粒與所述第二晶粒。
  7. 如申請專利範圍第6項所述的三維積體電路結構，更包括重配置線路，嵌入於所述第一介電層中。
  8. 如申請專利範圍第6項所述的三維積體電路結構，其中所述第一測試墊中具有探針標記。
  9. 一種製造三維積體電路結構的方法，包括： 對第一半導體晶圓的第一金屬化結構以及第二半導體晶圓的第二金屬化結構進行晶粒效能測試，以辨別第一晶粒與第二晶粒，其中所述第一晶粒與所述第二晶粒為已知良好晶粒； 在所述第一半導體晶圓上形成第一介電層，且在所述第二半導體晶圓上形成第二介電層； 取出所述第一晶粒，所述第一晶粒藉由所述第一介電層與所述第二介電層接合所述第二晶粒； 形成連接件，所述連接件藉由基板穿孔電性連接所述第一晶粒與所述第二晶粒，以形成堆疊結構；以及 切割所述堆疊結構，以形成三維積體電路結構。
  10. 如申請專利範圍第9項所述的製造三維積體電路結構的方法，其中所述第一金屬化結構與所述第二金屬化結構各自包括測試墊、內連線、重配置線路或其組合。
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