CN106856196A - 功率模块 - Google Patents
功率模块 Download PDFInfo
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- CN106856196A CN106856196A CN201610528274.7A CN201610528274A CN106856196A CN 106856196 A CN106856196 A CN 106856196A CN 201610528274 A CN201610528274 A CN 201610528274A CN 106856196 A CN106856196 A CN 106856196A
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Abstract
本发明提供一种能够提高高温条件下的结构稳定性和可靠性的功率模块,起包括:上衬底,其具有金属层;下衬底,其与上衬底隔开,并具有面对上衬底的金属层的金属层;半导体元件,其配置成布置在上衬底和下衬底之间;以及,至少一个支脚部,其在上衬底的金属层和下衬底的金属层中的至少一者上形成,从而以预定的间隔将上衬底与下衬底彼此隔开,其中,支脚部可将半导体元件与上衬底的金属层或下衬底的金属层电连接。
Description
技术领域
本发明涉及一种功率模块,且更具体地,涉及一种能够提高结构稳定性,同时在高温下保持稳定和可靠的功率模块。
背景技术
功率模块是安装在几乎所有电子设备中的部件,并且功率模块用于供电、转换电力并确保稳定性和效率。
功率模块的示例包括:绝缘栅双极晶体管(IGBT)模块,其可布置在专用情况中,同时IGBT具有安装在其中的多个二极管;嵌入电流传感器的智能功率模块(IPM:intelligent power module),其中添加了用于过流、过热等的保护电路;以及,金属氧化物半导体场效应晶体管(MOSFET)模块。
此外,某些功率模块,例如双侧冷却型功率模块,可以具有彼此隔开来彼此面对的两个衬底的结构形成。
两个衬底包括在上下方向上彼此隔开的上衬底和下衬底,其中,半导体元件可安装在上衬底与下衬底之间,并且可通过导线(wire)将引线(lead)与半导体元件的电极电连接。
在此情况下,如果导线与上衬底接触,则会发生电气短路。为此,可在上衬底与下衬底之间安装间隙子(spacer)来确保上衬底与下衬底之间的垂直间隔,从而防止导线与上衬底接触。
然而,现有的功率模块具有如下缺陷:如果因高温条件下的热膨胀而导致应力被施加至半导体元件,则间隙子的变形会很严重,并且,间隙子的变形会引起上衬底和/或下衬底的变形,因此在高温下,功率模块的稳定性和可靠性会降低。
此外,间隙子主要由铜钼(Cu-Mo)材料制成。然而,由铜钼材料制成的间隙子会具有较大电阻,并且会非常昂贵。
此外,现有的功率模块具有以下缺陷,其中,导线的两端可通过超声波焊接与半导体元件和引线接合,因此容易因相对小的外力在接合表面上发生短路。此外,导线的接合区狭窄,因此导线容易因集中的外力而发生断裂。
发明内容
本发明的一方面提供了一种功率模块,其通过简化制造过程,能够提高结构稳定性,同时确保在高温下的稳定性和可靠性,并减少电阻、提高耐久性等。
根据本发明的示例性实施例,一种功率模块包括:上衬底,其配置成具有金属层;下衬底,其配置成与所述上衬底隔开,并具有面对上衬底的金属层的金属层;半导体元件,其配置成布置在上衬底与下衬底之间;以及,至少一个支脚部(leg portion),其配置成在上衬底的金属层和下衬底的金属层中的至少一者上形成,从而以预定的间隔将上衬底和下衬底彼此隔开,其中,支脚部可配置成将半导体元件与上衬底的金属层或下衬底的金属层电连接。
通过粘合剂将半导体元件的顶面与上衬底的金属层电连接,并将半导体元件的底面与下衬底的金属层电连接。
上衬底的顶面和下衬底的底面上分别设置有冷却模块。
根据本发明的另一示例性实施例,一种功率模块包括:上衬底,其配置成具有上绝缘层,以及在上绝缘层的底面上形成的金属层;下衬底,其配置成与上衬底隔开,并具有下绝缘层,以及在下绝缘层的顶面上形成的金属层;至少一个半导体元件,其配置成分别与上衬底的连接层及下衬底的连接层相连;以及,至少一个支脚部,其配置成从上衬底的金属层朝向下衬底弯曲,其中,支脚部可具有与下衬底的金属层接合的接合端部。
可通过粘合剂将支脚部的接合端部与下衬底的金属层接合。
支脚部可形成为在上衬底的金属层的边缘处弯曲,并且支脚部的高度可等于上衬底的底面与下衬底的顶面之间的间隔。
下衬底的金属层可一体地形成有引线。
上衬底还可包括在上绝缘层的顶面上形成的金属层。
上衬底的上部可与上冷却模块连接。
下衬底还可包括在下绝缘层的底面上形成的金属层。
下衬底的下部可与下冷却模块连接。
根据本发明的另一示例性实施例,一种功率模块包括:上衬底,其配置成具有上绝缘层,以及在上绝缘层的底面上形成的金属层;下衬底,其配置成与上衬底隔开,并具有下绝缘层,以及在下绝缘层的顶面上形成的金属层;至少一个半导体元件,其配置成分别与上衬底的连接层及下衬底的连接层连接;以及,至少一个支脚部,其配置成从下衬底的金属层朝向上衬底弯曲,其中支脚部可具有与上衬底的金属层接合的接合端部。
可通过粘合剂将支脚部的接合端部与上衬底的金属层接合。
支脚部可在下衬底的金属层的边缘处形成弯曲,并且支脚部的高度可等于上衬底的底面与下衬底的顶面之间的间隔。
上衬底的金属层可一体地形成有引线。
上衬底还可包括在上绝缘层的顶面上形成的金属层。
上衬底的上部可与上冷却模块相连。
下衬底还可包括在下绝缘层的底面上形成的金属层。
下衬底的下部可与下冷却模块相连。
附图说明
从下文结合附图进行的详细描述中,本发明的上述及其他目标、特征和优势将变得更加显而易见。
图1是根据本发明的示例性实施例的功率模块的侧视截面图;
图2是根据本发明的另一示例性实施例的功率模块的透视图;
图3是沿着图2中的A-A线切开的截面图;
图4是根据本发明的又一示例性实施例的功率模块的侧视截面图。
附图标记说明:
10:上衬底
11:上绝缘层
13:金属层
20:下衬底
21:下绝缘层
23:金属层
31:支脚部
33:接合端部
具体实施方式
应当理解的是,本文所使用的术语“车辆”或“车辆的”或者其他相似术语包括一般的机动车辆,例如包括运动型多用途车(SUV)、公交车、卡车、各式商用车辆在内的载客车辆,包括各种艇和船在内的水运工具,以及航空器等等,并且包括混合动力车辆、电动车辆、插电式混合动力电动车辆、氢动力车辆以及其他代用燃料车辆(例如,从石油以外的资源取得的燃料)。如本文所述,混合动力车辆是同时具有两种或多种动力源的车辆,例如,同时汽油驱动和电驱动的车辆。
本文所使用的专有名词仅是为了说明特定实施例的目的,而非意在限制本发明。如本文所使用的,除非上下文另外清楚表明,单数形式“一个”、“一种”和“该”意在也包括复数形式。还将理解的是,当在本说明书中使用时,词语“包括”和/或“包含”规定所述特征、整数、步骤、操作、元件和/或部件的存在,但不排除一个或多个其他特征、整数、步骤、操作、元件、部件和/或其集合的存在或添加。如本文所使用的,词语“和/或”包括一个或多个相关列出项目的任何或全部组合。
贯穿说明书,除非明确说明与之相反,词语“包括”和其变形例如“包含”或者“含有”将被理解成意味着包括所述元素但是不排除任意其他元素。此外,在说明书中描述的词语“单元”、“-机”、“-器”以及“模块”意味着用于处理至少一个功能和操作的单元,并且其可通过硬件组件或者软件组件以及其二者接合进行实施。
此外,本发明的控制逻辑可实施为包含由处理器、控制器等执行的可执行程序指令的计算机可读介质上的非暂时性计算机可读介质。计算机可读介质的示例包括但不限于ROM、RAM、光盘(CD)-ROM、磁带、软盘、闪存、智能卡和光学数据存储设备。计算机可读记录介质也可分布在网络连接的计算机系统中,以便例如通过远程信息处理服务器或控制器局域网络(CAN),以分布方式存储和执行计算机可读介质。
在下文中,将参考附图详细描述本发明的示例性实施例。为了参考,在附图中示出的、用于描述本发明的示例性实施例而进行参考的部件的尺寸、线的厚度等可为了便于理解进行稍微地夸张。此外,可考虑本发明中的功能定义用于描述本发明的术语,因此其可根据用户、操作者的意图和实施等进行变化。因此,应当基于贯穿说明书的内容理解术语的定义。
参考图1,根据本发明的各种示例性实施例的功率模块可包括:上衬底10;下衬底20,其与上衬底10隔开;以及,半导体元件50,其安装在上衬底10与下衬底20之间。如本文所提供的,半导体元件50指的是一个或多个半导体元件,例如,有源器件例如半导体芯片,和/或无源器件,例如电感器或电容器。
上衬底10可包括上绝缘层11,以及在上绝缘层11的底面上形成的至少一个金属层13。
上绝缘层11可由绝缘材料,例如陶瓷制成,金属层13可由导电材料,例如铜制成。
此外,甚至在上绝缘层11的顶面可由导电材料,例如铜的金属层15形成。
下衬底20可包括下绝缘层21,以及在下绝缘层21的顶面上形成的至少一个金属层23。
下绝缘层21可由绝缘材料,例如陶瓷制成,金属层23可由导电材料,例如铜制成。
此外,甚至下绝缘层21的底面可形成有导电材料,例如铜,的金属层25。
同时,在上衬底10的金属层13或者下衬底20的金属层23上一体地形成至少一个支脚部31,其中,支脚部31可形成为从上衬底10的金属层13或从下衬底20的金属层23朝向相对的衬底弯曲,从而可以预定的间隔将上衬底10与下衬底20彼此隔开。
参考图1,可在上衬底10的金属层13上一体地形成支脚部31。具体地,支脚部31可弯曲成从上衬底10的金属层13朝向下衬底20的金属层23倾斜,并且支脚部31的下端可形成与下衬底20的金属层23接合的接合端部33。
可通过由导电材料,例如银(Ag)制成的粘合剂32接合支脚部31的接合端部33。
可根据传导的电流强度控制接合端部33的接合面积。因此,考虑上衬底10的变形优选使接合端部33的接合面积最小。
此外,优选在至少三个部位形成支脚部31,因此,可实施稳定的支承结构。
具体地,可通过支脚部31的垂直高度h确定上衬底10与下衬底20之间的间隔。
半导体元件50可安装在上衬底10与下衬底20之间。具体地,可通过粘合剂12将半导体元件50的顶面与上衬底10的金属层13接合,并可与上衬底10的金属层13电连接,可通过粘合剂22将半导体元件50的底面与下衬底20的金属层23接合,并可与下衬底20的金属层23电连接。粘合剂12和22可由导电材料,例如,银制成。
如上所述,由于支脚部31电连接在上衬底10的金属层13与下衬底20的金属层23之间,半导体元件50的顶面与上衬底10的金属层13电连接,并且半导体元件50的底面与下衬底20的金属层23电连接,因此半导体50的电极可与下衬底20的金属层23电连接,从而可替代现有功率模块的引线接合。
总之,根据本发明的示例性实施例,与现有引线接合相比,支脚部31电连接在半导体元件50的电极与下衬底20的金属层23之间,支脚部31的接合端部33的接合面积大于导线的接合面积,从而使抵抗外力的抵抗性(resistance)得以提高,并且支脚部31向半导体元件50集中地施加应力,因此将显著提高结构的刚度。
图2是根据本发明的另一示例性实施例的功率模块的透视图,并且图3是沿着图2的A-A线切开的截面图。
图2和图3示出上衬底10的金属层13上的三个支脚部31弯曲成朝向下衬底20倾斜的结构。
如此,根据本发明的示例性实施例,至少有三个支脚部31与下衬底20的金属层23接合,从而显著地提高了结构的稳定性。具体地,根据在图2至图3中所描述的示例性实施例,尽管能够提供任意数量的支脚部(例如,1、2、3、4、5,或更多),但优选提供3个支脚部。
此外,下衬底20的金属层23可一体地形成有电连接在半导体元件50与外部电路之间的引线41。因此,由于无需单独的引线41接合过程,因此制造过程将被简化,从而显著减少制造成本。
图4是根据本发明的又一示例性实施例的功率模块的侧视截面图。
参考图4,支脚部31可在下衬底20的金属层23上一体地形成。具体地,支脚部31可弯曲成从下衬底20的金属层23朝向上衬底10的金属层13倾斜,并且支脚部31的上端可形成有与上衬底10的金属层13接合的接合端部33。
其余组件与前述示例性实施例类似或相同,因此将省略其详细描述。
如上所述,根据本发明的示例性实施例,可在上衬底或下衬底上一体地形成将上衬底与下衬底彼此隔开的支脚部来替代单独的间隙子,从而减少电阻并提高耐久性,同时简化制造过程。
此外,根据本发明的示例性实施例,支脚部可控制上衬底与下衬底之间的间隔来装配半导体元件,从而有效地实现整体上的薄型结构,从而使功率模块小型化。
具体地,根据本发明的示例性实施例,代替间隙子,支脚部将上衬底与下衬底彼此隔开,将半导体元件的顶面与上衬底直接接合,并将半导体元件的底面与下衬底直接接合。因此,甚至当在高温条件下发生热膨胀时,也可减少施加在半导体元件上的应力,从而能防止上衬底和下衬底变形,因此,显著地提高了高温下的稳定性和可靠性。
此外,根据本发明的示例性实施例,由于支脚部将半导体元件与上衬底的金属层或下衬底的金属层电连接,因此无需单独地引线接合,因此提高了结构的稳定性。
在上文中,尽管已经参考示例性实施例和附图描述了本发明,但是本发明不限于此,而是在不违背在所附权利要求中主张的本发明的精神和范围的情况下,可由本发明所属领域内的技术人员做出各种修改和变化。
Claims (14)
1.一种功率模块,包括:
上衬底,其具有金属层;
下衬底,其与所述上衬底隔开,并具有面对所述上衬底的金属层的金属层;
半导体元件,其布置在所述上衬底和所述下衬底之间;以及
至少一个支脚部,其形成在所述上衬底的金属层和所述下衬底的金属层中的至少一者上,从而使所述上衬底与所述下衬底以预定的间隔彼此隔开,
其中,所述支脚部配置成将所述半导体元件与所述上衬底的金属层或所述下衬底的金属层电连接。
2.根据权利要求1所述的功率模块,其中,所述半导体元件的顶面和底面通过粘合剂与所述上衬底的金属层和所述下衬底的金属层电连接。
3.根据权利要求1所述的功率模块,其中所述上衬底的顶面和所述下衬底的底面分别设置有冷却模块。
4.一种功率模块,包括:
上衬底,其具有上绝缘层和形成在所述上绝缘层的底面上的金属层;
下衬底,其与所述上衬底隔开,并具有下绝缘层和形成在所述下绝缘层的顶面上的金属层;
半导体元件,其分别与上衬底的连接层和下衬底的连接层连接;以及
至少一个支脚部,其从所述上衬底的金属层朝向所述下衬底弯曲,
其中,所述支脚部具有与所述下衬底的金属层接合的接合端部。
5.根据权利要求4所述的功率模块,其中,所述支脚部的接合端部通过粘合剂与所述下衬底的金属层接合。
6.根据权利要求4所述的功率模块,其中所述支脚部形成为在所述上衬底的金属层的边缘处弯曲,并且所述上衬底的底面与所述下衬底的顶面之间的间隔基于所述支脚部的高度来确定。
7.根据权利要求4所述的功率模块,其中所述下衬底的金属层一体地形成有引线。
8.根据权利要求4所述的功率模块,其中所述上衬底还包括形成在所述上绝缘层的顶面上的金属层。
9.根据权利要求4所述的功率模块,其中,所述上衬底的上部与上冷却模块连接。
10.根据权利要求4所述的功率模块,其中所述下衬底还包括形成在所述下绝缘层的底面上的金属层。
11.根据权利要求4所述的功率模块,其中所述下衬底的下部与下冷却模块连接。
12.一种功率模块,包括:
上衬底,其具有上绝缘层和形成在所述上绝缘层的底面上的金属层;
下衬底,其与所述上衬底隔开,并具有下绝缘层和形成在所述下绝缘层的顶面上的金属层;
半导体元件,其分别与所述上衬底的连接层和所述下衬底的连接层连接;以及
至少一个支脚部,其从所述下衬底的金属层朝向所述上衬底弯曲,
其中所述支脚部具有与所述上衬底的金属层接合的接合端部。
13.根据权利要求12所述的功率模块,其中,所述支脚部的接合端部通过粘合剂与所述上衬底的金属层接合。
14.根据权利要求12所述的功率模块,其中所述支脚部形成为在所述下衬底的金属层的边缘处弯曲,并且所述上衬底的底面与所述下衬底的顶面之间的间隔基于所述支脚部的高度来确定。
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US (2) | US10062631B2 (zh) |
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KR101734712B1 (ko) | 2017-05-11 |
US20180350714A1 (en) | 2018-12-06 |
US20170170091A1 (en) | 2017-06-15 |
US10622276B2 (en) | 2020-04-14 |
US10062631B2 (en) | 2018-08-28 |
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