CN106711140B - 半导体器件及其形成方法 - Google Patents
半导体器件及其形成方法 Download PDFInfo
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- CN106711140B CN106711140B CN201610723801.XA CN201610723801A CN106711140B CN 106711140 B CN106711140 B CN 106711140B CN 201610723801 A CN201610723801 A CN 201610723801A CN 106711140 B CN106711140 B CN 106711140B
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Abstract
示例性半导体器件包括半导体衬底和在半导体衬底上方的互连结构。互连结构包括功能电路区和通过缓冲区与功能电路区间隔开的密封环的第一部分。器件还包括在互连结构上方的钝化层和在钝化层上方并且连接密封环的第一部分的密封环的第二部分。密封环的第二部分设置在缓冲区中。本发明的实施例还提供了一种形成半导体器件的方法。
Description
技术领域
本发明涉及半导体领域,更具体地,涉及半导体器件及其形成方法。
背景技术
由于许多电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成度的不断提高,半导体工业经历了快速发展。大体上,该集成度的改进源自最小部件尺寸(例如,缩小半导体工艺节点至小于20nm节点)的不断减小,其允许将更多的组件集成到给定的区域中。由于最近对微型化、更高速度和更大带宽以及更低功率消耗和等待时间(latency)的需求不断增长,因此亟需用于半导体管芯的更小和更具创造性的封装技术。
通常,通过使用焊料凸块的一种类型的封装件可将半导体管芯与在半导体管芯外部的其他器件连接。可通过首先在半导体管芯上形成一个或多个再分布层(RDL)/底接触金属化,然后在RDL/底接触金属化上放置焊料形成焊料凸块。在放置焊料之后,可实施回流操作以将焊料形成为期望的凸块形状。然后,可将焊料凸块放置与外部器件物理接触并可实施另一个回流操作以接合焊料凸块与外部器件。以这种方式,可在半导体管芯和外部器件之间产生诸如印刷电路板、另一个半导体管芯等的物理和电连接。
发明内容
本发明的实施例提供了一种半导体器件,包括:半导体衬底;在半导体衬底上方的互连结构,其中,互连结构包括:功能电路区;以及通过缓冲区与功能电路区间隔开的密封环的第一部分;在互连结构上方的钝化层;以及在钝化层上方并且连接密封环的第一部分的密封环的第二部分,其中,密封环的第二部分设置在缓冲区中。
本发明的实施例提供了一种半导体器件,包括:衬底;互连结构,包括在衬底的顶面处电连接至有源器件的第一导电部件;在互连结构上方的第一钝化层;密封环,包括:在互连结构中的第一部分,其中,第一部分包围第一导电部件并且通过缓冲区与第一导电部件间隔开;以及连接至第一部分并且在第一钝化层上方延伸的第二部分,其中,第二部分延伸至缓冲区中;在第一钝化层上方并且电连接至第一导电部件的第二导电部件,其中,第二导电部件和密封环的第二部分的顶面齐平;以及在第二导电部件上方的第一聚合物层,其中,第一聚合物层的侧壁在缓冲区中设置在密封环的第二部分的正上方。
本发明的实施例提供了一种形成半导体器件的方法,包括:包围器件管芯的互连结构中的第一导电部件形成密封环的第一部分,其中,通过缓冲区将密封环的第一部分与第一导电部件隔开;在互连结构上方沉积第一钝化层;在第一钝化层上方形成第二导电部件并电连接至至少一个第一导电部件;在第一钝化层上方形成密封环的第二部分,其中,密封环的第二部分延伸至缓冲区;在第二导电部件和密封环的第二部分的侧壁上方沉积第二钝化层并且沿着第二导电部件和密封环的第二部分的侧壁延伸;以及在第二钝化层上方沉积第一聚合物层,其中,第一聚合物层延伸至缓冲区并且包括设置在密封环的第二部分正上方的侧壁。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明。应该强调的是,根据工业中的标准实践,各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上,为了清楚的讨论,各种部件的数量和尺寸可以被任意增加或减少。
图1A至图8示出根据一些实施例,制造半导体器件的各个中间阶段的截面图和自顶向下的视图。
图9示出根据一些实施例,用于制造半导体器件的工艺流程图。
具体实施方式
以下公开提供了多种不同实施例或实例,用于实现本发明的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然,这些仅是实例并且不旨在限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外,本发明可以在多个实例中重复参考符号和/或字符。这种重复用于简化和清楚,并且其本身不表示所述多个实施例和/或配置之间的关系。
此外,在此可使用诸如“在…之下”、“在…下面”、“下面的”、“在…上面”、以及“上面的”等的空间关系术语,以容易地描述如图中所示的一个元件或部件与另一元件或部件的关系。应当理解,除图中所示的方位之外,空间关系术语将包括使用或操作中的装置的各种不同的方位。例如,如果翻转图中所示的装置,则被描述为在其他元件或部件“下面”或“之下”的元件将被定位为在其他元件或部件的“上面”。因此,示例性术语“在…下面”包括在上面和在下面的方位。装置可以以其它方式定位(旋转90度或在其他方位),并且通过在此使用的空间关系描述符进行相应地解释。
关于具体背景,即,晶圆级芯片尺寸封装(WLCSP)描述各个实施例。然而,可将其他实施例应用于其他类型的封装配置。
各个实施例包括具有器件管芯和延伸至器件管芯中的密封环的半导体器件封装件。密封环可包围器件管芯的内部功能电路区,所述器件管芯具有在所述器件管芯中形成的功能电路。在各个实施例中,可在密封环和器件管芯的功能电路区之间形成缓冲区(例如,没有功能电路或密封环部件)。可采用缓冲区以防止(或至少减少)在管芯加工期间由密封环所致的对器件管芯的内部电路区的损坏。可在管芯上方形成具有再分布线(RDL)的钝化层和/或聚合物层,并且密封环还可延伸至这些钝化层和聚合物层。在各个实施例中,至少设置在管芯上方的密封环的部分可进一步横向延伸至缓冲区中。在整个说明书中,术语“横向”用于描述基本上平行于下层衬底的主要表面的方向并且不用于描述任何绝对方位。聚合物层的边缘可设置在密封环上方(例如,在缓冲区中),因此,密封环可用作用于聚合物层的接合衬垫,这有利地减轻在随后的制造工艺期间产生的封装件中的应力并且减少制造缺陷(例如,分层)。
图1A示出根据一些实施例,器件管芯100的截面图。管芯100可为半导体管芯并且可为诸如处理器、逻辑电路、存储器、模拟电路、数字电路、复合信号等的任何类型的集成电路。尽管自始至终称为管芯,但可存在对管芯100的一些或所有加工,同时管芯100是更大晶圆的一部分(未示出)。可应用切割工艺以分隔管芯100与晶圆中的其他部件(例如,其他器件管芯)。
管芯100可包括衬底102、有源器件104和在衬底上方的互连结构106。例如,衬底102可包括掺杂或无掺杂的块状硅,或绝缘体上半导体(SOI)衬底的有源层。通常,SOI衬底包括在绝缘体层上形成的诸如硅的半导体材料层。例如,绝缘体层可为隐埋氧化物(BOX)层或氧化硅层。在诸如硅或玻璃衬底的衬底上提供绝缘体层。可选地,衬底102可包括诸如锗的另一个元素半导体;包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体;包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体;或其组合。还可使用诸如多层次或梯度衬底的其他衬底。
可在衬底102的顶面处形成诸如晶体管、电容器、电阻器、二极管、光电二极管、熔断器等的有源器件104。可在有源器件104和衬底102上方形成互连结构106。互连结构106可包括使用任何适当的方法形成的包含导电部件108(例如,导线和通孔)的层间介电层(ILD)和/或金属间介电(IMD)层。例如,ILD和IMD层可包括设置在这种导电部件之间的具有低于约4.0或甚至2.0的k值的低k介电材料。在一些实施例中,例如,ILD和IMD层可由磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂式玻璃、旋涂式聚合物、碳化硅材料、其化合物、其复合物、其组合等制成,并通过诸如旋涂、化学汽相沉积(CVD)和等离子体增强CVD(PECVD)的任何适当的方法形成。
可通过诸如单镶嵌或双镶嵌工艺的镶嵌工艺形成导电部件108。导电部件108由导电材料(例如,包括铜、铝、钨、其组合等)形成,并且导电部件108可加衬有扩散阻挡层和/或粘合层(未示出)。扩散阻挡层可由一个或多个TaN、Ta、TiN、Ti、CoW层等形成。互连结构106中的导电部件108电连接各个有源器件104以在管芯100内形成功能电路。由这种电路提供的功能可包括存储器结构、处理结构、传感器、放大器、配电、输入/输出电路等。本领域一般技术人员理解,仅为了例示目的提供上述实施例以进一步解释本发明的应用,并且实施例不意图以任何方式限制本发明。视情况,对于给定的应用使用其他电路。
还应该注意,可在ILD和IMD层的相邻层之间布置一个或多个蚀刻停止层(未示出)。通常,当形成通孔和/或接触件时,蚀刻停止层提供停止蚀刻工艺的机制。蚀刻停止层由与诸如下层衬底102和上层互连结构106的相邻层具有不同蚀刻选择性的介电材料形成。在一个实施例中,蚀刻停止层可由通过CVD或PECVD技术沉积的SiN、SiCN、SiCO、CN、其组合等形成。
如由图1A进一步示出的,互连结构106还包括一个或多个密封环110,所述密封环110也可能邻近导电部件108延伸通过ILD和IMD层。密封环110可提供保护管芯100的部件(例如,导电部件108)免受在管芯100的加工期间可能存在的水、化学品、残留物和/或污染物。如在图1B中提供的管芯100的自顶向下的视图中示出的,可沿着管芯100的外围形成各个密封环110并且密封环110可为形成以包围管芯100的功能电路区100A(例如,具有在那里形成的导电部件108的管芯100的区域)的连续结构。在图1B中,示出单个密封环110,尽管可包括多个密封环(例如,参见图1A)。此外,在图1B中,密封环110的形状基本上为矩形,尽管在其他实施例中,在自顶向下的视图中,密封环110可具有不同形状。返回参考图1A,密封环110可由导电材料形成。在一个实施例中,密封环110由与导电部件108相同的材料,与导电部件108同时并且通过与导电部件108相同的工艺形成。例如,密封环110可包括在各个ILD和IMD层中的导电线部分,其中导电通孔部分连接在ILD和IMD层之间的导线部分。
在各个实施例中,可将密封环110与有源器件104电隔离,并且密封环110不可形成具有有源器件104的任何功能电路。此外,可通过缓冲区100B(有时称为密封环延伸区(SREZ))将密封环110与管芯100的功能电路区100A间隔开。通过包括适当尺寸的缓冲区100B,可降低在密封环110的形成期间对导电部件108的损坏的风险。例如,在一个实施例中,缓冲区100B具有约5.4μm的横向尺寸W1,例如,尽管在其他实施例中缓冲区100B可具有不同尺寸。在这种实施例中,密封环110可横跨约9μm的横向尺寸W2,例如,尽管在其他实施例中,密封环110可占据不同的覆盖区(footprint)。此外,尽管图1A示出密封环110作为在衬底102的顶面处的停止,但在其他实施例中,密封环110可延伸至衬底102中。在一些实施例中,密封环110的底部可能基本上齐平或低于衬底102中的有源器件区的底部(例如,源极/漏极区104’)。
在互连结构106(包括导电部件108和密封环110)上方形成钝化层112,诸如在互连结构106中的最顶端金属化层上方。在一些实施例中,钝化层112可包括与下层ILD和IMD层类似的材料(例如,低k介电材料)。在其他实施例中,钝化层112可由诸如氧化硅、无掺杂硅酸盐玻璃、氮氧化硅等的非有机材料形成。还可使用其他适当的钝化材料。
图2至图6示出在管芯100上方形成输入/输出部件以形成晶圆级芯片尺寸封装件200的各个中间阶段的截面图。在图2中,在钝化层112上方形成各个互连部件。例如,可在钝化层112上方形成导电部件114。取决于封装件设计,导电部件114可为接触焊盘和/或RDL,并且导电部件114可包括诸如铝的金属材料,但可选地,可使用诸如铜的其他材料。
在一些实施例中,可使用诸如溅射的沉积工艺形成导电部件114从而形成材料层(未示出),然后可通过适当的工艺(诸如光刻掩模和蚀刻)去除材料层的部分以形成导电部件114。例如,在另一个实施例中,导电部件114的形成可包括沉积导电晶种层(未示出)、使用具有多个开口的掩模层(未示出)以限定导电部件114的形状、以及使用电化学电镀或无电镀电镀工艺填充掩模层中的开口。然后,可去除掩模层和晶种层的过多部分。可将导电部件114电连接至管芯100内的导电部件108,并且导电部件114的侧壁可能或可能不与管芯100的最顶端金属化层中的下层导电部件108的侧壁对齐(在图2中标记为108’)。例如,图2示出具有侧壁114S的导电部件114,所述侧壁114S与在导电部件114正下方的导电部件108的侧壁108S不对齐。在一些实施例中,侧壁114A和108S之间的横向距离W3可为约1μm,尽管在其他实施例中距离W3可能不同。
如通过图2进一步示出的,还可在管芯100上方形成密封环部分110’。在封装件200的自顶向下的视图(未示出)中,密封环部分110’可包围导电部件114。在一些实施例中,密封环部分110’可由与导电部件114相同的材料,与导电部件114同时并且使用与导电部件114相同的工艺形成。密封环部分110’可延伸通过钝化层112以接触管芯100内的密封环110的部分。此外,密封环部分110’可包括在缓冲区100B外部的部分110A和设置在缓冲区100B内的部分110B。在一些实施例中,缓冲区110B外部的部分110A具有横向尺寸W5,并且缓冲区100B中的部分110B具有横向尺寸W4。在各个实施例中,横向尺寸W4可为横向尺寸W5的至少约10%,并且横向尺寸W4可为至少约1μm。例如,在一个实施例中,横向尺寸W4为约3.24μm。观察到,通过延伸密封环110的部分至缓冲区100B中达到上述尺寸,由随后的加工产生的,生成的封装件的应力可被密封环110吸收,这有利地减少制造缺陷(例如,分层)。
接下来,在图3中,在导电部件114、密封环110和钝化层112上方形成钝化层116。在各个实施例中,可使用与上述关于钝化层112描述的类似的材料和/或类似的工艺形成钝化层116。例如,钝化层116可包括诸如氧化硅、无掺杂硅酸盐玻璃、氮氧化硅等的非有机材料。钝化层116和112的材料可能相同或可能不相同。在一些实施例中,可使用共形沉积工艺沉积钝化层116,并且钝化层116的厚度T1可为约0.8μm至约1μm。还可将钝化层116图案化(例如,使用光刻和/或蚀刻)以包括开口118,其至少暴露下层导电部件114的部分。在图案化之后,钝化层116的部分仍可覆盖导电部件114的边缘部分。
接下来参考图4,在钝化层116上方形成聚合物层120。聚合物层120可使用诸如旋转涂布技术、层压等的任何适当的方法由任何适当的材料(例如,聚酰亚胺(PI)、聚苯并噁唑(PBO)、苯并环丁烯(BCB)、环氧树脂、硅酮、丙烯酸酯、纳米填充的苯酚树脂、硅氧烷、氟化的聚合物、聚降冰片烯等)形成。在一些实施例中,沉积聚合物层120以具有约4μm至约7μm的厚度T2,尽管在其他实施例中厚度T2可能不同。在一些实施例中,聚合物层120和钝化层116可包括不同材料,其可在不同方向(例如,相反的方向)上将应力应用于管芯100。例如,聚合物层120可在朝向管芯100内部的方向(由箭头120S指示的)上应用拉伸应力,而钝化层116可在朝向管芯100外部的方向(由箭头116S指示的)上应用压缩应力。
聚合物层120可延伸超出功能电路区100A的边缘至缓冲区100B中横向尺寸W6。例如,在一个实施例中,横向尺寸W6可为约3.24μm至约5.86μm。在各个实施例中,聚合物层120的边缘120’可在缓冲区100B中的密封环部分110’正上方对齐。通过在密封环部分110’正上方设置聚合物层120的端点(例如,边缘120’),可使用密封环110吸收应力,所述应力在随后的制造工艺期间应用于封装件(例如,如由箭头120s和116s指示的,通过聚合物层120和钝化层116应用的应力)。这些随后的制造工艺可包括将其他封装元件(例如,表面安装技术(SMT)、其他管芯等)接合至封装件200、固化工艺(例如,固化聚合物层120)等。在这种实施例中,可减少由于这些随后的工艺产生的制造缺陷(例如,分层)的风险。
随后,在图5中,可使用任何适当的工艺将在聚合物层120中的开口122图案化。例如,在一个实施例中,聚合物层120包括感光材料并且使用光刻工艺将聚合物层120图案化。在这种实施例中,可使用光掩模(未示出)将聚合物层120的部分暴露。然后,可将聚合物层120显影,并且取决于使用正性或负性光刻胶,可将聚合物层120的暴露或未暴露的部分去除。在其他实施例中,可使用诸如激光蚀刻或任何其他适当的工艺的不同工艺将聚合物层120图案化。开口122可延伸通过聚合物层120以暴露导电部件114。
在图案化之后,可将固化工艺应用于聚合物层120以固化图案和硬化聚合物层120。固化工艺可包括将图案化聚合物层120的温度从室温(例如,约20摄氏度(℃))提高至适当的固化温度(例如,约200℃至约250℃)。在一个实施例中,可将聚合物层120的温度保持在固化温度时间为约两小时。由于固化工艺,聚合物层120可经历收缩(未明确示出)。例如,在固化工艺之后,可将聚合物层120总的横向尺寸W7减小约2μm。由于聚合物层120的边缘设置在密封环部分110’正上方,密封环110可至少部分吸收由该收缩所致的应力,这可有利地降低封装件200的分层或其他制造缺陷的风险。
图6示出在聚合物层120上方形成导电部件124。导电部件124可延伸通过聚合物层120并且电连接至下层导电部件114。在一些实施例中,可使用与上述关于导电部件114描述的类似的材料和/或工艺形成导电部件124。导电部件124和114的材料可能相同或可能不同。例如,在一个实施例中,导电部件124可包括铜,而导电部件114可包括铝。导电部件124可用作RDL以允许随后形成的外部连接件(例如,连接件130,参见图7)被放置在半导体管芯100上方的任何期望的位置中,而非将外部连接件的位置限制于导电部件114正上方的区域。
如由图6进一步示出的,可在聚合物层120和导电部件124上方形成额外的聚合物层126以保护各个下层部件。可使用与上述关于聚合物层120描述的类似的材料和/或工艺形成聚合物层126。例如,聚合物层126可具有约4μm至约7μm的厚度T3,尽管其他实施例可包括具有不同厚度的聚合物层。
在一些实施例中,聚合物层126可横向延伸通过聚合物层120的边缘120’。例如,聚合物层126可延伸超出功能电路区100A的边缘横向尺寸W8。在聚合物层120的横向尺寸W6为约3.24μm至约5.86μm的实施例中,横向尺寸W8可为约9μm。聚合物层126的边缘126’与聚合物层120的边缘120’不对齐。通过配置聚合物层120和126的边缘不对齐,可获得诸如改进的工艺控制、更容易的缺陷识别等的多种优点。在其他实施例中,聚合物层120和126的各个边缘120’和126’可基本上对齐。
在图7中,可使用任何适当的工艺将聚合物层126图案化以暴露导电部件124。例如,在一个实施例中,聚合物层126包括感光材料并使用上述光刻工艺图案化所述聚合物层126。在图案化后,可如上所述将聚合物层126固化以硬化聚合物层126。还可使用图案化聚合物层126的其他适当的方法(例如,蚀刻)。
接下来在图8中,在管芯100上方形成凸块下金属化层(UBM)128和外部连接件130。可形成与下层导电部件124电接触的UBM128。例如,UBM128可包括诸如钛层、铜层和镍层的三层导电材料。然而,材料和层的其他布置,诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置、铜/镍/金的布置等也适用于UBM128的形成。
可通过在聚合物层126上方并且沿着通过聚合物层126的开口内部形成每个层来制造UBM128。可使用诸如电化学电镀的电镀工艺实施每个层的形成,尽管可选地,取决于所需的材料可使用诸如溅射、蒸发或PECVD工艺的其他形成工艺。一旦形成需要的层,然后就通过适当的光刻掩模和蚀刻工艺将层的部分去除以去除不需要的材料以及留下诸如圆形、八边形、正方形或矩形的需要形状的UBM128,尽管可选地,可形成任何需要的形状。
外部连接件130可为接触凸块并且可包括诸如锡的材料,或诸如银、无铅锡或铜的其他适当的材料。在连接件130为锡焊料凸块的实施例中,可首先通过诸如蒸发、电镀、印刷、焊料转移、球配置等的适当的方法形成锡层来形成连接件130。一旦在结构上形成形成锡层,就实施回流以将材料形成为期望的凸块形状。外部连接件130可用于电连接封装件200与诸如另外的器件管芯、中介板、封装件衬底、印刷电路板、母板等的另外的封装元件。额外地,还可在封装件200上安装一个或多个其他部件(例如,SMT,未示出)。在安装期间,可降低对封装件200的应力以延伸密封环110至缓冲区100B中以及配置聚合物层120(例如,具有位于密封环110正上方的边缘)。
图9示出根据一些实施例,用于形成器件封装件的工艺流程图300。在步骤302中,提供器件管芯(例如,管芯100),器件管芯可包括功能电路区(例如,区100A)和包围功能电路区的密封环(例如,密封环110)。可通过缓冲区(例如,缓冲区100B)将密封环与功能电路区间隔开。在步骤304中,在器件管芯中的钝化层上方形成导电部件。导电部件可包括横向延伸至缓冲区中的密封环部分(例如,部分110’)。在步骤306中,在导电部件上方形成聚合物层(例如,聚合物层120)。聚合物层的边缘(例如,边缘120’)可设置在密封环正上方,并且聚合物层可横向延伸通过器件管芯的功能电路区的边缘。在步骤308中,可在聚合物层上方形成诸如额外的聚合物层、导电部件、UBM、外部连接件等的额外的封装部件。
实施例包括具有器件管芯和包围器件管芯的功能电路区的密封环的半导体器件封装件。可在密封环和器件管芯的功能电路区之间形成缓冲区。可使用缓冲区以防止(或至少减少)对器件管芯的电路区内的功能元件的损坏。在各个实施例中,设置在管芯的钝化层上方的密封环的至少一部分可进一步横向延伸至缓冲区中,并且在密封环上方形成的聚合物层的边缘可设置在缓冲区中的密封环正上方。因此,密封环可用作聚合物层的接合衬垫,这有利地吸收在随后的制造工艺期间产生的封装件中的应力并且减少制造缺陷(例如,分层)。
根据一个实施例,器件包括半导体衬底和在半导体衬底上方的互连结构。互连结构包括功能电路区和通过缓冲区与功能电路区间隔开的密封环的第一部分。器件还包括在互连结构上方的钝化层以及在钝化层上方并且连接密封环的第一部分的密封环的第二部分。密封环的第二部分设置在缓冲区中。
根据另一个实施例,器件包括衬底、包括电连接至在衬底的顶面处形成的有源器件的第一导电部件电的互连结构、和在互连结构上方的第一钝化层。器件还包括密封环,所述密封环具有在互连结构中的第一部分和连接至第一部分并且在第一钝化层上方延伸的第二部分。第一部分包围第一导电部件并且通过缓冲区与第一导电部件间隔开,并且第二部分延伸至缓冲区中。器件还包括在第一钝化层上方并且电连接至第一导电部件的第二导电部件。第二导电部件和所述密封环的第二部分的顶面基本齐平。器件还包括在密封环和第二导电部件上方的第一聚合物层。第一聚合物层的侧壁设置在缓冲区中的密封环的第二部分正上方。
根据另一个实施例,方法包括形成密封环的第一部分,密封环的第一部分包围器件管芯的互连结构中的第一导电部件,在互连结构上方沉积第一钝化层,在第一钝化层上方形成第二导电部件并电连接至至少一个第一导电部件,以及在第一钝化层上方形成密封环的第二部分。通过缓冲区将密封环的第一部分与第一导电部件隔开,以及将密封环的第二部分电连接至密封环的第一部分并且延伸至缓冲区。方法还包括在第二导电部件和密封环的第二部分的侧壁上方沉积第二钝化层并且沿着第二导电部件和密封环的第二部分的侧壁延伸以及在第二钝化层上方沉积第一聚合物层。第一聚合物层延伸至缓冲区并且包括设置在密封环的第二部分正上方的侧壁。
本发明的实施例提供了一种半导体器件,包括:半导体衬底;在半导体衬底上方的互连结构,其中,互连结构包括:功能电路区;以及通过缓冲区与功能电路区间隔开的密封环的第一部分;在互连结构上方的钝化层;以及在钝化层上方并且连接密封环的第一部分的密封环的第二部分,其中,密封环的第二部分设置在缓冲区中。
根据本发明的一个实施例,还包括在钝化层上方的聚合物层,其中,聚合物层的边缘在缓冲区中设置在密封环的第二部分正上方。
根据本发明的一个实施例,还包括在聚合物层上方的额外的聚合物层,其中,额外的聚合物层横向延伸通过聚合物层的边缘。
根据本发明的一个实施例,功能电路区包括在半导体衬底的顶面处电连接至有源器件的第一导电部件,其中,器件还包括在功能电路区正上方并电连接至第一导电部件的第二导电部件,并且其中,第二导电部件与密封环的第二部分齐平。
根据本发明的一个实施例,还包括通过缓冲区与功能电路区间隔开的密封环的第三部分,其中,密封环的第三部分连接密封环的第二部分与密封环的第一部分,并且其中,密封环的第三部分和密封环的第二部分的顶面齐平。
根据本发明的一个实施例,密封环的第二部分的横向尺寸至少为密封环的第三部分的横向尺寸的10%。
根据本发明的一个实施例,密封环的第二部分的横向尺寸为1μm或更大。
根据本发明的一个实施例,密封环包围功能电路区,并且其中,密封环在半导体衬底的顶面处与有源器件电隔离。
本发明的实施例提供了一种半导体器件,包括:衬底;互连结构,包括在衬底的顶面处电连接至有源器件的第一导电部件;在互连结构上方的第一钝化层;密封环,包括:在互连结构中的第一部分,其中,第一部分包围第一导电部件并且通过缓冲区与第一导电部件间隔开;以及连接至第一部分并且在第一钝化层上方延伸的第二部分,其中,第二部分延伸至缓冲区中;在第一钝化层上方并且电连接至第一导电部件的第二导电部件,其中,第二导电部件和密封环的第二部分的顶面齐平;以及在第二导电部件上方的第一聚合物层,其中,第一聚合物层的侧壁在缓冲区中设置在密封环的第二部分的正上方。
根据本发明的一个实施例,密封环的第二部分包围第二导电部件。
根据本发明的一个实施例,还包括在密封环的第二部分和第二导电部件的侧壁上方并且沿着密封环的第二部分和第二导电部件的侧壁延伸的第二钝化层,其中,第二钝化层设置在第一聚合物层下方。
根据本发明的一个实施例,还包括:在第一聚合物层上方的第二聚合物层;在第二聚合物层上方并且电连接至第二导电部件的第三导电部件;在第三导电部件上方并且电连接至第三导电部件的凸块下金属化层(UBM);以及在凸块下金属化层上方并且电连接至凸块下金属化层的外部连接件。
根据本发明的一个实施例,第二聚合物层延伸通过第一聚合物层的侧壁。
根据本发明的一个实施例,密封环的第二部分的第一侧壁设置在密封环的第一部分正上方,并且其中,密封环的第二部分的第二侧壁设置在缓冲区中。
根据本发明的一个实施例,密封环延伸通过互连结构。
本发明的实施例提供了一种形成半导体器件的方法,包括:包围器件管芯的互连结构中的第一导电部件形成密封环的第一部分,其中,通过缓冲区将密封环的第一部分与第一导电部件隔开;在互连结构上方沉积第一钝化层;在第一钝化层上方形成第二导电部件并电连接至至少一个第一导电部件;在第一钝化层上方形成密封环的第二部分,其中,密封环的第二部分延伸至缓冲区;在第二导电部件和密封环的第二部分的侧壁上方沉积第二钝化层并且沿着第二导电部件和密封环的第二部分的侧壁延伸;以及在第二钝化层上方沉积第一聚合物层,其中,第一聚合物层延伸至缓冲区并且包括设置在密封环的第二部分正上方的侧壁。
根据本发明的一个实施例,还包括在沉积第一聚合物层之后,固化第一聚合物层。
根据本发明的一个实施例,还包括:图案化第二钝化层中的第一开口;图案化第一聚合物层中的第二开口,第二开口与第一开口连接,其中,第一开口和第二开口暴露第二导电部件;在第一聚合物层上方形成第三导电部件并且延伸通过第一开口和第二开口;以及在第三导电部件上方沉积第二聚合物层。
根据本发明的一个实施例,沉积第二聚合物层包括沉积第二聚合物层以横向延伸通过第一聚合物层。
根据本发明的一个实施例,形成密封环的第二部分包括与形成第二导电部件同时使用相同的工艺。
上面论述了若干实施例的部件,使得本领域技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员也应该意识到,这些等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (25)
1.一种半导体器件,包括:
半导体衬底;
在所述半导体衬底上方的互连结构,其中,所述互连结构包括:
功能电路区;以及
通过缓冲区与所述功能电路区间隔开的密封环的第一部分,其中在所述半导体器件的顶视图中,所述密封环的第一部分连续包围所述功能电路区,其中所述密封环在所述半导体衬底的顶面处与有源器件电隔离;
在所述互连结构上方的钝化层;以及
在所述钝化层上方并且连接所述密封环的第一部分的所述密封环的第二部分,其中,所述密封环的第二部分设置在所述缓冲区中。
2.根据权利要求1所述的半导体器件,还包括在所述钝化层上方的聚合物层,其中,所述聚合物层的边缘在所述缓冲区中设置在所述密封环的第二部分正上方。
3.根据权利要求2所述的半导体器件,还包括在所述聚合物层上方的额外的聚合物层,其中,所述额外的聚合物层横向延伸通过所述聚合物层的边缘。
4.根据权利要求1所述的半导体器件,其中,所述功能电路区包括在所述半导体衬底的顶面处电连接至有源器件的第一导电部件,其中,所述半导体器件还包括在所述功能电路区正上方并电连接至所述第一导电部件的第二导电部件,并且其中,所述第二导电部件与所述密封环的第二部分齐平。
5.根据权利要求1所述的半导体器件,还包括通过所述缓冲区与所述功能电路区间隔开的所述密封环的第三部分,其中,所述密封环的第三部分连接所述密封环的第二部分与所述密封环的第一部分,并且其中,所述密封环的第三部分和所述密封环的第二部分的顶面齐平。
6.根据权利要求5所述的半导体器件,其中,所述密封环的第二部分的横向尺寸至少为所述密封环的第三部分的横向尺寸的10%。
7.根据权利要求1所述的半导体器件,其中,所述密封环的第二部分的横向尺寸为1μm或更大。
8.根据权利要求1所述的半导体器件,其中,所述缓冲区在所述半导体衬底和所述钝化层之间无任何导电部件,并且其中,所述密封环的第二部分不在任何导电部件的正上方延伸。
9.一种半导体器件,包括:
衬底;
互连结构,包括在所述衬底的顶面处电连接至有源器件的第一导电部件;
在所述互连结构上方的第一钝化层;
密封环,包括:
在所述互连结构中的第一部分,其中,所述第一部分通过缓冲区与所述第一导电部件间隔开,并且其中在所述半导体器件的顶视图中,所述第一部分完全包围所述第一导电部件;以及
连接至所述第一部分并且在所述第一钝化层上方延伸的第二部分,其中,所述第二部分延伸至所述缓冲区中,其中所述密封环的第二部分的第一侧壁设置在所述密封环的第一部分正上方,并且其中,所述密封环的第二部分的第二侧壁设置在所述缓冲区中;
在所述第一钝化层上方并且电连接至所述第一导电部件的第二导电部件,其中,所述第二导电部件和所述密封环的第二部分的顶面齐平;以及
在所述第二导电部件上方的第一聚合物层,其中,所述第一聚合物层的侧壁在所述缓冲区中设置在所述密封环的第二部分的正上方。
10.根据权利要求9所述的半导体器件,其中,所述密封环的第二部分包围所述第二导电部件。
11.根据权利要求9所述的半导体器件,还包括在所述密封环的第二部分和所述第二导电部件的侧壁上方并且沿着所述密封环的第二部分和所述第二导电部件的侧壁延伸的第二钝化层,其中,所述第二钝化层设置在所述第一聚合物层下方。
12.根据权利要求9所述的半导体器件,还包括:
在所述第一聚合物层上方的第二聚合物层;
在所述第二聚合物层上方并且电连接至所述第二导电部件的第三导电部件;
在所述第三导电部件上方并且电连接至所述第三导电部件的凸块下金属化层(UBM);以及
在所述凸块下金属化层上方并且电连接至所述凸块下金属化层的外部连接件。
13.根据权利要求12所述的半导体器件,其中,所述第二聚合物层延伸通过所述第一聚合物层的侧壁。
14.根据权利要求9所述的半导体器件,其中,所述密封环的第二部分的第一侧壁设置在所述缓冲区的外侧。
15.根据权利要求9所述的半导体器件,其中,所述密封环延伸通过所述互连结构。
16.一种形成半导体器件的方法,包括:
形成密封环的第一部分,在所述半导体器件的顶视图中,所述密封环的第一部分包围器件管芯的互连结构中的第一导电部件,其中,通过缓冲区将所述密封环的第一部分与所述第一导电部件隔开;
在所述互连结构上方沉积第一钝化层;
在所述第一钝化层上方形成第二导电部件并电连接至至少一个所述第一导电部件;
在所述第一钝化层上方形成密封环的第二部分,其中,所述密封环的第二部分延伸至所述缓冲区;
在所述第二导电部件和所述密封环的第二部分的侧壁上方沉积第二钝化层并且沿着所述第二导电部件和所述密封环的第二部分的侧壁延伸;以及
在所述第二钝化层上方沉积第一聚合物层,其中,所述第一聚合物层延伸至所述缓冲区并且包括设置在所述密封环的第二部分正上方的侧壁。
17.根据权利要求16所述的方法,还包括在沉积所述第一聚合物层之后,固化所述第一聚合物层。
18.根据权利要求16所述的方法,还包括:
图案化所述第二钝化层中的第一开口;
图案化所述第一聚合物层中的第二开口,所述第二开口与所述第一开口连接,其中,所述第一开口和所述第二开口暴露所述第二导电部件;
在所述第一聚合物层上方形成第三导电部件并且延伸通过所述第一开口和所述第二开口;以及
在所述第三导电部件上方沉积第二聚合物层。
19.根据权利要求18所述的方法,其中,沉积所述第二聚合物层包括沉积所述第二聚合物层以横向延伸通过所述第一聚合物层。
20.根据权利要求16所述的方法,其中,形成所述密封环的第二部分包括与形成所述第二导电部件同时使用相同的工艺。
21.一种半导体器件,包括:
互连结构,包括:
第一导电部件,在半导体衬底的顶面处电连接至有源器件;以及
第二导电部件,所述第二导电部件在所述半导体器件的顶视图中,包围所述第一导电部件,并且所述第二导电部件在所述半导体衬底的顶面处与任何有源器件电隔离;
在所述互连结构上方的钝化层;
第三导电部件,在所述钝化层上方并且延伸穿过所述钝化层,其中垂直于所述半导体衬底的主表面的第一线延伸穿过所述第三导电部件和所述第二导电部件,并且其中,垂直于所述半导体衬底的主表面的第二线也延伸穿过所述第三导电部件并且进一步在所述第一导电部件和所述第二导电部件之间延伸;
第四导电部件,与所述第三导电部件位于同一层中,其中所述第四导电部件电连接至一个或多个所述第一导电部件;以及
在所述钝化层上方的第一聚合物层,其中所述第一聚合物层的侧壁设置在所述第三导电部件的正上方。
22.根据权利要求21所述的半导体器件,进一步包括在所述第一聚合物层上方的第二聚合物层,其中所述第二聚合物层沿着所述第一聚合物层的侧壁延伸,并且其中所述第二聚合物层的侧壁设置在所述第三导电部件的正上方。
23.根据权利要求21所述的半导体器件,进一步包括第五导电部件,位于所述第一聚合物层上方并且延伸穿过所述第一聚合物层,其中所述第五导电部件电连接至所述第四导电部件。
24.根据权利要求21所述的半导体器件,其中,所述钝化层在第一方向上向所述半导体器件施加应力,并且其中所述第一聚合物层在与所述第一方向相对的第二方向上向所述半导体器件施加应力。
25.根据权利要求21所述的半导体器件,其中,所述第一导电部件与所述第二导电部件通过缓冲区隔开,并且其中,所述缓冲区在所述半导体衬底和所述钝化层之间无任何导电部件。
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