TWI743063B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI743063B
TWI743063B TW105136807A TW105136807A TWI743063B TW I743063 B TWI743063 B TW I743063B TW 105136807 A TW105136807 A TW 105136807A TW 105136807 A TW105136807 A TW 105136807A TW I743063 B TWI743063 B TW I743063B
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Taiwan
Prior art keywords
sealing ring
conductive feature
polymer layer
layer
passivation layer
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TW105136807A
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TW201724361A (zh
Inventor
潘信瑜
普翰屏
曹佩華
徐語晨
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置，其包含半導體基底及所述半導體基底上方的內連線結構。所述內連線結構包含功能電路區域及藉由緩衝區與所述功能電路區域間隔開的封環的第一部分。所述裝置亦包含所述內連線結構上方的鈍化層及在所述鈍化層上方且連接所述封環的所述第一部分的所述封環的第二部分。所述封環的所述第二部分設置於所述緩衝區中。

Description

半導體裝置
本發明實施例是關於一種半導體裝置，且特別是有關於一種半導體裝置之封環結構。
半導體行業歸因於各種電子組件(例如，電晶體、二極體、電阻器、電容器等)的整合密度的持續改良而已經歷快速增長。整合密度的此改良主要來自最小特徵大小的不斷減小(例如，使半導體製程節點朝向次20nm節點縮減)，其允許更多組件整合於給定區域中。隨著近來對小型化、較高速度以及較大頻寬以及較低功率消耗及潛時的需求的增長，對半導體晶粒的更小且更具創造性的封裝技術的需要已增長。
一般而言，半導體晶粒可經由利用焊料凸塊的一種類型的封裝連接至半導體晶粒外部的其他裝置。可藉由最初在半導體晶粒上形成一或多個重佈層(redistribution layer，RDL)/底面接觸金屬化物且接著將焊料置放於所述RDL/底面接觸金屬化物上而形成焊料凸塊。在已置放焊料之後，可執行回焊操作以便將焊料塑形為所要凸塊形狀。可接著將焊料凸塊置放成與外部裝置實體接觸，且可執行另一回焊操作以便使焊料凸塊與外部裝置結合。以 此方式，可在半導體晶粒與外部裝置(諸如，印刷電路板、另一半導體晶粒或其類似者)之間形成實體連接及電連接。
本發明實施例提出一種半導體裝置，其包含半導體基底及所述半導體基底上方的內連線結構。所述內連線結構包含功能電路區域及藉由緩衝區與所述功能電路區域間隔開的封環的第一部分。所述半導體裝置亦包含所述內連線結構上方的鈍化層及在所述鈍化層上方且連接所述封環的所述第一部分的所述封環的第二部分。所述封環的所述第二部分設置於所述緩衝區中。
100:裝置晶粒/晶粒
100A:功能電路區域
100B:緩衝區/緩衝區域
102:基底/底下基底
104:主動元件
104':源極/汲極區域
106:內連線結構/上覆內連線結構
108:導電特徵
108S:側壁
108':最高金屬化物層
110:封環
110':封環部分
110A:部分
110B:部分
112:鈍化層
114:導電特徵
114S:側壁
116:鈍化層
116S:箭頭
118:開口
120:聚合物層
120S:箭頭
120':邊緣
122:開口
124:導電特徵
126:額外聚合物層/聚合物層
126':邊緣
128:凸塊下金屬化物(UBM)
130:連接器/外部連接器
200:晶圓級晶片尺度封裝/封裝
300:製程流程
302~308:步驟
T1:厚度
T2:厚度
T3:厚度
W1:側向尺寸
W2:側向尺寸
W3:側向距離/距離
W4:側向尺寸
W5:側向尺寸
W6:側向尺寸
W7:總體側向尺寸
W8:側向尺寸
當結合附圖閱讀時，自以下詳細描述最好地理解本發明的態樣。應注意，根據行業中的標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意地增大或減小各種特徵的尺寸。
圖1A至圖1B以及圖2至圖8說明根據一些實施例的製造半導體裝置的各個中間階段的橫截面圖及俯視圖。
圖9說明用於製造根據一些實施例的半導體裝置的製程流程。
以下揭露內容提供用於實施本發明的不同特徵的許多不 同實施例或實例。在下文中描述組件及配置的特定實例以簡化本發明。當然，這些實例僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵以及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本發明可在各種實例中重複參考標號及/或字母。此重複是出於簡單性及清晰性的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
另外，諸如「在...之下」、「在...下方」、「下部」、「在...上方」、「上部」以及其類似者的空間相對術語可在本文中為易於描述而使用，以描述如圖中所說明的一個元件或特徵與另一元件或特徵的關係。除了諸圖中所描繪的定向以外，空間相對術語亦意欲涵蓋裝置在使用或操作中的不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
參照特定上下文，即晶圓級晶片尺度封裝(wafer level chip scale packaging，WLCSP)，描述各種實施例。然而，其他實施例可應用於其他類型的封裝組態。
各種實施例包含具有裝置晶粒及延伸至裝置晶粒中的封環的半導體裝置封裝。封環可圍繞內部形成有功能電路的裝置晶粒的內部功能電路區域。在各種實施例中，緩衝區(例如，不具有功能電路或封環特徵)可形成在封環與裝置晶粒的功能電路區域之間。可採用緩衝區以便防止(或至少減少)在晶粒處理期間由封環引起的對裝置晶粒的內部電路區域的損壞。具有重佈線 (redistribution line，RDL)的鈍化層及/或聚合物層可形成在晶粒上方，且封環亦可延伸至這些鈍化層及聚合物層中。在各種實施例中，設置於晶粒上方的封環的至少一部分可進一步側向延伸至緩衝區中。貫穿描述，術語「側向」用於描述實質上平行於底下基底的主表面的方向且並不用於描述任何絕對定向。聚合物層的邊緣可設置在封環上方(例如，在緩衝區中)，且因此，封環可被用作聚合物層的著陸墊，此有利地減輕在後續製造製程期間所得封裝中的應力且減少製造缺陷(例如，分層)。
圖1A說明根據一些實施例的裝置晶粒100的橫截面圖。晶粒100可為半導體晶粒且可為任何類型的積體電路，諸如處理器、邏輯電路、記憶體、類比電路、數位電路、混合訊號以及其類似者。儘管通篇被稱作晶粒，但對晶粒100的一些或所有處理可在晶粒100為較大晶圓(未說明)的一部分時進行。可應用單體化製程以將晶粒100與晶圓中的其他特徵(例如，其他裝置晶粒)分離。
晶粒100可包含基底102、主動元件104以及基底上方的內連線結構106。基底102可包括例如經摻雜的基體矽或未經摻雜的基體矽，或絕緣層上有矽(semiconductor-on-insulator，SOI)基底的主動層。一般而言，SOI基底包括形成於絕緣層上的半導體材料(諸如，矽)的層。絕緣層可為例如內埋氧化物(buried oxide，BOX)層或氧化矽層。絕緣層提供於基底(諸如，矽基底或玻璃基底)上。或者，基底102可包含另一基本半導體，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、 GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層基底或梯度基底。
主動元件104(諸如，電晶體、電容器、電阻器、二極體、光二極體、熔絲以及其類似者)可形成在基底102的頂部表面處。內連線結構106可形成在主動元件104及基底102上方。內連線結構106可包含使用任何合適的方法所形成的含有導電特徵108(例如，導電線及導通孔)的層間介電(inter-layer dielectric，ILD)層及/或金屬間介電(inter-metal dielectric，IMD)層。ILD層及IMD層可包含設置於此些導電特徵之間的具有例如小於約4.0或甚至2.0的k值的低k介電材料。在一些實施例中，ILD層及IMD層可由例如磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼磷矽玻璃(borophosphosilicate glass，BPSG)、氟矽酸鹽玻璃(fluorosilicate glass，FSG)、SiOxCy、旋塗式玻璃、旋塗式聚合物、碳化矽材料、其化合物、其複合物、其組合或其類似者製成；由任何合適的方法(諸如，自旋、化學氣相沈積(chemical vapor deposition，CVD)以及電漿增強型CVD(plasma-enhanced CVD，PECVD))形成。
導電特徵108可藉由金屬鑲嵌製程形成，諸如單金屬鑲嵌製程或雙金屬鑲嵌製程。導電特徵108由導電材料(例如，包括銅、鋁、鎢、其組合以及其類似者)形成且導電特徵108可內襯有擴散障壁層及/或黏著層(未展示)。擴散障壁層可由TaN、Ta、TiN、Ti、CoW或其類似者的一或多個層形成。內連線結構106中的導電特徵108將各種主動元件104電連接以在晶粒100內形成功能電路。由此些電路所提供的功能可包含記憶體結構、處理結構、感測器、放大器、功率分佈、輸入/輸出電路或其類似者。一般熟習 此項技術者將瞭解，以上實例僅是出於說明的目的而提供以進一步解釋本發明的應用且並不意欲以任何方式限制本發明。可在適合於給定應用的情況下使用其他電路。
亦應注意，一或多個蝕刻終止層(未展示)可位於ILD層及IMD層的相鄰者之間。一般而言，蝕刻終止層提供當形成導通孔及/或接點時終止蝕刻製程的機制。蝕刻終止層由與相鄰層(例如，底下基底102及上覆內連線結構106)具有不同蝕刻選擇性的介電材料形成。在實施例中，蝕刻終止層可由SiN、SiCN、SiCO、CN、其組合或其類似者形成；藉由CVD技術或PECVD技術沈積。
如藉由圖1A進一步說明，內連線結構106進一步包含一或多個封環110，其亦可延伸穿過與導電特徵108相鄰的ILD層及IMD層。封環110可在處理晶粒100期間提供對晶粒100的特徵(例如，導電特徵108)的保護使其免於受到存在的水、化學物質、殘餘物及/或污染物之害。每一封環110可沿著晶粒100的周邊形成且可為經形成以環繞晶粒100的功能電路區域100A(例如，具有形成在此處的導電特徵108的晶粒100的區域)的連續結構，如提供於圖1B中的晶粒100的俯視圖中所說明。在圖1B中，說明單個封環110，但可包含多個封環(例如，參見圖1A)。此外，在圖1B中，封環110在形狀上實質上為矩形，但在其他實施例中，封環110在俯視圖中可具有不同形狀。返回參照圖1A，封環110可由導電材料形成。在實施例中，封環110與導電特徵108由相同材料、在相同時間以及藉由相同製程形成。舉例而言，封環110可包含各種ILD層及IMD層中的導電線部分，導電導通孔部分在ILD層與IMD層之間連接導電線部分。
在各種實施例中，封環110可與主動元件104電性隔離，且封環110可不與主動元件104形成任何功能電路。此外，封環110可藉由緩衝區100B(有時被稱作封環延伸區(seal ring extension zone，SREZ))與晶粒100的功能電路區域100A間隔開。藉由包含具有合適大小的緩衝區100B，在形成封環110期間對導電特徵108造成損壞的風險可降低。舉例而言，在實施例中，緩衝區100B具有例如約5.4μm的側向尺寸W1，但在其他實施例中緩衝區100B可具有不同尺寸。在此類實施例中，封環110可橫跨例如約9μm的側向尺寸W2，但在其他實施例中封環110可佔據不同佔據面積。此外，儘管圖1A將封環110說明為在基底102的頂部表面處終止，但在其他實施例中，封環110可延伸至基底102中。在一些實施例中，封環110的底部可實質上與基底102中的主動元件區域(例如，源極/汲極區域104')的底部齊平或低於所述底部。
鈍化層112形成於內連線結構106(包括導電特徵108及封環110)上方，諸如在內連線結構106中的最高金屬化物層上方。在一些實施例中，鈍化層112可包含與底下ILD層及底下IMD層類似的材料(例如，低k介電質)。在其他實施例中，鈍化層112可由非有機材料(諸如，氧化矽、未經摻雜的矽酸鹽玻璃、氮氧化矽以及其類似者)形成。亦可使用其他合適的鈍化材料。
圖2至圖6說明在晶粒100上方形成輸入/輸出特徵以形成晶圓級晶片尺度封裝200的各個中間階段的橫截面圖。在圖2中，各種內連特徵形成於鈍化層112上方。舉例而言，導電特徵114可形成在鈍化層112上方。導電特徵114可取決於封裝設計而 為接觸墊及/或RDL，且導電特徵114可包括金屬材料，諸如鋁；但可替代地使用其他材料，諸如銅。
在一些實施例中，可使用沈積製程(諸如，濺鍍)形成材料(未展示)的層且所述材料層的部分可接著經由合適的製程(諸如，微影遮蔽及蝕刻)移除以形成導電特徵114，而形成導電特徵114。在另一實施例中，導電特徵114的形成可包含沈積導電晶種層(未展示)，使用具有各種開口的遮罩層(未展示)以界定導電特徵114的形狀，以及使用例如電化學電鍍或無電極電鍍製程填充遮罩層中的開口。可接著移除遮罩層及晶種層的過量部分。導電特徵114可電連接至晶粒100內的導電特徵108，且導電特徵114的側壁可或可不與晶粒100的最高金屬化物層(在圖2中標記為108')中的底下導電特徵108的側壁對準。舉例而言，圖2說明導電特徵114的側壁114S與在導電特徵114正下方的導電特徵108的側壁108S未對準。在一些實施例中，側壁114S與側壁108S之間的側向距離W3可為約1μm，但在其他實施例中距離W3可不同。
如藉由圖2進一步說明，封環部分110'亦可形成於晶粒100上方。在封裝200(未展示)的俯視圖中，封環部分110'可圍繞導電特徵114。在一些實施例中，封環部分110'與導電特徵114可由相同材料、在相同時間以及使用相同製程形成。封環部分110'可延伸穿過鈍化層112以接觸晶粒100內的封環110的各部分。此外，封環部分110'可包含在緩衝區100B外的部分110A及設置於緩衝區100B內的部分110B。在一些實施例中，在緩衝區100B外的部分110A具有側向尺寸W5，且緩衝區100B中的部分110B 具有側向尺寸W4。在各種實施例中，側向尺寸W4可至少約為側向尺寸W5的10%，且側向尺寸W4可至少約為1μm。舉例而言，在實施例中，側向尺寸W4為約3.24μm。已觀測到，藉由將封環110的一部分延伸至緩衝區100B中直至上述尺寸，歸因於後續處理而對於所得封裝的應力可由封環110吸收，此有利地減少製造缺陷(例如，分層)。
接下來在圖3中，鈍化層116形成於導電特徵114、封環110以及鈍化層112上方。在各種實施例中，鈍化層116可使用如在上文中關於鈍化層112所描述的類似材料及/或類似製程形成。舉例而言，鈍化層116可包括非有機材料，諸如氧化矽、未經摻雜的矽酸鹽玻璃、氮氧化矽以及其類似者。鈍化層116及鈍化層112的材料可相同或可不相同。在一些實施例中，鈍化層116可使用共形(cinformal)沈積製程沈積，且鈍化層116的厚度T1可為約0.8μm至約1μm。鈍化層116可進一步經圖案化(例如，使用微影及/或蝕刻)以包含開口118，其至少曝露底下導電特徵114的部分。在圖案化之後，鈍化層116的部分可仍覆蓋導電特徵114的邊緣部分。
接下來參看圖4，聚合物層120形成於鈍化層116上方。聚合物層120可使用任何合適的方法(諸如，旋塗式塗佈技術、疊層以及其類似者)由任何合適的材料(例如，聚醯亞胺(polyimide，PI)、聚苯并噁唑(polybenzoxazole，PBO)、苯環丁烷(benzocyclobuten，BCB)、環氧樹脂、矽酮、丙烯酸酯、奈米填充的酚系樹脂、矽氧烷、經氟化的聚合物、聚降冰片烯以及其類似者)形成。在一些實施例中，聚合物層120經沈積以具有約4μm 至約7μm的厚度T2，但在其他實施例中厚度T2可不同。在一些實施例中，聚合物層120及鈍化層116可包括不同材料，其可以不同方向(例如，相反方向)將應力施加於晶粒100。舉例而言，聚合物層120可以朝向晶粒100的內部的方向(由箭頭120S指示)施加拉伸應力，而鈍化層116可以朝向晶粒100的外部的方向(由箭頭116S指示)施加壓縮應力。
聚合物層120可延伸超出功能電路區域100A的邊緣並進入緩衝區100B中達側向尺寸W6。舉例而言，在實施例中，側向尺寸W6可為約3.24μm至約5.86μm。在各種實施例中，聚合物層120的邊緣120'可在緩衝區100B中直接對準於封環部分110'上方。藉由將聚合物層120的端點(例如，邊緣120')直接設置在封環部分110'上方，可使用封環110吸收在後續製造過程期間施加至封裝的應力(例如，由聚合物層120及鈍化層116所施加的應力，如由箭頭120s及箭頭116s所指示)。這些後續製造過程可包含將其他封裝組件(例如，表面黏著技術(surface mount technology，SMT)、其他晶粒以及其類似者)結合至封裝200；固化製程(例如，固化聚合物層120)以及其類似者。在此類實施例中，由於這些後續製程的製造缺陷(例如，分層)的風險可降低。
隨後，在圖5中，開口122可在聚合物層120中使用任何合適的製程經圖案化。舉例而言，在實施例中，聚合物層120包括感光性材料，且聚合物層120使用微影製程經圖案化。在此類實施例中，可使用光罩(未繪示)曝光聚合物層120的部分。可接著顯影聚合物層120，且可取決於使用正性抗蝕劑還是負性抗蝕劑而移除聚合物層120的曝光部分或未曝光部分。在其他實施例中， 聚合物層120可使用不同製程(諸如，雷射蝕刻或任何其他合適的製程)經圖案化。開口122可延伸穿過聚合物層120以曝露導電特徵114。
在圖案化之後，可將固化製程施加於聚合物層120以固化圖案且硬化聚合物層120。固化製程可包含使經圖案化聚合物層120的溫度自室溫(例如，約攝氏20度(C))升高至合適的固化溫度(例如，約200℃與約250℃之間)。在實施例中，聚合物層120的溫度可維持在固化溫度下約兩個小時。由於固化製程，聚合物層120可經歷收縮(並未明確地說明)。舉例而言，聚合物層120的總體側向尺寸W7可在固化製程之後減小約2μm。由於聚合物層120的邊緣直接設置在封環部分110'上方，因此封環110可至少部分地吸收由此收縮產生的應力，此可有利地降低封裝200的分層或其他製造缺陷的風險。
圖6說明導電特徵124在聚合物層120上方的形成。導電特徵124可延伸穿過聚合物層120且電連接至底下導電特徵114。在一些實施例中，導電特徵124可使用如上文關於導電特徵114所描述的類似材料及/或類似製程而形成。導電特徵124及導電特徵114的材料可相同或可不相同。舉例而言，在實施例中，導電特徵124可包括銅，而導電特徵114可包括鋁。導電特徵124可用作RDL以允許隨後形成的外部連接件(例如，連接件130，參見圖7)置於半導體晶粒100上方的任何所要位置中，而非將外部連接件的位置限制於直接在導電特徵114上方的區域。
如藉由圖6進一步說明，額外聚合物層126可形成在聚合物層120及導電特徵124上方以保護各種位於底下的特征。聚 合物層126可使用如上文關於聚合物層120所描述的類似材料及/或類似製程而形成。聚合物層126可具有例如約4μm至約7μm的厚度T3，但其他實施例可包含具有不同厚度的聚合物層。
在一些實施例中，聚合物層126可側向延伸經過聚合物層120的邊緣120'。舉例而言，聚合物層126可延伸超出功能電路區域100A的邊緣達側向尺寸W8。在聚合物層120的側向尺寸W6為約3.24μm至約5.86μm的實施例中，側向尺寸W8可為約9μm。聚合物層126的邊緣126'並不與聚合物層120的邊緣120'對準。藉由將聚合物層120與聚合物層126的邊緣組態為未對準，可實現各種優點，諸如改良製程控制、較容易的缺陷識別以及其類似者。在其他實施例中，聚合物層120與聚合物層126的各別邊緣120'與邊緣126'實質上可經對準。
在圖7中，聚合物層126可使用任何合適的製程經圖案化以曝露導電特徵124。舉例而言，在實施例中，聚合物層126包括感光性材料且使用如上文所描述的微影製程經圖案化。在圖案化之後，聚合物層126可如上文所描述經固化以硬化聚合物層126。亦可使用圖案化聚合物層126的其他合適的方法(例如，蝕刻)。
接下來在圖8中，凸塊下金屬化物(UBM)128及外部連接件130形成於晶粒100上方。UBM 128可與底下導電特徵124電接觸地形成。UBM 128可例如包括三個導電材料層，諸如鈦層、銅層以及鎳層。然而，材料及層的其他配置(諸如，鉻/鉻-銅合金/銅/金的配置；鈦/鈦鎢/銅的配置；銅/鎳/金的配置或其類似者)亦適合於形成UBM 128。
可藉由在聚合物層126上方且沿著穿過聚合物層126的開口的內部形成每一層而產生UBM 128。可使用電鍍製程(諸如，電化學電鍍)執行每一層的形成，但可取決於所要材料而替代地使用其他形成製程(諸如，濺鍍、蒸鍍或PECVD製程)。一旦已形成所要的層，便可接著經由合適的微影遮蔽製程及蝕刻製程移除層的部分以移除非所要材料，且保留呈諸如圓形、八邊形、正方形或矩形形狀的所要形狀的UBM 128，但可替代地形成任何所要形狀。
外部連接件130可為接觸凸塊且可包括諸如錫的材料或其他合適的材料，諸如銀、無鉛錫或銅。在連接件130為錫焊料凸塊的實施例中，可藉由最初經由合適的方法(諸如，蒸鍍、電鍍、印刷、焊料轉移、植球以及其類似者)形成錫層而形成連接件130。一旦錫層已形成於結構上，便可執行回焊以便將材料塑形成所要凸塊形狀。外部連接件130可用於將封裝200電性連接至另一封裝組件，諸如另一裝置晶粒、插入件、封裝基底、印刷電路板、主機板以及其類似者。另外，一或多個其他特徵(例如，SMT，未說明)亦可安裝在封裝200上。在安裝期間，由於封環110延伸至緩衝區100B中及聚合物層120的組態(例如，具有直接在封環110上方的邊緣)，對於封裝200的應力可降低。
圖9說明根據一些實施例的用於形成裝置封裝的製程流程300。在步驟302中，提供裝置晶粒(例如，晶粒100)，所述裝置晶粒可包含功能電路區域(例如，區域100A)及圍繞所述功能電路區域的封環(例如，封環110)。封環可藉由緩衝區(例如，緩衝區域100B)與功能電路區域間隔開。在步驟304中，導電特 徵形成於裝置晶粒中的鈍化層上方。導電特徵可包含側向延伸至緩衝區中的封環部分(例如，部分110')。在步驟306中，聚合物層(例如，聚合物層120)形成於導電特徵上方。聚合物層的邊緣(例如，邊緣120')可直接設置在封環上方，且聚合物層可側向延伸經過裝置晶粒的功能電路區域的邊緣。在步驟308中，額外封裝特徵(諸如，額外聚合物層、導電特徵、UBM、外部連接件以及其類似者)可形成在聚合物層上方。
實施例包含具有裝置晶粒及圍繞裝置晶粒的功能電路區域的封環的半導體裝置封裝。緩衝區可形成在封環與裝置晶粒的功能電路區域之間。可採用緩衝區以便防止(或至少減小)對裝置晶粒的電路區域內的功能組件的損壞。在各種實施例中，設置於晶粒的鈍化層上方的封環的至少一部分可進一步側向延伸至緩衝區中，且形成於封環上方的聚合物層的邊緣可在緩衝區中直接設置在封環上方。因此，封環可被用作聚合物層的著陸墊，封環有利地吸收在後續製造製程期間所得封裝中的應力且減少製造缺陷(例如，分層)。
根據實施例，半導體裝置包含半導體基底及位於半導體基底上方的內連線結構。內連線結構包含功能電路區域及藉由緩衝區與所述功能電路區域間隔開的封環的第一部分。所述半導體裝置亦包含內連線結構上方的鈍化層及在所述鈍化層上方且連接封環的第一部分的封環的第二部分。封環的第二部分設置於緩衝區中。
根據本發明時實施例，更包括位於所述鈍化層上方的聚合物層，其中所述聚合物層的邊緣直接設置在所述緩衝區中的所 述封環的所述第二部分上方。
根據本發明時實施例，更包括位於所述聚合物層上方的額外聚合物層，其中所述額外聚合物層側向延伸經過所述聚合物層的邊緣。
根據本發明時實施例，所述功能電路區域包括電連接至在所述半導體基底的頂部表面處的主動元件的第一導電特徵，其中所述半導體裝置進一步包括直接在所述功能電路區域上方且電連接至所述第一導電特徵的第二導電特徵，且其中所述第二導電特徵實質上與所述封環的所述第二部分齊平。
根據本發明時實施例，更包括藉由所述緩衝區與所述功能電路區域間隔開的所述封環的第三部分，其中所述封環的所述第三部分將所述封環的所述第二部分連接至所述封環的所述第一部分，且其中所述封環的所述第三部分的頂部表面與所述封環的所述第二部分實質上齊平。
根據本發明時實施例，所述封環的所述第二部分的側向尺寸至少約為所述封環的所述第三部分的側向尺寸的10%。
根據本發明時實施例，所述封環的所述第二部分的側向尺寸為約1μm或大於1μm。
根據本發明時實施例，所述封環圍繞所述功能電路區域，且其中所述封環與在所述半導體基底的頂部表面處的主動元件電性隔離。
根據另一實施例，半導體裝置包含基底；內連線結構，其包含電連接至形成在基底的頂部表面處的主動元件的第一導電特徵及內連線結構上方的第一鈍化層。此半導體裝置進一步包含封 環，其具有內連線結構中的第一部分及連接至第一部分且在第一鈍化層上方延伸的第二部分。所述第一部分圍繞第一導電特徵且藉由緩衝區與第一導電特徵間隔開，且所述第二部分延伸至緩衝區中。半導體裝置亦包含在第一鈍化層上方且電連接至第一導電特徵的第二導電特徵。第二導電特徵的頂部表面與封環的第二部分實質上齊平。半導體裝置亦包含封環及第二導電特徵上方的第一聚合物層。第一聚合物層的側壁直接設置在緩衝區中的封環的第二部分上方。
根據本發明時實施例，所述封環的所述第二部分圍繞所述第二導電特徵。
根據本發明時實施例，更包括在所述封環的所述第二部分及所述第二導電特徵的側壁上方且沿著其延伸的第二鈍化層，其中所述第二鈍化層設置在所述第一聚合物層下方。
根據本發明時實施例，更包括第二聚合物層，其在所述第一聚合物層上方；第三導電特徵，其在所述第二聚合物層上方且電連接至所述第二導電特徵；凸塊下金屬化物(UBM)，其在所述第三導電特徵上方且電連接至所述第三導電特徵；以及外部連接件，其在所述UBM上方且電連接至所述UBM。
根據本發明時實施例，所述第二聚合物層延伸經過所述第一聚合物層的所述側壁。
根據本發明時實施例，所述封環的所述第二部分的第一側壁直接設置在所述封環的所述第一部分上方，且其中所述封環的所述第二部分的第二側壁設置於所述緩衝區中。
根據本發明時實施例，所述封環延伸穿過所述內連線結 構。
根據又一實施例，方法包含環繞裝置晶粒的內連線結構中的第一導電特徵形成封環的第一部分；將第一鈍化層沈積於內連線結構上方；形成在第一鈍化層上方且電連接至第一導電特徵中的至少一者的第二導電特徵；以及在第一鈍化層上方形成封環的第二部分。封環的第一部分藉由緩衝區與第一導電特徵分離，且封環的第二部分電連接至封環的第一部分且延伸至緩衝區中。方法亦包含沈積在第二導電特徵及封環的第二部分的側壁上方且沿著第二導電特徵及封環的第二部分的側壁延伸的第二鈍化層；以及將第一聚合物層沈積於第二鈍化層上方。第一聚合物層延伸至緩衝區中且包含直接設置在封環的第二部分上方的側壁。
根據本發明時實施例，更包括在沈積所述第一聚合物層之後，固化所述第一聚合物層。
根據本發明時實施例，更包括圖案化所述第二鈍化層中的第一開口；圖案化連接至所述第一開口的所述第一聚合物層中的第二開口，其中所述第一開口及所述第二開口曝露所述第二導電特徵；形成第三導電特徵，其在所述第一聚合物層上方且延伸穿過所述第一開口及所述第二開口；以及將第二聚合物層沈積於所述第三導電特徵上方。
根據本發明時實施例，沈積所述第二聚合物層包括沈積所述第二聚合物層以側向延伸經過所述第一聚合物層。
根據本發明時實施例，形成所述封環的所述第二部分包括在形成所述第二導電特徵同時使用與形成所述第二導電特徵相同的製程。
前文概述若干實施例的特徵，以使得熟習此項技術者可較好地理解本發明的態樣。熟習此項技術者應理解，他們可易於使用本發明作為設計或修改其他製程及結構的基礎以實現本文中所引入的實施例的相同目的及/或達成相同優點。熟習此項技術者亦應認識到，此類等效構造並不脫離本發明的精神以及範疇，且其可在不脫離本發明的精神以及範疇的情況下在本文中進行各種改變、替代以及更改。
100‧‧‧裝置晶粒/晶粒
100A‧‧‧功能電路區域
100B‧‧‧緩衝區/緩衝區域
102‧‧‧基底/底下基底
104‧‧‧主動元件
104'‧‧‧源極/汲極區域
106‧‧‧內連線結構/上覆內連線結構
108‧‧‧導電特徵
110‧‧‧封環
112‧‧‧鈍化層
W1‧‧‧側向尺寸
W2‧‧‧側向尺寸

Claims (10)

  1. 一種半導體裝置，包括：半導體基底；內連線結構，位在所述半導體基底上方，其中所述內連線結構包括：功能電路區域；以及封環的第一部分，其藉由緩衝區與所述功能電路區域間隔開，其中由所述半導體裝置的上方往下方俯視時，所述封環的所述第一部分連續地圍繞所述功能電路區域，其中所述封環與在所述半導體基底的頂部表面處的主動元件電性隔離；鈍化層，其在所述內連線結構上方；以及所述封環的第二部分，位在所述鈍化層上方且連接所述封環的所述第一部分，其中所述封環的所述第二部分設置於所述緩衝區中。
  2. 如申請專利範圍第1項所述之半導體裝置，更包括位於所述鈍化層上方的聚合物層，其中所述聚合物層的邊緣直接設置在所述緩衝區中的所述封環的所述第二部分上方。
  3. 如申請專利範圍第2項所述之半導體裝置，更包括位於所述聚合物層上方的額外聚合物層，其中所述額外聚合物層側向延伸經過所述聚合物層的邊緣。
  4. 如申請專利範圍第1項所述之半導體裝置，更包括藉由所述緩衝區與所述功能電路區域間隔開的所述封環的第三部分，其中所述封環的所述第三部分將所述封環的所述第二部分連接至所述封環的所述第一部分，且其中所述封環的所述第三部分 的頂部表面與所述封環的所述第二部分實質上齊平。
  5. 一種半導體裝置，包括：基底；內連線結構，其包含第一導電特徵，所述第一導電特徵電性連接至形成在所述基底的頂部表面處的主動元件；第一鈍化層，位於所述內連線結構上方；封環，其包括：第一部分，位於所述內連線結構中，其中所述第一部分藉由緩衝區與所述第一導電特徵間隔開，且其中由所述半導體裝置的上方往下方俯視時，所述第一部分完全地圍繞第一導電特徵；第二部分，連接至所述第一部分且在延伸至所述第一鈍化層上方，其中所述第二部分延伸至緩衝區中，其中所述第二部分的第一側壁直接設置在所述封環的所述第一部分上方，且其中所述封環的所述第二部分的第二側壁設置於所述緩衝區中；第二導電特徵，位在所述第一鈍化層上方且電連接至所述第一導電特徵，其中所述第二導電特徵的頂部表面與所述封環的所述第二部分實質上齊平；第一聚合物層，位於所述第二導電特徵上方，其中所述第一聚合物層的側壁直接設置在所述緩衝區中的所述封環的所述第二部分上方。
  6. 如申請專利範圍第5項所述之半導體裝置，更包括在所述第二導電特徵及所述封環的所述第二部分的側壁上方且沿著其延伸的第二鈍化層，其中所述第二鈍化層設置在所述第一聚合物層下方。
  7. 一種半導體裝置，包括：內連線結構，包括：第一導電特徵，電性連接至形成在半導體基底的頂部表面處的主動元件；第二導電特徵，圍繞所述第一導電特徵且與所述半導體基底的所述頂部表面處的所述主動元件電性絕緣；鈍化層，位於所述內連線結構上方；第三導電特徵，位於且延伸通過所述內連線結構上方，其中垂直所述半導體基底的主要表面的第一線延伸通過所述第三導電特徵以及所述導電特徵，且其中垂直所述半導體基底的所述主要表面的第二線也延伸通過所述第三導電特徵且更延伸至所述第一導電特徵與所述第二導電特徵之間；第四導電特徵，位於與所述第三導電特徵同一層，其中所述第四導電特徵電性連接至所述第一導電特徵的其中一個或多個；以及第一聚合物層，位於所述鈍化層上方，其中所述第一聚合物層的側壁直接設置在所述第三導電特徵上方。
  8. 一種半導體裝置的製造方法，包括：在元件晶粒的內連線結構中形成位於第一導電特徵周圍的封環的第一部分，其中所述封環的所述第一部分藉由緩衝區與所述第一導電特徵間隔開；將第一鈍化層沈積於所述內連線結構上方；形成第二導電特徵，其位於所述第一鈍化層上方且電連接至所述第一導電特徵中的至少一者； 在所述第一鈍化層上方形成所述封環的第二部分，其中所述封環的所述第二部分延伸至緩衝區中；沈積位在所述第二導電特徵及所述封環的所述第二部分的側壁上方並延伸的第二鈍化層；以及將第一聚合物層沈積於所述第二鈍化層上方，其中所述第一聚合物層延伸至所述緩衝區中且包含直接設置在所述封環的所述第二部分上方的側壁。
  9. 如申請專利範圍第8項所述的方法，更包括：圖案化所述第二鈍化層中的第一開口；圖案化連接至所述第一開口的所述第一聚合物層中的第二開口，其中所述第一開口及所述第二開口曝露所述第二導電特徵；形成第三導電特徵，其在所述第一聚合物層上方且延伸穿過所述第一開口及所述第二開口；以及將第二聚合物層沈積於所述第三導電特徵上方。
  10. 如申請專利範圍第8項所述的方法，其中沈積所述第二聚合物層包括沈積所述第二聚合物層以側向延伸經過所述第一聚合物層。
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