CN106683999A - 形成金属栅极以缓解天线缺陷的方法 - Google Patents

形成金属栅极以缓解天线缺陷的方法 Download PDF

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CN106683999A
CN106683999A CN201610527074.XA CN201610527074A CN106683999A CN 106683999 A CN106683999 A CN 106683999A CN 201610527074 A CN201610527074 A CN 201610527074A CN 106683999 A CN106683999 A CN 106683999A
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Prior art keywords
groove
metal gates
layer
sidewall spacer
dielectric layer
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王祥保
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明涉及在衬底上方形成场效应晶体管(FET)的方法以及改进回蚀刻轮廓和防止金属栅极缺陷的相关的集成电路器件。在一些实施例中，穿过层间介电(ILD)层，沿着侧壁间隔件形成凹槽，并且由高k介电层和金属栅极填充该凹槽。实施回蚀刻以降低高k介电层和金属栅极，其中，高k介电材料和金属栅极材料的“天线”形状的残余物沿着侧壁间隔件留在高k层和金属栅极的边界区域处。然后，对侧壁间隔件实施第二蚀刻，去除侧壁间隔件的顶部边缘部分。然后，可以对高k介电层和金属栅极实施一个或多个蚀刻步骤以平坦化和去除残余物。本发明的实施例还涉及形成金属栅极以缓解天线缺陷的方法。

Description

形成金属栅极以缓解天线缺陷的方法
技术领域
本发明的实施例涉及集成电路器件，更具体地，涉及形成金属栅极以缓解天线缺陷的方法。
背景技术
在过去的几十年，半导体制造工业已经经历了指数增长。在半导体演进过程中，功能密度(即，单位芯片面积中的互连器件的数量)通常在增加，同时几何尺寸(即，可使用制造工艺创建的最小组件或线)减小。一个优势是采用由具有高介电常数(高k)的材料绝缘的金属栅极的诸如晶体管的半导体器件的发展。相对于由二氧化硅绝缘的传统的多晶硅栅极，这样的半导体器件具有改进的性能和减小的部件尺寸。
发明内容
本发明的实施例提供了一种在衬底上方形成场效应晶体管(FET)的方法，所述方法包括：穿过层间介电(ILD)层，沿着侧壁间隔件形成凹槽；形成高k介电层以覆盖所述凹槽的底面和侧壁表面；在所述凹槽的未被所述高k介电层占据的剩余部分内形成金属栅极；实施第一系列的一个或多个蚀刻以降低所述高k介电层和所述金属栅极，沿着所述侧壁间隔件留下所述高k介电层的残余物；实施第二蚀刻以形成所述侧壁间隔件的锥形上表面，所述侧壁间隔件的高度随着不断接近所述金属栅极而单调地减小；以及实施第三系列的一个或多个蚀刻以去除所述高k介电层的所述残余物和平坦化所述金属栅极。
本发明的另一实施例提供了一种形成集成电路(IC)的方法，包括：穿过衬底上方的层间介电(ILD)层，形成对应于n沟道场效应晶体管(n-FET)的第一金属栅极的第一凹槽和对应于p沟道场效应晶体管(p-FET)的第二金属栅极的第二凹槽，所述第一凹槽和所述第二凹槽形成在各自侧壁间隔件的相邻对之间；在所述第一凹槽和所述第二凹槽的底面上方以及沿着所述侧壁间隔件的内侧壁形成高k介电层；在所述第一凹槽和所述第二凹槽内分别地形成第一金属栅极和第二金属栅极；实施平坦化以使所述ILD层、所述侧壁间隔件、所述高k介电层以及所述第一金属栅极和所述第二金属栅极的上表面共面；实施溅射蚀刻以形成所述侧壁间隔件的锥形上表面；以及实施一系列蚀刻以减小所述高k介电层和所述金属栅极的高度。
本发明的另一实施例提供了一种FinFET器件，包括：鳍，设置在平坦的衬底上方；层间介电(ILD)层，设置在所述衬底上方，所述层间介电(ILD)层覆盖所述鳍并且包括设置在所述ILD层内的第一凹槽和第二凹槽；侧壁间隔件，沿着所述凹槽的侧壁设置；第一金属栅极和第二金属栅极，所述第一金属栅极设置在所述第一凹槽内，所述第二金属栅极设置在所述第二凹槽内，所述第一金属栅极和所述第二金属栅极围绕所述鳍的顶面和侧壁表面；高k介电层，设置在所述侧壁间隔件和所述金属栅极之间并且横跨所述金属栅极的底面延伸；以及其中，所述侧壁间隔件的锥形上表面高于所述高k介电层的上表面，并且所述侧壁间隔件的高度随着不断接近所述金属栅极而单调地减小。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1示出了包括finFET器件的集成电路的一些实施例的立体截面。
图2A示出了图1的集成电路的沿线A-A’的一些实施例的截面图。
图2B示出了图1的集成电路的沿线B-B’的一些实施例的截面图。
图2C示出了图1的集成电路的沿线C-C’的一些实施例的截面图。
图3示出了形成集成电路的方法的一些实施例的流程图。
图4至图15示出了显示形成集成电路的方法的一些实施例的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
高k介电材料的介电常数k高于二氧化硅的介电常数。高k电介质用于半导体制造工艺中，在半导体制造工艺中，高k电介质经常用于替代二氧化硅栅极电介质。例如，高k金属栅极(HKMG)技术采用高k栅极电介质上方的金属栅极(MG)并且提供相对于具有多晶硅栅极和/或二氧化硅栅极电介质的传统的晶体管的性能改进。尽管缩放持续减小HKMG电路的尺寸，但是纵横比的增加可以造成HKMG制造工艺的填充和回蚀刻问题。
更具体地，在用于形成HKMG结构的一些常规方法中，布置在侧壁间隔件之间的牺牲栅极形成在衬底上方，并且低k介电层(有时称为层间电介质(ILD)或金属间电介质(IMD))形成在牺牲栅极上方。在实施化学机械平坦化(CMP)操作以平坦化牺牲栅极和低k介电层的顶面之后，然后选择性地去除牺牲栅电极以在侧壁间隔件之间留下凹槽。然后，沿着凹槽的下表面和侧壁形成高k栅极电介质，并且在高k栅极电介质上方沉积金属以填充凹槽的剩余部分。然后，实施另一CMP操作以使金属、高k栅极电介质和低k电介质的上表面共面。然后，相对于低k介电层的顶面，选择性地回蚀刻或凹进金属的平坦化的上表面。不幸地，由于凹槽的开口尺寸较小，沿着凹槽的侧壁可能非故意地留下少量的金属和/或高k栅极电介质(“残余物”)。残余物可以说具有“天线”的形状，其中，更多的残余物可以积聚在凹槽的下拐角中并且可以以逐渐减小的方式向上延伸至凹槽的上部区域。然后，沉积硬掩模材料以填充凹槽的剩余部分，并且回化学机械平坦化(CMP)硬掩模材料以在凹槽中形成硬掩模，以及在硬掩模位于适当的位置时对结构实施额外的蚀刻。
由于天线形状的残余物向上延伸至位于硬掩模和侧壁间隔件之间的凹槽的上部区域，所以在实施CMP平坦化工艺以形成硬掩模之后，可以暴露于周围环境。当接触件或其他导电层形成在其上时，暴露的天线形状的残余物可以引起泄露或短路缺陷。另外，接着发生的湿洗或蚀刻工艺可以不期望地穿过天线形状的残余物向下扩散(即，围绕和位于硬掩模的外边缘下方)，最终损坏下面的金属栅极、高k电介质和/或其他层。例如，在一些情况下，接着发生的蚀刻可以部分地或完全地去除金属栅极和/或高k介电层和/或可以在结构上削弱产生出的结构；导致各种问题。
相应地，本发明涉及减少天线形状的残余物的技术，并且因此，改进了HKMG晶体管的可靠性。在一些实施例中，在形成任何天线形状的残余物之后，使用额外的处理步骤以去除天线形状的残余物。这些额外的工艺步骤可以改变金属栅极上方的侧壁轮廓，以使形成在金属栅极上方的硬掩模具有与侧壁间隔件直接接触的侧壁(即，没有任何天线形状的残余物介入在硬掩模和侧壁间隔件之间)。以这种方式，残余物减少并且金属栅极和高k层的更好的轮廓具有帮助防止栅极非故意地损坏和/或去除的侧壁轮廓，从而改进FET器件的产量和性能。尽管这些额外的工艺步骤可能增加了制造工艺的一些成本和复杂度，但是它们提供了改进的器件可靠性。
图1示出了包括具有一些FinFET设置在其上的集成电路100的集成电路的一些实施例的立体截面图。如将在本文中更详细的理解(例如，关于本文中进一步描述的后续的制造工艺)，通过限制天线形状缺陷的效应的制造工艺形成集成电路100，并且集成电路100具有可以证明这些改进的制造方法的结构特征。
集成电路100包括诸如硅鳍的半导体鳍103，其在衬底102上方沿着第一方向X延伸。如从截面线A-A’(图1和图2A)可见，沿着鳍103的长度设置第一和第二finFET101、105。如图2A所示，第一finFET101包括布置在鳍103中的第一沟道区域上方以及布置在第一和第二源极/漏极区域202a、202b之间的第一金属栅极132a。第二finFET105包括布置在鳍103中的第二沟道区域上方以及布置在第三和第四源极/漏极区域202c、202d之间的第二金属栅极132b。在一些实施例中，源极/漏极区域202a-202d包括在鳍103的上表面之上延伸的外延生长的SiGe或SiP区域。高k介电层106用作栅极电介质并且将金属栅极132与鳍103的沟道区域分隔开。可以沿着衬底102和鳍103上方的ILD层104的侧壁表面和底面设置蚀刻停止层114。如图2C所示，在器件操作期间，金属栅极132a“包裹”围绕鳍103的侧壁表面和顶面以在鳍103中提供合适的耗尽(例如，完全耗尽)。
在一些实施例中，第一金属栅极132a对应于n型finFET并且第二金属栅极132b对应于p型finFET。在一些实施例中，接触件142可以穿过ILD层104和蚀刻停止层114设置以到达源极/漏极区域202。此外，如图2B所示，第一金属栅极132a和第二金属栅极132b可以包括具有由阻挡层108覆盖的底面和侧壁表面的金属层110。金属栅极132可以进一步包括额外的金属层。例如，第二金属栅极132b可以进一步包括设置在阻挡层108和高k介电层106之间的功函金属层109，而第一金属栅极132a包括不同的功函金属层或缺少这样的功函金属层。
如图1所示，第一金属栅极132a设置在第一凹槽130a内，并且第二金属栅极132b设置在第二凹槽130b内。侧壁间隔件116沿着凹槽130的侧壁设置。在一些实施例中，介电层105可以设置在由鳍103分隔开的衬底上。在一些其他实施例中，介电层105或由其他材料制成的绝缘层可以设置在鳍103下面，从而将鳍103与衬底102分隔开。侧壁间隔件116可以坐落于介电层105上并且沿着鳍103的侧壁向上延伸。高k介电层106也可以设置在介电层105上并且沿着鳍103的侧壁向上延伸。侧壁间隔件116可以包括SiO2、SiN、SiC、SiCN、SiON、SiOCN或它们的组合。在一些实施例中，侧壁间隔件116具有锥形上表面。随着不断接近金属栅极132，侧壁间隔件116的高度单调地减小。侧壁间隔件116的高度可以大于高k介电层106的高度。侧壁间隔件116的锥形上表面可以横向地高于高k介电层106和金属栅极132的上表面。在一些实施例中，高k介电层106和金属栅极132的上表面共面。在一些实施例中，侧壁间隔件116的锥形上表面向下延伸至高k介电层106的上表面，而在一些可选实施例中，高k介电层106邻接侧壁间隔件116的竖直的内侧壁，而不是侧壁间隔件116的锥形的上表面。
如图2A至图2C所示，硬掩模150可以设置在金属栅极132a、132b上方，并且在132a、132b处直接横向地邻接凹槽的上部处的蚀刻停止层114。有利地，设置在本发明中的硬掩模150的上表面之下的侧壁间隔件116的锥形上表面可以证明对侧壁间隔件116和/或凹槽130a、130b实施额外的蚀刻处理以从凹槽130a、130b的侧壁去除天线形状的残余物的事实。此外，由于锥形允许硬掩模150直接邻接蚀刻停止层114(即，没有天线形状的残余物的部分在硬掩模150的外边缘和蚀刻停止层114之间向上延伸)，与之前的方法相比，图1和图2a至图2c所示的结构更不受硬掩模蚀刻的影响。因此，与之前的方法相比，图1的结构可以展示出改进的可靠性。
图3示出了根据一些实施例的形成集成电路的方法300的流程图。虽然本文将所公开的方法300示出和描述为一系列的步骤或事件，但是应当理解，所示出的这些步骤或事件的顺序不应解释为限制意义。例如，一些步骤可以以不同顺序发生和/或与除了本文所示和/或所述步骤或事件之外的其他步骤或事件同时发生。另外，并不要求所有示出的步骤都用来实施本文所描述的一个或多个方面或实施例。此外，可在一个或多个分离的步骤和/或阶段中执行本文所述步骤的一个或多个。
在步骤302中，在衬底上方形成牺牲多晶硅栅极。在多晶硅栅极旁边形成侧壁间隔件。
在步骤304中，层间介电(ILD)层形成在多晶硅栅极之间。然后，去除多晶硅栅极以穿过相邻的侧壁间隔件之间的ILD层形成凹槽。
在步骤306中，形成高k介电层以覆盖凹槽的底面和侧壁表面。在凹槽的未被高k介电层占据的剩余部分内形成金属栅极。
在步骤308中，实施第一系列蚀刻以降低高k介电层和金属栅极。沿着侧壁间隔件留下高k介电层的残余物。
在步骤310中，实施第二蚀刻以为侧壁间隔件形成锥形上表面。随着不断接近金属栅极，侧壁间隔件的高度单调地减小。
在步骤312中，实施第三系列蚀刻以去除高k介电层的残余物和平坦化金属栅极。
在步骤314中，在平坦化的金属栅极和高k介电层上形成硬掩模层。
在步骤316中，为金属栅极和源极/漏极区域形成接触件。
图4至图15示出了显示包括场效应晶体管(FET)的集成电路(IC)的方法的截面图的一些实施例。尽管描述图4至图15与方法300有关，但是应该理解，图4至图15公开的结构不限制于本方法，而是可以作为独立于本方法的结构单独存在。
图4示出了对应于步骤302的截面图400的一些实施例。如截面图400所示，在衬底402上方图案化牺牲多晶硅栅极420a、420b。在一些实施例中，在形成牺牲多晶硅栅极420a、420b之前，在衬底402的上表面上形成栅极氧化物层422。在图案化牺牲多晶硅栅极420a、420b之后，沿着牺牲多晶硅栅极420和栅极氧化物层422的侧壁形成侧壁间隔件416。可以通过在牺牲多晶硅栅极420上方沉积共形的间隔件层以及回蚀刻共形的间隔件层以沿着牺牲多晶硅栅极420和栅极氧化物层422的侧壁留下侧壁间隔件416来形成侧壁间隔件416。在形成侧壁间隔件之后，例如，可以通过离子注入或通过在衬底402中的牺牲栅极420的相对两侧上形成凹槽并且用应变诱导源极/漏极材料(例如，外延生长SiP或SiGe)填充凹槽来形成源极/漏极区域202。
在一些实施例中，衬底402可以是平坦的，具有均匀的厚度。此外，衬底402可以是n型或p型并且可以例如是块状Si晶圆或绝缘体上硅(SOI)衬底。如果存在，SOI衬底通常由布置在处理晶圆上方并且通过埋氧层与处理晶圆分隔开的高品质硅的有源层制成。在一些其他实施例中，半导体衬底也可以是蓝宝石衬底、二元化合物衬底(例如，III-V族衬底)或具有或不具有形成在半导体衬底上方的额外的绝缘层或导电层的其他更高阶化合物衬底(例如，AlGaAs)。在一些其他实施例中，衬底402可以是包括形成在平坦的衬底上方的凸起的鳍的有鳍的衬底。源极/漏极区域202和其间的沟道区域418形成在凸起的鳍内。侧壁间隔件416可以由诸如二氧化硅(SiO2)、氮化硅(SiN)、碳化硅(SiC)、碳氮化硅(SiCN)、氮氧化硅(SiON)、碳氮氧化硅(SiOCN)或它们的组合的介电材料形成。
图5示出了对应于步骤304的截面图500的一些实施例。如截面图500所示，层间介电(ILD)层404沉积在图4的结构上方，并且填充相邻数对侧壁间隔件的外边缘之间的间隙。然后，执行平坦化工艺，其后，去除牺牲多晶硅栅极(图4的420a、420b，可能与栅极氧化物422一起)以形成第一凹槽410a和第二凹槽410b，将侧壁间隔件416和ILD层404留在适当的位置。
在一些实施例中，ILD层404可以是具有约3.9的介电常数的二氧化硅(SiO2)层，而在一些其他实施例中，ILD层404可以是氮化硅或氮氧化硅。ILD层404还可以是具有小于3.9的介电常数的多孔或固体低k电介质。在一些实施例中，在形成ILD层404之前，形成围绕ILD层404的底面和侧壁表面的蚀刻停止层414。蚀刻停止层414可以包括碳化硅或氮化硅。
图6示出了对应于步骤306的截面图600的一些实施例。如截面图600中所示，形成高k介电层406以覆盖凹槽410的底面和侧壁表面。可以形成金属栅极532a、532b，其包括沿着高k介电层406形成的阻挡层408和形成在凹槽410的剩余的间隔件内的金属层510。在一些实施例中，第一金属栅极532a形成在第一凹槽410a内以用于n沟道场效应晶体管(n-FET)，并且第二金属栅极532b形成在第二凹槽410b内以用于p沟道场效应晶体管(p-FET)。在一些实施例中，功函金属层409形成在第二凹槽410b内而不形成介于阻挡层408和高k介电层406之间的第一凹槽410a内。在一些实施例中，金属层510包括钨(W)。功函金属层409可以包括钛(Ti)、铝(Al)或氮化钛(TiN)。然后，实施平坦化以使ILD层404、侧壁间隔件416、高k介电层406、阻挡层408和金属栅极532a、532b的上表面横向对准。在一些实施例中，平坦化可包括化学机械抛光(CMP)工艺。可以包括氧化材料和/或其他反应产物的残余薄膜602可能留在平坦化的顶面的顶部上。
图7至图9示出了对应于步骤308的截面图700、800和900的一些实施例，其中，实施第一蚀刻或第一系列蚀刻以减小高k介电层406和金属栅极532a、532b的高度。
如图7的截面图700中所示，实施金属突破蚀刻以去除残余薄膜602并且暴露出金属栅极532a、532b的上表面。
如图8的截面图800所示，功函金属蚀刻可以具有与金属突破蚀刻不同的蚀刻化学物或不同的蚀刻条件，实施功函金属蚀刻以回蚀刻高k介电层406的上部以及阻挡层408、功函金属层409和金属层510的上部。
如图9的截面图900所示，实施高k蚀刻以选择性地去除高k介电层406。在一些实施例中，高k蚀刻可以是具有与突破蚀刻700和/或功函金属蚀刻800相同或不同的蚀刻化学物和/或相同或不同的蚀刻条件的干蚀刻。高k蚀刻之后是含氯气的清洗工艺。可以施加一些高k蚀刻和清洗工艺循环，例如，5次或更多次以产生图9中所示的结构。作为实例，突破蚀刻700、功函金属蚀刻800以及高k蚀刻900可以降低高k介电层406和金属栅极532约50nm的高度h。可以蚀刻高k介电层406和金属栅极532以形成呈角度的上表面，但是沿着侧壁间隔件416留下残余物902(在某种程度上，可以称为天线形状的残余物)。残余物可以具有约11nm的高度d。
图10示出了对应于步骤310的截面图1000的一些实施例。如截面图1000所示，实施在某种程度上可以称为漏斗蚀刻的第二蚀刻以形成侧壁间隔件416的锥形上表面。随着不断接近金属栅极532，侧壁间隔件416的高度单调地减小。在一些实施例中，第二蚀刻包括物理蚀刻工艺，诸如凭借原子流、分子流或离子流指向结构并且来自原子、分子或离子的冲击力喷射结构的材料的溅射工艺。用这样的方法，可以将诸如氩(Ar)的具有较高的原子质量的原子用作能量粒子以去除侧壁间隔件416的顶部内边缘部分。作为实例，可以应用室压为约6毫托(mT)、流速为约200标准毫升/分钟(sccm)以及偏压为约200伏(V)的溅射蚀刻。在一些实施例中，离子流以非90度的入射角指向结构(例如，非法向入射角)。原子流、分子流或离子流的入射角可以对应于在侧壁间隔件(416a)的顶部边缘部与侧壁间隔件(416b)的基本上竖直的侧壁相接触处的角度。因此，凹槽的上部区域比凹槽的下部区域宽。
图11至图12示出了对应于步骤312的截面图1100、1200的一些实施例，实施第三系列蚀刻以去除高k介电材层406的残余物并且平坦化金属栅极532。
然后，如图11的截面图1100所示，实施高k蚀刻工艺以选择性地去除高k介电层406的部分。因此，去除和/或减少天线形状的高k残余物。由于侧壁间隔件416的锥形形状允许高k蚀刻更好地去除残余物，所以侧壁间隔件416的锥形形状有助于该工艺。
然后，如图12的截面图1200所示，选择性蚀刻金属栅极532，导致金属栅极结构具有与高k电介质、阻挡层和功函金属的上表面基本上相平的上表面。高k介电层406和金属栅极532可以具有约47nm的高度h’。如果有，在锥形侧壁间隔件416位于适当的位置时，可以去除剩余的金属残余物。在一些实施例中，高k介电层406和金属栅极532具有共面的顶面。在其他实施例中，与第三系列蚀刻之前的残余物的高度d相比，沿侧壁间隔件416留下少得多的尖端残余物，具有小于约6nm的高度d’。
图13示出了对应于步骤314的截面图1300的一些实施例。如截面图1300所示，硬掩模层150形成在平坦化的金属栅极532和高k介电层406上。硬掩模层150在侧壁间隔件416和ILD层404上方向上延伸,并且平坦化硬掩模层150以使ILD层404、侧壁间隔件416和硬掩模层150的顶面横向地对准。
图14至图15示出了对应于步骤316的截面图1400、1500的一些实施例。如截面图1400所示，第二ILD层1002形成在ILD层404、侧壁间隔件416和硬掩模层150上方。如截面图1500所示，为金属栅极532形成接触件1004并且为源极/漏极区域202形成接触件1006。穿过形成在ILD层404、侧壁间隔件416和硬掩模层150上方的第二ILD层1002形成接触件1004、1006。
应该理解，虽然在本文中通篇参考示例性的结构来论述本文所述的方法的多个方面，但那些方法并不受所述相应的结构限制。反之，方法(和结构)被视为彼此独立的且能够独立以及可以在不参考图中所描述的任何具体方面的情况下实现。另外，可以以诸如旋涂、溅射、生长和/或沉积技术等的任何适合的方式来形成本文所述的层。
同样地，基于阅读和/或理解说明书和附图，对于本领域技术人员而言可能发生等效地替换和/或修改。本文的公开内容包括这样的修改和替换并且因此通常不旨在限制。例如，虽然本文所提供的附图示出和描述出具有具体的掺杂物类型，但将理解到正如本领域普通技术人员所理解地，可以利用可选地掺杂物类型。
因此，本发明涉及一种结构和一种用于形成具有场效应器件的集成电路的方法。在初始回蚀刻金属栅极和周围的高k介电层之后，蚀刻沿着高k介电层设置的侧壁间隔件以形成锥形上表面。因此，纵横比减小并且通过接下来的蚀刻工艺可以更彻底地去除金属栅极和高k介电层的残余物。实现金属栅极和高k层的更佳的轮廓(意味着更平坦)以防止栅极缺失和提高场效应器件的产量和性能。
在一些实施例中，本发明涉及一种在衬底上方形成场效应晶体管(FET)的方法。该方法包括：穿过层间介电(ILD)层沿着侧壁间隔件形成凹槽并且形成高k介电层以覆盖凹槽的底面和侧壁表面。该方法还包括：在凹槽的未被高k介电层占据的剩余部分内形成金属栅极。该方法还包括：实施第一系列蚀刻以降低高k介电层和金属栅极，沿着侧壁间隔件留下高k介电层的残余物。该方法还包括：实施第二蚀刻以形成侧壁间隔件的锥形上表面，随着不断接近金属栅极，侧壁间隔件的高度单调地减小。该方法还包括：实施第三系列蚀刻以去除高K介电层的残余物并且平坦化金属栅极。
在上述方法中，其中，所述第二蚀刻包括物理蚀刻工艺。
在上述方法中，其中，所述第二蚀刻是使用氩(Ar)原子的溅射工艺。
在上述方法中，其中，所述金属栅极由钨(W)材料形成。
在上述方法中，其中，在实施所述第一系列的一个或多个蚀刻之前，所述ILD层、所述侧壁间隔件、所述高k介电层和所述金属栅极的上表面横向地对准。
在上述方法中，在所述第三系列的一个或多个蚀刻之后，还包括：在所述金属栅极和所述高k介电层上形成硬掩模层，所述硬掩模层在所述侧壁间隔件和所述ILD层上方向上延伸；以及实施平坦化，以使所述ILD层、所述侧壁间隔件和所述硬掩模层的顶面横向地对准。
在上述方法中，其中，所述衬底是平坦衬底，至少一个鳍设置在所述平坦衬底上方。
在另一个实施例中，本发明涉及一种形成集成电路(IC)的方法。该方法包括：穿过位于衬底上方的层间介电(ILD)层形成对应于n沟道场效应晶体管(n-FET)的第一金属栅极的第一凹槽和对应于p沟道场效应晶体管(p-FET)的第二金属栅极的第二凹槽，第一凹槽和第二凹槽沿着侧壁间隔件形成。该方法还包括：在第一凹槽和第二凹槽的底面上方和沿着侧壁间隔件形成高k介电层，并且在第一凹槽和第二凹槽内分别地形成第一金属栅极和第二金属栅极。该方法还包括：实施平坦化以使ILD层、侧壁间隔件、高k介电层以及第一和第二金属栅极的上表面共面。该方法还包括：实施溅射蚀刻以形成侧壁间隔件的锥形上表面。该方法还包括：实施一系列蚀刻以降低高K介电层和金属栅极。
在上述方法中，还包括：在分别位于所述高k介电层与所述第一金属栅极之间和位于所述高k介电层与所述第二金属栅极之间的所述第一凹槽和所述第二凹槽内形成阻挡层；以及在所述阻挡层和所述高k介电层之间的所述第二凹槽内而不在所述第一凹槽内形成功函金属层。
在上述方法中，还包括：在所述金属栅极和所述高k介电层上形成硬掩模层，其中，所述硬掩模层的上表面与所述ILD层的上表面共面。
在上述方法中，其中，形成的所述高k介电层的底面与所述侧壁间隔件的底面对准。
在上述方法中，其中，所述金属栅极包括钨(W)。
在上述方法中，其中，所述衬底包括至少一个半导体鳍，并且所述第一金属栅极和所述第二金属栅极形成为围绕所述鳍的顶面和侧壁表面。
在又另一的实施例中，本发明涉及FinFET器件。FinFET器件包括设置在平坦的衬底上方的鳍和设置在衬底上方的层间介电(ILD)层，ILD层覆盖鳍，包括设置在ILD层内的第一凹槽和第二凹槽。FinFET器件还包括：沿凹槽的侧壁设置的侧壁间隔件。FinFET器件还包括：设置在第一凹槽内的第一金属栅极和设置第二凹槽内的第二金属栅极，第一金属栅极和第二金属栅极围绕鳍的顶面和侧壁表面。FinFET器件还包括：高k介电层，设置在侧壁间隔件和金属栅极之间并且横跨金属栅极的底面延伸。侧壁间隔件的锥形上表面高于高k介电层的上表面，并且侧壁间隔件的高度随着不断接近金属栅极而单调地减小。
在上述FinFET器件中，其中，所述侧壁间隔件和所述高k介电层具有竖直对准的底面。
在上述FinFET器件中，进一步包括：外延源极/漏极区域，设置在位于所述第一凹槽和所述第二凹槽旁边的所述鳍内。
在上述FinFET器件中，进一步包括：阻挡层，设置在所述第一凹槽和所述第二凹槽内，所述第一凹槽和所述第二凹槽分别位于所述高k介电层与所述第一金属栅极之间和位于所述高k介电层与所述第二金属栅极之间；以及功函金属层，设置在所述阻挡层和所述高k介电层之间的所述第二凹槽内而不在所述第一凹槽内。
在上述FinFET器件中，进一步包括：蚀刻停止层，围绕所述ILD层的底面和侧壁表面。
在上述FinFET器件中，进一步包括：绝缘层，将所述平坦的衬底和所述鳍分隔开。
在上述FinFET器件中，其中，所述侧壁间隔件包括SiO2、SiN、SiC、SiCN、SiON、SiOCN或它们的组合。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种在衬底上方形成场效应晶体管(FET)的方法，所述方法包括：
穿过层间介电(ILD)层，沿着侧壁间隔件形成凹槽；
形成高k介电层以覆盖所述凹槽的底面和侧壁表面；
在所述凹槽的未被所述高k介电层占据的剩余部分内形成金属栅极；
实施第一系列的一个或多个蚀刻以降低所述高k介电层和所述金属栅极，沿着所述侧壁间隔件留下所述高k介电层的残余物；
实施第二蚀刻以形成所述侧壁间隔件的锥形上表面，所述侧壁间隔件的高度随着不断接近所述金属栅极而单调地减小；以及
实施第三系列的一个或多个蚀刻以去除所述高k介电层的所述残余物和平坦化所述金属栅极。
2.根据权利要求1所述的方法，其中，所述第二蚀刻包括物理蚀刻工艺。
3.根据权利要求1所述的方法，其中，所述第二蚀刻是使用氩(Ar)原子的溅射工艺。
4.根据权利要求1所述的方法，其中，所述金属栅极由钨(W)材料形成。
5.根据权利要求1所述的方法，其中，在实施所述第一系列的一个或多个蚀刻之前，所述ILD层、所述侧壁间隔件、所述高k介电层和所述金属栅极的上表面横向地对准。
6.根据权利要求1所述的方法，在所述第三系列的一个或多个蚀刻之后，还包括：
在所述金属栅极和所述高k介电层上形成硬掩模层，所述硬掩模层在所述侧壁间隔件和所述ILD层上方向上延伸；以及
实施平坦化，以使所述ILD层、所述侧壁间隔件和所述硬掩模层的顶面横向地对准。
7.根据权利要求1所述的方法，
其中，所述衬底是平坦衬底，至少一个鳍设置在所述平坦衬底上方。
8.一种形成集成电路(IC)的方法，包括：
穿过衬底上方的层间介电(ILD)层，形成对应于n沟道场效应晶体管(n-FET)的第一金属栅极的第一凹槽和对应于p沟道场效应晶体管(p-FET)的第二金属栅极的第二凹槽，所述第一凹槽和所述第二凹槽形成在各自侧壁间隔件的相邻对之间；
在所述第一凹槽和所述第二凹槽的底面上方以及沿着所述侧壁间隔件的内侧壁形成高k介电层；
在所述第一凹槽和所述第二凹槽内分别地形成第一金属栅极和第二金属栅极；
实施平坦化以使所述ILD层、所述侧壁间隔件、所述高k介电层以及所述第一金属栅极和所述第二金属栅极的上表面共面；
实施溅射蚀刻以形成所述侧壁间隔件的锥形上表面；以及
实施一系列蚀刻以减小所述高k介电层和所述金属栅极的高度。
9.根据权利要求8所述的方法，还包括：
在分别位于所述高k介电层与所述第一金属栅极之间和位于所述高k介电层与所述第二金属栅极之间的所述第一凹槽和所述第二凹槽内形成阻挡层；以及
在所述阻挡层和所述高k介电层之间的所述第二凹槽内而不在所述第一凹槽内形成功函金属层。
10.一种FinFET器件，包括：
鳍，设置在平坦的衬底上方；
层间介电(ILD)层，设置在所述衬底上方，所述层间介电(ILD)层覆盖所述鳍并且包括设置在所述ILD层内的第一凹槽和第二凹槽；
侧壁间隔件，沿着所述凹槽的侧壁设置；
第一金属栅极和第二金属栅极，所述第一金属栅极设置在所述第一凹槽内，所述第二金属栅极设置在所述第二凹槽内，所述第一金属栅极和所述第二金属栅极围绕所述鳍的顶面和侧壁表面；
高k介电层，设置在所述侧壁间隔件和所述金属栅极之间并且横跨所述金属栅极的底面延伸；以及
其中，所述侧壁间隔件的锥形上表面高于所述高k介电层的上表面，并且所述侧壁间隔件的高度随着不断接近所述金属栅极而单调地减小。
CN201610527074.XA 2015-07-28 2016-07-05 形成金属栅极以缓解天线缺陷的方法 Pending CN106683999A (zh)

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