CN106653676A - 衬底结构、半导体器件以及制造方法 - Google Patents
衬底结构、半导体器件以及制造方法 Download PDFInfo
- Publication number
- CN106653676A CN106653676A CN201510735985.7A CN201510735985A CN106653676A CN 106653676 A CN106653676 A CN 106653676A CN 201510735985 A CN201510735985 A CN 201510735985A CN 106653676 A CN106653676 A CN 106653676A
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon
- insulator layer
- semiconductor layer
- substrat structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Abstract
Description
Claims (17)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510735985.7A CN106653676B (zh) | 2015-11-03 | 2015-11-03 | 衬底结构、半导体器件以及制造方法 |
US15/279,236 US10262891B2 (en) | 2015-11-03 | 2016-09-28 | Substrate having two semiconductor materials on insulator |
EP16196135.4A EP3166131A1 (en) | 2015-11-03 | 2016-10-27 | A substrate having two semiconductor materials on insulator and its process of fabrication |
US16/282,126 US11011410B2 (en) | 2015-11-03 | 2019-02-21 | Substrate having two semiconductor materials on insulator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510735985.7A CN106653676B (zh) | 2015-11-03 | 2015-11-03 | 衬底结构、半导体器件以及制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106653676A true CN106653676A (zh) | 2017-05-10 |
CN106653676B CN106653676B (zh) | 2019-12-24 |
Family
ID=57209300
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510735985.7A Active CN106653676B (zh) | 2015-11-03 | 2015-11-03 | 衬底结构、半导体器件以及制造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US10262891B2 (zh) |
EP (1) | EP3166131A1 (zh) |
CN (1) | CN106653676B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111679454A (zh) * | 2020-06-19 | 2020-09-18 | 联合微电子中心有限责任公司 | 半导体器件的制备方法 |
CN111785729A (zh) * | 2020-06-11 | 2020-10-16 | 长江存储科技有限责任公司 | 一种三维存储器的制作方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11502106B2 (en) * | 2020-02-11 | 2022-11-15 | Globalfoundries U.S. Inc. | Multi-layered substrates of semiconductor devices |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101401199A (zh) * | 2006-02-27 | 2009-04-01 | 特拉希特技术公司 | 含有连接表面层和衬底区域的部分soi结构制造方法 |
CN101641774A (zh) * | 2007-03-28 | 2010-02-03 | 硅绝缘体技术有限公司 | 用于制造复合衬底的工艺 |
US20110163410A1 (en) * | 2007-06-06 | 2011-07-07 | S.O.I.Tec Silicon On Insulator Technologies | Method for producing hybrid components |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5272104A (en) * | 1993-03-11 | 1993-12-21 | Harris Corporation | Bonded wafer process incorporating diamond insulator |
US6380108B1 (en) * | 1999-12-21 | 2002-04-30 | North Carolina State University | Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby |
EP1647046A2 (en) * | 2003-07-23 | 2006-04-19 | ASM America, Inc. | DEPOSITION OF SiGE ON SILICON-ON-INSULATOR STRUCTURES AND BULK SUBSTRATES |
US7422956B2 (en) * | 2004-12-08 | 2008-09-09 | Advanced Micro Devices, Inc. | Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers |
US7282425B2 (en) | 2005-01-31 | 2007-10-16 | International Business Machines Corporation | Structure and method of integrating compound and elemental semiconductors for high-performance CMOS |
US7399686B2 (en) * | 2005-09-01 | 2008-07-15 | International Business Machines Corporation | Method and apparatus for making coplanar dielectrically-isolated regions of different semiconductor materials on a substrate |
US7531392B2 (en) * | 2006-02-27 | 2009-05-12 | International Business Machines Corporation | Multi-orientation semiconductor-on-insulator (SOI) substrate, and method of fabricating same |
US7595232B2 (en) * | 2006-09-07 | 2009-09-29 | International Business Machines Corporation | CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors |
US8587063B2 (en) * | 2009-11-06 | 2013-11-19 | International Business Machines Corporation | Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels |
US8853060B1 (en) * | 2013-05-27 | 2014-10-07 | United Microelectronics Corp. | Epitaxial process |
-
2015
- 2015-11-03 CN CN201510735985.7A patent/CN106653676B/zh active Active
-
2016
- 2016-09-28 US US15/279,236 patent/US10262891B2/en active Active
- 2016-10-27 EP EP16196135.4A patent/EP3166131A1/en not_active Withdrawn
-
2019
- 2019-02-21 US US16/282,126 patent/US11011410B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101401199A (zh) * | 2006-02-27 | 2009-04-01 | 特拉希特技术公司 | 含有连接表面层和衬底区域的部分soi结构制造方法 |
CN101641774A (zh) * | 2007-03-28 | 2010-02-03 | 硅绝缘体技术有限公司 | 用于制造复合衬底的工艺 |
US20110163410A1 (en) * | 2007-06-06 | 2011-07-07 | S.O.I.Tec Silicon On Insulator Technologies | Method for producing hybrid components |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111785729A (zh) * | 2020-06-11 | 2020-10-16 | 长江存储科技有限责任公司 | 一种三维存储器的制作方法 |
CN111785729B (zh) * | 2020-06-11 | 2021-10-26 | 长江存储科技有限责任公司 | 一种三维存储器的制作方法 |
CN111679454A (zh) * | 2020-06-19 | 2020-09-18 | 联合微电子中心有限责任公司 | 半导体器件的制备方法 |
CN111679454B (zh) * | 2020-06-19 | 2023-07-07 | 联合微电子中心有限责任公司 | 半导体器件的制备方法 |
Also Published As
Publication number | Publication date |
---|---|
CN106653676B (zh) | 2019-12-24 |
US20170125287A1 (en) | 2017-05-04 |
EP3166131A1 (en) | 2017-05-10 |
US10262891B2 (en) | 2019-04-16 |
US11011410B2 (en) | 2021-05-18 |
US20190244854A1 (en) | 2019-08-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI402943B (zh) | 具有不同表面方向之絕緣體上半導體主動層 | |
US20190259834A1 (en) | Iii-v semiconductor devices with selective oxidation | |
CN110400774A (zh) | 用于形成薄的绝缘体上半导体soi衬底的方法 | |
US9515089B1 (en) | Bulk fin formation with vertical fin sidewall profile | |
WO2012155830A1 (zh) | 锗和iii-v混合共平面的绝缘体上硅(s0i)半导体结构及其制备方法 | |
CN102790054A (zh) | 锗和iii-v混合共平面的半导体结构及其制备方法 | |
US20140159123A1 (en) | Etch resistant raised isolation for semiconductor devices | |
CN106653676A (zh) | 衬底结构、半导体器件以及制造方法 | |
US10290503B2 (en) | Spacer enabled poly gate | |
CN109817514A (zh) | 绝缘层上半导体基板与其形成方法 | |
JP6031253B2 (ja) | ハイブリッドmosfetデバイスの製造方法およびそれにより得られるハイブリッドmosfet | |
US8859388B2 (en) | Sealed shallow trench isolation region | |
JP3993820B2 (ja) | 半導体素子の素子分離膜の形成方法 | |
CN108091611A (zh) | 半导体装置及其制造方法 | |
CN100449785C (zh) | 半导体装置及半导体装置的制造方法 | |
JP2003168789A (ja) | Soiウェーハの製造方法 | |
US20120132923A1 (en) | Substrate for integrated circuit and method for forming the same | |
TW201428829A (zh) | 半導體裝置之製造方法 | |
TW201816847A (zh) | 用於nfet和pfet裝置的間隙壁整合方案 | |
CN106558495B (zh) | 鳍式场效应晶体管及其形成方法 | |
JP2005322830A (ja) | 半導体装置の製造方法 | |
US9564326B2 (en) | Lithography using interface reaction | |
CN111354675A (zh) | 浅沟槽隔离结构的形成方法及浅沟槽隔离结构 | |
CN109103255A (zh) | 半导体装置 | |
KR102546554B1 (ko) | 멀티 soi 기판 제조 방법 및 멀티 soi 기판 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20180523 Address after: No. 18 Zhangjiang Road, Pudong New Area, Shanghai Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Core integrated circuit (Ningbo) Co., Ltd. Address before: 100176 18 Wenchang Avenue, Daxing District economic and Technological Development Zone, Beijing Applicant before: Semiconductor Manufacturing International (Beijing) Corporation Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
GR01 | Patent grant | ||
GR01 | Patent grant |