CN106653624B - 一种稳固芯片的封装工艺 - Google Patents

一种稳固芯片的封装工艺 Download PDF

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CN106653624B
CN106653624B CN201710062945.XA CN201710062945A CN106653624B CN 106653624 B CN106653624 B CN 106653624B CN 201710062945 A CN201710062945 A CN 201710062945A CN 106653624 B CN106653624 B CN 106653624B
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chip
layers
die bond
welding section
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CN106653624A (zh
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何忠亮
郭秋卫
汪元元
朱争鸣
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Shenzhen Dinghua Xintai Technology Co.,Ltd.
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Led Device Packages (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明提出了一种稳固芯片的封装工艺,优势在于,适用于存在孤岛电极的设计,可显著增加集成电路封装I/O数。另外,固定芯片的平台边角区域铜层表面有机金属转化膜与封装树脂紧密结合,保证了芯片封装稳固,有利于提升后期测试良率和使用寿命。

Description

一种稳固芯片的封装工艺
技术领域
本发明涉及一种稳固芯片的封装工艺,本发明属于电子技术领域。
背景技术
方形扁平无引脚封装(Quad Flat NO-lead Package,QFN)技术是一种重要的集成电路封装工艺,传统QFN利用铜板正反面不同图案腐蚀得到引脚框架结构,制作过程需要塑封贴膜,且难以设计孤岛电极,I/O数受限制较多。另外,封装后使用过程中受应力作用往往出现芯片连接不牢的现象。
发明内容
针对现有技术的不足,本发明提出了一种稳固芯片的封装工艺,其特征在于:工艺过程包括:(1)在导电基板上涂覆感光材料;(2)感光材料图形转移,使得芯片固定平台和引脚邦线区的线路槽露出;(3)在图形化区基板露出部分镀底电极;(4)在底电极上继续镀铜层;(5)再次涂覆感光材料,并通过图形转移只露出引脚邦线区和芯片固定平台的固晶焊接区铜层,而芯片固定平台上固晶焊接区四周边缘的铜层仍被感光材料覆盖;(6)在引脚邦线区和固晶焊接区的铜层上镀顶电极;(7)去除剩余感光材料;(8)在铜层侧面以及芯片焊接平台上固晶焊接区四周的铜层顶面修饰有机金属转化膜;(9)将芯片焊接在固晶焊接区,并将引脚邦定在引脚邦线区的顶电极上;(10)灌注封装树脂材料,树脂固化成型后去除基板,露出底电极,完成封装。
所述感光材料优选聚丙烯酸酯类的干膜、湿膜。
所述底电极为标准电极电势高于铜的金属材料,优选金、银、钯或其合金,顶电极为标准电极电势高于铜且易于焊接的金属,优选金、银、钯或其合金。
所述芯片固定平台包括中间的固晶焊接区和固晶焊接区四周的区域,固晶焊接区镀有顶电极并与芯片焊接,固晶焊接区四周区域的铜层上没有顶电极。
铜层侧面以及芯片固定平台上固晶焊接区四周的铜层顶面修饰的有机金属转化膜优选采用棕氧化或黑氧化工艺在铜的表面反应来获取。
所述封装树脂材料优选环氧树脂。
所述导电基板为金属基板或镀有导电金属层的刚性基板,树脂固化成型后采用物理剥离或化学蚀刻的方式去除导电基板。
本发明的优势在于,适用于存在孤岛电极的设计,可显著增加集成电路封装I/O数。另外,固定芯片的平台边角区域铜层表面有机金属转化膜与封装树脂紧密结合,保证了芯片封装稳固,有利于提升后期测试良率和使用寿命。
附图说明
图1采用本发明封装结构示意图。1-底电极;2-铜层;3-铜层表面有机金属转化膜;4-顶电极;5-封装树脂;6-芯片;7-邦线。
图2采用本发明工艺流程图。a-导电基板涂覆感光材料;b-在图形化获得线路槽;c-镀底电极;d-镀铜层;e-再次涂覆感光材料;f-引脚邦线区和芯片固定平台上的固晶焊接区铜层,而芯片固定平台上固晶焊接区四周的铜层仍被感光材料覆盖;g-镀顶电极;f-去除剩余感光材料;g-在铜层侧面以及芯片固定平台上的固晶焊接区的铜层顶面修饰有机金属转化膜;h-固定芯片和邦线;i-灌注封装树脂;j-剥离导电基板。
具体实施方式
实施例1:
在铜基板上涂覆聚丙烯酸酯干膜,通过曝光图形转移,使得芯片固定区和引脚邦线区的线路槽露出;在图形化区铜基板露出部分镀3μm银作为底电极,在银底电极上继续镀40μm铜层;再次涂覆感光材料,并通过图形转移只露出引脚邦线区和芯片固定平台上的固晶焊接区的铜层,而芯片固定平台上固晶焊接区四周的铜层仍被感光材料覆盖;在引脚邦线区和固晶焊接区的铜层上镀3μm银作为顶电极,去除剩余聚丙烯酸酯干膜,将全部材料浸入硫酸-过氧化氢棕氧化溶液中使得铜表面生成有机金属转化膜;将芯片焊接在固晶焊接区,并将引脚邦定在引脚邦线区的顶电极上;灌注封装环氧树脂材料,树脂固化成型后将铜基板完全腐蚀掉,得到如图1所示的封装结构,完成封装。工艺流程如图2所示。
实施例2:
在铝基板上涂覆聚丙烯酸酯干膜,通过曝光图形转移,使得芯片固定区和引脚邦线区的线路槽露出;在图形化区铝基板露出部分镀2μm金作为底电极,在银底电极上继续镀45μm铜层;再次涂覆感光材料,并通过图形转移只露出引脚邦线区和芯片固定平台上的固晶焊接区的铜层,而芯片固定平台上固晶焊接区四周的铜层仍被感光材料覆盖;在引脚邦线区和固晶焊接区的铜层上镀2μm钯作为顶电极,去除剩余聚丙烯酸酯干膜,将全部材料浸入硫酸-过氧化氢棕氧化溶液中使得铜表面生成有机金属转化膜;将芯片焊接在固晶焊接区,并将引脚邦定在引脚邦线区的顶电极上;灌注封装环氧树脂材料,树脂固化成型后将铝基板完全腐蚀掉,得到如图1所示的封装结构,完成封装。
实施例3:
在镀锡氧化铝基板的锡层上涂覆聚丙烯酸酯湿膜,通过曝光图形转移,使得芯片固定区和引脚邦线区的线路槽露出;在图形化区基板露出部分镀2μm银作为底电极,在银底电极上继续镀45μm铜层;再次涂覆感光材料,并通过图形转移只露出引脚邦线区和芯片固定平台上的固晶焊接区的铜层,而芯片固定平台上固晶焊接区四周的铜层仍被感光材料覆盖;在引脚邦线区和固晶焊接区的铜层上镀2μm银作为顶电极,去除剩余聚丙烯酸酯干膜,将全部材料浸入氢氧化钠-亚硝酸钠-磷酸三钠黑氧化溶液中使得铜表面生成有机金属转化膜;将芯片焊接在固晶焊接区,并将引脚邦定在引脚邦线区的顶电极上;灌注封装环氧树脂材料,树脂固化成型后将镀锡氧化铝基板物理剥离,得到如图1所示的封装结构,完成封装。
实施例4:
在镜面不锈钢基板上涂覆聚丙烯酸酯湿膜,通过曝光图形转移,使得芯片固定区和引脚邦线区的线路槽露出;在图形化区不锈钢基板露出部分镀1μm金作为底电极,在银底电极上继续镀30μm铜层;再次涂覆感光材料,并通过图形转移只露出引脚邦线区和芯片固定平台上的固晶焊接区的铜层,而而芯片固定平台上固晶焊接区四周的铜层仍被感光材料覆盖;在引脚邦线区和固晶焊接区的铜层上镀2μm银作为顶电极,去除剩余聚丙烯酸酯干膜,将全部材料浸入氢氧化钠-亚硝酸钠-磷酸三钠黑氧化溶液中使得铜表面生成有机金属转化膜;将芯片焊接在固晶焊接区,并将引脚邦定在引脚邦线区的顶电极上;灌注封装环氧树脂材料,树脂固化成型后将镜面不锈钢基板物理剥离,得到如图1所示的封装结构,完成封装。

Claims (9)

1.一种稳固芯片的封装工艺,其特征在于:工艺过程包括:(1)在导电基板上涂覆感光材料;(2)感光材料图形转移,使得芯片固定平台和引脚邦线区的线路槽露出;(3)在图形化区基板露出部分镀底电极;(4)在底电极上继续镀铜层;(5)再次涂覆感光材料,并通过图形转移只露出引脚邦线区和芯片固定平台的固晶焊接区铜层,而芯片固定平台上固晶焊接区四周边缘的铜层仍被感光材料覆盖;(6)在引脚邦线区和固晶焊接区的铜层上镀顶电极;(7)去除剩余感光材料;(8)在铜层侧面以及芯片焊接平台上固晶焊接区四周的铜层顶面修饰有机金属转化膜;(9)将芯片焊接在固晶焊接区,并将引脚邦定在引脚邦线区的顶电极上;(10)灌注封装树脂材料,树脂固化成型后去除基板,露出底电极,完成封装。
2.根据权利要求1所述一种稳固芯片的封装工艺,其特征在于:所述感光材料聚丙烯酸酯类的干膜、湿膜。
3.根据权利要求1所述一种稳固芯片的封装工艺,其特征在于:所述底电极为标准电极电势高于铜的金属材料,顶电极为标准电极电势高于铜且易于焊接的金属。
4.根据权利要求3所述一种稳固芯片的封装工艺,其特征在于:所述标准电极电势高于铜的金属材料包括金、银、钯或其合金。
5.根据权利要求3所述一种稳固芯片的封装工艺,其特征在于:所述标准电极电势高于铜且易于焊接的金属包括金、银、钯或其合金。
6.根据权利要求1所述一种稳固芯片的封装工艺,其特征在于:所述芯片固定平台包括中间的固晶焊接区和固晶焊接区四周的区域,固晶焊接区镀有顶电极并与芯片焊接,固晶焊接区四周区域的铜层上没有顶电极。
7.根据权利要求1所述一种稳固芯片的封装工艺,其特征在于:铜层侧面以及芯片固定平台上固晶焊接区四周的铜层顶面修饰的有机金属转化膜采用棕氧化或黑氧化工艺在铜的表面反应来获取。
8.根据权利要求1所述一种稳固芯片的封装工艺,其特征在于:所述封装树脂材料环氧树脂。
9.根据权利要求1所述一种稳固芯片的封装工艺,其特征在于:所述导电基板为金属基板或镀有导电金属层的刚性基板,树脂固化成型后采用物理剥离或化学蚀刻的方式去除导电基板。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001217372A (ja) * 2000-06-28 2001-08-10 Sanyo Electric Co Ltd 回路装置およびその製造方法
CN1538518A (zh) * 2003-04-16 2004-10-20 �¹������ҵ��ʽ���� 导体衬底,半导体器件及其制造方法
CN1599046A (zh) * 2004-08-09 2005-03-23 江苏长电科技股份有限公司 集成电路或分立元件超薄无脚封装工艺及其封装结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001217372A (ja) * 2000-06-28 2001-08-10 Sanyo Electric Co Ltd 回路装置およびその製造方法
CN1538518A (zh) * 2003-04-16 2004-10-20 �¹������ҵ��ʽ���� 导体衬底,半导体器件及其制造方法
CN1599046A (zh) * 2004-08-09 2005-03-23 江苏长电科技股份有限公司 集成电路或分立元件超薄无脚封装工艺及其封装结构

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