CN109461663A - 一种集成电路封装工艺 - Google Patents

一种集成电路封装工艺 Download PDF

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CN109461663A
CN109461663A CN201811267250.6A CN201811267250A CN109461663A CN 109461663 A CN109461663 A CN 109461663A CN 201811267250 A CN201811267250 A CN 201811267250A CN 109461663 A CN109461663 A CN 109461663A
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汪元元
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Shenzhen Huili Creative Intelligence Technology Co Ltd
Shanghai Li Li Electronic Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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Abstract

本发明提出了一种新型的集成电路封装工艺,具有以下优势:(1)采用导电高分子涂层作为底电极,易于剥离和清洗,免去复杂昂贵的蚀刻金属基板工序,且基板可以重复利用;(2)通过增材法自下而上设计电极结构,可大量采用孤岛电极,显著增加集成电路封装I/O数;(3)通过黑氧化或棕氧化工艺,增强了顶电极和底电极之间的铜表面与封装树脂材料的结合,封装结构牢固。

Description

一种集成电路封装工艺
技术领域
本发明涉及一种集成电路封装工艺,本发明属于电子技术领域。
背景技术
方形扁平无引脚封装(Quad Flat No-lead Package,QFN)技术具有焊盘尺寸小、体积小、占有PCB区域小、元件厚度薄、非常低的阻抗、自感,可满足高速或者微波的应用等优点,广泛应用于芯片封装制造上。但QFN中部向四周连续布线,线宽受限于铜厚、且难以设计孤岛电极,增加I/O数会带来的生产成本和可靠性问题,限制了芯片和PCB板的设计自由度。基于以上缺点,我司发展了在金属基板上自下而上设计电极结构,封装完成后通过蚀刻去除金属板的工艺方式,大大提升了封装设计的自由度,但是,后期需要蚀刻掉金属基板,占用较多的工艺时间和成本,基板也无法重复利用。
发明内容
针对现有技术的不足,本发明提出了一种新型集成电路封装工艺,其特征在于:工艺过程包括:(1)在刚性基板上涂覆导电高分子涂层并烘干;(2)导电高分子涂层上涂覆感光材料,再通过图形转移露出线路槽;(3)在图形化区域有机导电涂层露出部分镀底电极;(4)在底电极上继续镀铜层;(5)在铜层上镀顶电极;(6)去除剩余感光材料;(7)在铜层侧面修饰有机金属转化膜;(8)将芯片邦定在顶电极上并灌注封装树脂材料;(9)树脂固化成型后剥离基板,用溶剂清洗封装树脂和底电极上附着的导电高分子,露出底电极,完成封装,基板清洗后可回收利用。
所述导电高分子为电导率超过1Scm-1的共轭高分子涂层,包括聚苯胺、聚吡咯、聚3,4-乙撑二氧噻吩中的一种或其组合,涂覆方式优选溶液旋涂或刮涂,烘干温度80~120摄氏度。
所述感光材料优选聚丙烯酸酯类的干膜、湿膜。
所述底电极为标准电极电势高于铜的金属材料,包括金、银、钯或其合金,顶电极为标准电极电势高于铜且易于焊接的金属,包括银、钯或其合金。
所述铜层侧面修饰有机金属转化膜采用棕氧化或黑氧化工艺在铜的表面反应来获取。
所述封装树脂材料为环氧树脂。
所述用溶剂清洗封装树脂和底电极上附着的导电高分子,溶剂采用N-甲基-2-吡咯烷酮。
本发明的优势在于:
(1)用导电高分子涂层作为底电极,易于剥离和清洗,免去复杂昂贵的蚀刻金属基板工序,且基板可以重复利用;
(2)通过增材法自下而上设计电极结构,可大量采用孤岛电极,显著增加集成电路封装I/O数;
(3)通过黑氧化或棕氧化工艺,增强了顶电极和底电极之间的铜表面与封装树脂材料的结合,封装结构牢固。
附图说明
图1采用本发明侧面金属镀层结构示意图。1-金属基板;2-导电高分子涂层;3-底电极;4-铜层;5-顶电极。
图2采用本发明工艺流程图。a-刚性基板涂敷导电高分子涂层并烘干;b-涂敷感光材料并图形化获得线路槽;c-镀底电极;d-镀铜层;e-镀顶电极;f-去除剩余感光材料并在铜层侧面修饰有机金属转化膜;g-邦线;h-灌注封装树脂;i-剥离基板,并清洗掉附着在封装树脂和底电极上的导电高分子。
具体实施方式
实施例1:
在FR4基板旋涂涂覆聚苯胺涂层,120摄氏度烘干,聚苯胺涂层上涂覆聚丙烯酸酯干膜,通过曝光图形转移,露出线路槽;在图形化区聚苯胺涂层上露出部分镀3μm银作为底电极,在银底电极上继续镀40μm铜层;在铜层上再镀3μm银作为顶电极,金属层侧面结构如图1所示。去除剩余聚丙烯酸酯干膜,将全部材料浸入硫酸-过氧化氢棕氧化溶液中使得铜表面生成有机金属转化膜,在芯片邦定在顶电极上后灌注环氧封装树脂材料,最后,FR4基板机械剥离,采用N-甲基-2-吡咯烷酮清洗封装树脂和底电极上附着的聚苯胺,露出银底电极完成封装。
实施例2:
在铜基板上旋涂涂覆聚吡咯涂层,110摄氏度烘干,聚吡咯涂层上涂覆聚丙烯酸酯湿膜,通过曝光图形转移,露出线路槽;在图形化区聚吡咯涂层露出部分镀2μm金作为底电极,在金底电极上继续镀50μm铜层;在铜层上再镀3μm银作为顶电极。去除剩余聚丙烯酸酯湿膜,将全部材料浸入硫酸-过氧化氢棕氧化溶液中使得顶电机和底电机之间铜层侧表面生成有机金属转化膜,在芯片邦定在顶电极上后灌注环氧封装树脂材料,最后,将铜基板机械剥离掉,采用N-甲基-2-吡咯烷酮清洗封装树脂和底电极上附着的聚吡咯,出金底电极完成封装。
实施例3:
在氧化铝基板上刮涂涂覆聚3,4-乙撑二氧噻吩涂层,80摄氏度烘干,聚3,4-乙撑二氧噻吩涂层上涂覆聚丙烯酸酯湿膜,通过曝光图形转移,露出线路槽;在图形化区锡层露出部分镀2μm银作为底电极,在银底电极上继续镀45μm铜层;在铜层上再镀2μm银作为顶电极。去除剩余聚丙烯酸酯湿膜,将全部材料浸入氢氧化钠-亚硝酸钠-磷酸三钠黑氧化溶液中使得铜表面生成有机金属转化膜,在芯片邦定在顶电极上后灌注环氧封装树脂材料,最后,将氧化铝基板机械剥离,采用N-甲基-2-吡咯烷酮清洗封装树脂和底电极上附着的聚3,4-乙撑二氧噻吩,露出银底电极完成封装。
实施例4:
在玻璃基板上刮涂涂覆聚3,4-乙撑二氧噻吩涂层,100摄氏度烘干,聚3,4-乙撑二氧噻吩涂层上涂覆聚丙烯酸酯湿膜,通过曝光图形转移,露出线路槽;在图形化区锡层露出部分镀1μm金作为底电极,在金底电极上继续镀30μm铜层;在铜层上再镀1μm银作为顶电极。去除剩余聚丙烯酸酯湿膜,将全部材料浸入氢氧化钠-亚硝酸钠-磷酸三钠黑氧化溶液中使得铜表面生成有机金属转化膜,在芯片邦定在顶电极上后灌注环氧封装树脂材料,最后,将玻璃基板机械剥离,采用N-甲基-2-吡咯烷酮清洗封装树脂和底电极上附着的聚3,4-乙撑二氧噻吩,露出金底电极完成封装。

Claims (7)

1.一种集成电路封装工艺,其特征在于:工艺过程包括:(1)在刚性基板上涂覆导电高分子涂层并烘干;(2)导电高分子涂层上涂覆感光材料,再通过图形转移露出线路槽;(3)在图形化区域有机导电涂层露出部分镀底电极;(4)在底电极上继续镀铜层;(5)在铜层上镀顶电极;(6)去除剩余感光材料;(7)在铜层侧面修饰有机金属转化膜;(8)将芯片邦定在顶电极上并灌注封装树脂材料;(9)树脂固化成型后剥离基板,用溶剂清洗封装树脂和底电极上附着的导电高分子,露出底电极,完成封装,基板清洗后可回收利用。
所述导电高分子为电导率超过1Scm-1的共轭高分子涂层,包括聚苯胺、聚吡咯、聚3,4-乙撑二氧噻吩中的一种或其组合,涂覆方式优选溶液旋涂或刮涂,烘干温度80~120摄氏度。
2.根据权利要求1所述一种集成电路封装工艺,其特征在于:所述感光材料优选聚丙烯酸酯类的干膜、湿膜。
3.根据权利要求1所述一种集成电路封装工艺,其特征在于:所述底电极为标准电极电势高于铜的金属材料,包括金、银、钯或其合金,顶电极为标准电极电势高于铜且易于焊接的金属,包括银、钯或其合金。
4.根据权利要求1所述一种集成电路封装工艺,其特征在于:所述铜层侧面修饰有机金属转化膜采用棕氧化或黑氧化工艺在铜的表面反应来获取。
5.根据权利要求1所述一种集成电路封装工艺,其特征在于:所述封装树脂材料为环氧树脂。
6.根据权利要求1所述一种集成电路封装工艺,其特征在于:所述用溶剂清洗封装树脂和底电极上附着的导电高分子,溶剂采用N-甲基-2-吡咯烷酮。
7.根据权利要求1~6任意一项所述集成电路封装工艺封装的集成电路。
CN201811267250.6A 2018-10-29 2018-10-29 一种集成电路封装工艺 Withdrawn CN109461663A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4328355A2 (en) 2022-08-23 2024-02-28 Indian Oil Corporation Limited Process of reusing bi-facial metal substrates for photoactive semiconductor materials for solar water splitting

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4328355A2 (en) 2022-08-23 2024-02-28 Indian Oil Corporation Limited Process of reusing bi-facial metal substrates for photoactive semiconductor materials for solar water splitting

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